300 lines
14 KiB
C
300 lines
14 KiB
C
/**************************************************************************//**
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* @file adc.h
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* @version V1.00
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* $Revision: 3 $
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* $Date: 15/06/03 9:34p $
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* @brief Mini58 series ADC driver header file
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*
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* @note
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* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __ADC_H__
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#define __ADC_H__
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
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@{
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*/
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/** @addtogroup Mini58_ADC_Driver ADC Driver
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@{
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*/
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/** @addtogroup Mini58_ADC_EXPORTED_CONSTANTS ADC Exported Constants
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@{
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*/
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#define ADC_CH7_EXT (0UL) /*!< Use external input pin as ADC channel 7 source */
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#define ADC_CH7_BGP (ADC_CHEN_CH7SEL_Msk) /*!< Use internal band-gap voltage (VBG) as channel 7 source. */
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#define ADC_CMP0_LESS_THAN (0UL << ADC_CMP0_CMPCOND_Pos) /*!< ADC compare condition less than */
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#define ADC_CMP1_LESS_THAN (0UL << ADC_CMP1_CMPCOND_Pos) /*!< ADC compare condition less than */
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#define ADC_CMP0_GREATER_OR_EQUAL_TO (1ul << ADC_CMP0_CMPCOND_Pos) /*!< ADC compare condition greater or equal to */
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#define ADC_CMP1_GREATER_OR_EQUAL_TO (1ul << ADC_CMP1_CMPCOND_Pos) /*!< ADC compare condition greater or equal to */
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#define ADC_TRIGGER_BY_EXT_PIN (0UL) /*!< ADC trigger by STADC (P3.2) pin */
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#define ADC_TRIGGER_BY_PWM (ADC_CTL_HWTRGSEL_Msk) /*!< ADC trigger by PWM events */
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#define ADC_FALLING_EDGE_TRIGGER (0UL) /*!< External pin falling edge trigger ADC */
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#define ADC_RISING_EDGE_TRIGGER (ADC_CTL_HWTRGCOND_Msk) /*!< External pin rising edge trigger ADC */
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#define ADC_ADIF_INT (ADC_STATUS_ADIF_Msk) /*!< ADC convert complete interrupt */
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#define ADC_CMP0_INT (ADC_STATUS_ADCMPF0_Msk) /*!< ADC comparator 0 interrupt */
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#define ADC_CMP1_INT (ADC_STATUS_ADCMPF1_Msk) /*!< ADC comparator 0 interrupt */
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#define ADC_SAMPLE_CLOCK_0 (0UL) /*!< ADC sample time is 0 ADC clock */
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#define ADC_SAMPLE_CLOCK_1 (1UL) /*!< ADC sample time is 1 ADC clock */
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#define ADC_SAMPLE_CLOCK_2 (2UL) /*!< ADC sample time is 2 ADC clock */
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#define ADC_SAMPLE_CLOCK_4 (3UL) /*!< ADC sample time is 4 ADC clock */
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#define ADC_SAMPLE_CLOCK_8 (4UL) /*!< ADC sample time is 8 ADC clock */
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#define ADC_SAMPLE_CLOCK_16 (5UL) /*!< ADC sample time is 16 ADC clock */
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#define ADC_SAMPLE_CLOCK_32 (6UL) /*!< ADC sample time is 32 ADC clock */
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#define ADC_SAMPLE_CLOCK_64 (7UL) /*!< ADC sample time is 64 ADC clock */
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#define ADC_SAMPLE_CLOCK_128 (8UL) /*!< ADC sample time is 128 ADC clock */
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#define ADC_SAMPLE_CLOCK_256 (9UL) /*!< ADC sample time is 256 ADC clock */
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#define ADC_SAMPLE_CLOCK_512 (10UL) /*!< ADC sample time is 512 ADC clock */
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#define ADC_SAMPLE_CLOCK_1024 (11UL) /*!< ADC sample time is 1024 ADC clock */
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#define ADC_SEQMODE_TYPE_23SHUNT (0UL) /*!< ADC sequential mode 23-shunt type */
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#define ADC_SEQMODE_TYPE_1SHUNT (1UL) /*!< ADC sequential mode 1-shunt type */
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#define ADC_SEQMODE_MODESELECT_CH01 (0UL) /*!< ADC channel 0 then channel 1 conversion */
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#define ADC_SEQMODE_MODESELECT_CH12 (1UL) /*!< ADC channel 1 then channel 2 conversion */
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#define ADC_SEQMODE_MODESELECT_CH02 (2UL) /*!< ADC channel 0 then channel 2 conversion */
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#define ADC_SEQMODE_PWM0_RISING (0UL) /*!< ADC sequential mode PWM0 rising trigger ADC*/
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#define ADC_SEQMODE_PWM0_CENTER (1UL) /*!< ADC sequential mode PWM0 center trigger ADC*/
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#define ADC_SEQMODE_PWM0_FALLING (2UL) /*!< ADC sequential mode PWM0 falling trigger ADC*/
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#define ADC_SEQMODE_PWM0_PERIOD (3UL) /*!< ADC sequential mode PWM0 period trigger ADC*/
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#define ADC_SEQMODE_PWM2_RISING (4UL) /*!< ADC sequential mode PWM2 rising trigger ADC*/
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#define ADC_SEQMODE_PWM2_CENTER (5UL) /*!< ADC sequential mode PWM2 center trigger ADC*/
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#define ADC_SEQMODE_PWM2_FALLING (6UL) /*!< ADC sequential mode PWM2 falling trigger ADC*/
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#define ADC_SEQMODE_PWM2_PERIOD (7UL) /*!< ADC sequential mode PWM2 period trigger ADC*/
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#define ADC_SEQMODE_PWM4_RISING (8UL) /*!< ADC sequential mode PWM4 rising trigger ADC*/
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#define ADC_SEQMODE_PWM4_CENTER (9UL) /*!< ADC sequential mode PWM4 center trigger ADC*/
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#define ADC_SEQMODE_PWM4_FALLING (10UL) /*!< ADC sequential mode PWM4 falling trigger ADC*/
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#define ADC_SEQMODE_PWM4_PERIOD (11UL) /*!< ADC sequential mode PWM4 period trigger ADC*/
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/*@}*/ /* end of group Mini58_ADC_EXPORTED_CONSTANTS */
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/** @addtogroup Mini58_ADC_EXPORTED_FUNCTIONS ADC Exported Functions
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@{
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*/
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/**
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* @brief Configure the analog input source of channel 7
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* @param[in] adc Base address of ADC module
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* @param[in] u32Source Decides the analog input source of channel 7, valid values are
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* - \ref ADC_CH7_EXT
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* - \ref ADC_CH7_BGP
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* @return None
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* @note While using VBG as channel 7 source, ADC module clock must /b not exceed 300kHz
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* \hideinitializer
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*/
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#define ADC_CONFIG_CH7(adc, u32Source) (ADC->CHEN = ((adc)->CHEN & ~ADC_CHEN_CH7SEL_Msk) | (u32Source))
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/**
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* @brief Get the latest ADC conversion data
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* @param[in] adc Base address of ADC module
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* @param[in] u32ChNum Currently not used
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* @return Latest ADC conversion data
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* \hideinitializer
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*/
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#define ADC_GET_CONVERSION_DATA(adc, u32ChNum) ((adc)->DAT & ADC_DAT_RESULT_Msk)
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/**
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* @brief Return the user-specified interrupt flags
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* @param[in] adc Base address of ADC module
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* @param[in] u32Mask The combination of following interrupt status bits. Each bit corresponds to a interrupt status.
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* - \ref ADC_ADIF_INT
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* - \ref ADC_CMP0_INT
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* - \ref ADC_CMP1_INT
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* @return User specified interrupt flags
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* \hideinitializer
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*/
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#define ADC_GET_INT_FLAG(adc, u32Mask) ((adc)->STATUS & (u32Mask))
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/**
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* @brief This macro clear the selected interrupt status bits
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* @param[in] adc Base address of ADC module
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* @param[in] u32Mask The combination of following interrupt status bits. Each bit corresponds to a interrupt status.
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* - \ref ADC_ADIF_INT
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* - \ref ADC_CMP0_INT
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* - \ref ADC_CMP1_INT
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* @return None
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* \hideinitializer
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*/
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#define ADC_CLR_INT_FLAG(adc, u32Mask) ((adc)->STATUS = ((adc)->STATUS & ~(ADC_STATUS_ADIF_Msk | \
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ADC_STATUS_ADCMPF0_Msk | \
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ADC_STATUS_ADCMPF1_Msk)) | (u32Mask))
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/**
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* @brief Get the busy state of ADC
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* @param[in] adc Base address of ADC module
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* @return busy state of ADC
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* @retval 0 ADC is not busy
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* @retval 1 ADC is busy
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* \hideinitializer
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*/
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#define ADC_IS_BUSY(adc) ((adc)->STATUS & ADC_STATUS_BUSY_Msk ? 1 : 0)
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/**
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* @brief Check if the ADC conversion data is over written or not
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* @param[in] adc Base address of ADC module
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* @param[in] u32ChNum Currently not used
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* @return Over run state of ADC data
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* @retval 0 ADC data is not overrun
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* @retval 1 ADC data is overrun
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* \hideinitializer
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*/
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#define ADC_IS_DATA_OVERRUN(adc, u32ChNum) ((adc)->STATUS & ADC_STATUS_OV_Msk ? 1 : 0)
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/**
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* @brief Check if the ADC conversion data is valid or not
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* @param[in] adc Base address of ADC module
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* @param[in] u32ChNum Currently not used
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* @return Valid state of ADC data
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* @retval 0 ADC data is not valid
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* @retval 1 ADC data us valid
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* \hideinitializer
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*/
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#define ADC_IS_DATA_VALID(adc, u32ChNum) ((adc)->STATUS & ADC_STATUS_VALID_Msk ? 1 : 0)
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/**
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* @brief Power down ADC module
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* @param[in] adc Base address of ADC module
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* @return None
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* \hideinitializer
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*/
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#define ADC_POWER_DOWN(adc) ((adc)->CTL &= ~ADC_CTL_ADCEN_Msk)
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/**
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* @brief Power on ADC module
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* @param[in] adc Base address of ADC module
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* @return None
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* \hideinitializer
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*/
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#define ADC_POWER_ON(adc) ((adc)->CTL |= ADC_CTL_ADCEN_Msk)
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/**
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* @brief Configure the comparator 0 and enable it
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* @param[in] adc Base address of ADC module
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* @param[in] u32ChNum Specifies the source channel, valid value are from 0 to 7
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* @param[in] u32Condition Specifies the compare condition
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* - \ref ADC_CMP0_LESS_THAN
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* - \ref ADC_CMP0_GREATER_OR_EQUAL_TO
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* @param[in] u32Data Specifies the compare value. Valid value are between 0 ~ 0x3FF
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* @param[in] u32MatchCount Specifies the match count setting, valid values are between 1~16
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* @return None
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* @details For example, ADC_ENABLE_CMP0(ADC, 5, ADC_CMP_GREATER_OR_EQUAL_TO, 0x800, 10);
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* Means ADC will assert comparator 0 flag if channel 5 conversion result is
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* greater or equal to 0x800 for 10 times continuously.
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* \hideinitializer
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*/
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#define ADC_ENABLE_CMP0(adc, \
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u32ChNum, \
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u32Condition, \
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u32Data, \
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u32MatchCount) (ADC->CMP0 = ((u32ChNum) << ADC_CMP0_CMPCH_Pos) | \
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(u32Condition) | \
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((u32Data) << ADC_CMP0_CMPDAT_Pos) | \
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(((u32MatchCount) - 1) << ADC_CMP0_CMPMCNT_Pos) |\
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ADC_CMP0_ADCMPIE_Msk |\
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ADC_CMP0_ADCMPEN_Msk)
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/**
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* @brief Disable comparator 0
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* @param[in] adc Base address of ADC module
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* \hideinitializer
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*/
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#define ADC_DISABLE_CMP0(adc) ((adc)->CMP0 = 0)
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/**
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* @brief Configure the comparator 1 and enable it
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* @param[in] adc Base address of ADC module
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* @param[in] u32ChNum Specifies the source channel, valid value are from 0 to 7
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* @param[in] u32Condition Specifies the compare condition
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* - \ref ADC_CMP1_LESS_THAN
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* - \ref ADC_CMP1_GREATER_OR_EQUAL_TO
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* @param[in] u32Data Specifies the compare value. Valid value are between 0 ~ 0x3FF
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* @param[in] u32MatchCount Specifies the match count setting, valid values are between 1~16
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* @return None
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* @details For example, ADC_ENABLE_CMP1(ADC, 5, ADC_CMP1_GREATER_OR_EQUAL_TO, 0x800, 10);
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* Means ADC will assert comparator 1 flag if channel 5 conversion result is
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* greater or equal to 0x800 for 10 times continuously.
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* \hideinitializer
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*/
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#define ADC_ENABLE_CMP1(adc, \
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u32ChNum, \
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u32Condition, \
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u32Data, \
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u32MatchCount) (ADC->CMP1 = ((u32ChNum) << ADC_CMP1_CMPCH_Pos) | \
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(u32Condition) | \
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((u32Data) << ADC_CMP1_CMPDAT_Pos) | \
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((u32MatchCount - 1) << ADC_CMP1_CMPMCNT_Pos) |\
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ADC_CMP1_ADCMPEN_Msk)
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/**
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* @brief Disable comparator 1
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* @param[in] adc Base address of ADC module
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* \hideinitializer
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*/
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#define ADC_DISABLE_CMP1(adc) ((adc)->CMP1 = 0)
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/**
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* @brief Set ADC input channel. Enabled channel will be converted while ADC starts.
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* @param[in] adc Base address of ADC module
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* @param[in] u32Mask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1...
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* @return None
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* @note Mini58 series MCU ADC can only convert 1 channel at a time. If more than 1 channels are enabled, only channel
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* with smallest number will be convert.
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* \hideinitializer
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*/
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#define ADC_SET_INPUT_CHANNEL(adc, u32Mask) ((adc)->CHEN = (ADC->CHEN & ~ADC_CHEN_CHEN0_Msk) | (u32Mask))
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/**
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* @brief Start the A/D conversion.
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* @param[in] adc Base address of ADC module
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* @return None
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* \hideinitializer
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*/
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#define ADC_START_CONV(adc) ((adc)->CTL |= ADC_CTL_SWTRG_Msk)
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/**
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* @brief Stop the A/D conversion.
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* @param[in] adc Base address of ADC module
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* @return None
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* \hideinitializer
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*/
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#define ADC_STOP_CONV(adc) ((adc)->CTL &= ~ADC_CTL_SWTRG_Msk)
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void ADC_Open(ADC_T *adc,
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uint32_t u32InputMode,
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uint32_t u32OpMode,
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uint32_t u32ChMask);
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void ADC_Close(ADC_T *adc);
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void ADC_EnableHWTrigger(ADC_T *adc,
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uint32_t u32Source,
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uint32_t u32Param);
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void ADC_DisableHWTrigger(ADC_T *adc);
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void ADC_SetExtraSampleTime(ADC_T *adc,
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uint32_t u32ChNum,
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uint32_t u32SampleTime);
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void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask);
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void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask);
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void ADC_SeqModeEnable(ADC_T *adc, uint32_t u32SeqTYPE, uint32_t u32ModeSel);
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void ADC_SeqModeTriggerSrc(ADC_T *adc, uint32_t u32SeqModeTriSrc1, uint32_t u32SeqModeTriSrc2);
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/*@}*/ /* end of group Mini58_ADC_EXPORTED_FUNCTIONS */
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/*@}*/ /* end of group Mini58_ADC_Driver */
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/*@}*/ /* end of group Mini58_Device_Driver */
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#ifdef __cplusplus
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}
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#endif
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#endif //__ADC_H__
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/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
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