16640 lines
55 KiB
OpenEdge ABL
16640 lines
55 KiB
OpenEdge ABL
#line 1 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Source\\system_Mini58Series.c"
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#line 1 "D:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h"
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#line 27 "D:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h"
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#line 46 "D:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h"
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typedef signed char int8_t;
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typedef signed short int int16_t;
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typedef signed int int32_t;
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typedef signed __int64 int64_t;
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typedef unsigned char uint8_t;
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typedef unsigned short int uint16_t;
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typedef unsigned int uint32_t;
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typedef unsigned __int64 uint64_t;
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typedef signed char int_least8_t;
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typedef signed short int int_least16_t;
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typedef signed int int_least32_t;
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typedef signed __int64 int_least64_t;
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typedef unsigned char uint_least8_t;
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typedef unsigned short int uint_least16_t;
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typedef unsigned int uint_least32_t;
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typedef unsigned __int64 uint_least64_t;
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typedef signed int int_fast8_t;
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typedef signed int int_fast16_t;
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typedef signed int int_fast32_t;
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typedef signed __int64 int_fast64_t;
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typedef unsigned int uint_fast8_t;
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typedef unsigned int uint_fast16_t;
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typedef unsigned int uint_fast32_t;
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typedef unsigned __int64 uint_fast64_t;
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typedef signed int intptr_t;
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typedef unsigned int uintptr_t;
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typedef signed long long intmax_t;
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typedef unsigned long long uintmax_t;
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#line 216 "D:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h"
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#line 241 "D:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h"
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#line 305 "D:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h"
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#line 13 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Source\\system_Mini58Series.c"
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#line 1 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Include\\Mini58Series.h"
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typedef enum IRQn {
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NonMaskableInt_IRQn = -14,
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HardFault_IRQn = -13,
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SVCall_IRQn = -5,
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PendSV_IRQn = -2,
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SysTick_IRQn = -1,
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BOD_IRQn = 0,
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WDT_IRQn = 1,
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EINT0_IRQn = 2,
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EINT1_IRQn = 3,
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GPIO01_IRQn = 4,
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GPIO234_IRQn = 5,
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PWM_IRQn = 6,
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FB_IRQn = 7,
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TMR0_IRQn = 8,
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TMR1_IRQn = 9,
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UART0_IRQn = 12,
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UART1_IRQn = 13,
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SPI_IRQn = 14,
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GPIO5_IRQn = 16,
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HIRC_IRQn = 17,
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I2C0_IRQn = 18,
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I2C1_IRQn = 19,
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ACMP_IRQn = 25,
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PDWU_IRQn = 28,
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ADC_IRQn = 29
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} IRQn_Type;
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#line 1 "..\\..\\..\\Library\\CMSIS\\Include\\core_cm0.h"
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#line 45 "..\\..\\..\\Library\\CMSIS\\Include\\core_cm0.h"
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#line 120 "..\\..\\..\\Library\\CMSIS\\Include\\core_cm0.h"
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#line 162 "..\\..\\..\\Library\\CMSIS\\Include\\core_cm0.h"
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#line 1 "..\\..\\..\\Library\\CMSIS\\Include\\core_cmInstr.h"
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#line 1 "..\\..\\..\\Library\\CMSIS\\Include\\cmsis_armcc.h"
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static __inline uint32_t __get_CONTROL(void)
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{
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register uint32_t __regControl __asm("control");
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return(__regControl);
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}
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static __inline void __set_CONTROL(uint32_t control)
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{
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register uint32_t __regControl __asm("control");
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__regControl = control;
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}
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static __inline uint32_t __get_IPSR(void)
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{
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register uint32_t __regIPSR __asm("ipsr");
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return(__regIPSR);
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}
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static __inline uint32_t __get_APSR(void)
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{
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register uint32_t __regAPSR __asm("apsr");
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return(__regAPSR);
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}
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static __inline uint32_t __get_xPSR(void)
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{
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register uint32_t __regXPSR __asm("xpsr");
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return(__regXPSR);
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}
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static __inline uint32_t __get_PSP(void)
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{
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register uint32_t __regProcessStackPointer __asm("psp");
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return(__regProcessStackPointer);
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}
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static __inline void __set_PSP(uint32_t topOfProcStack)
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{
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register uint32_t __regProcessStackPointer __asm("psp");
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__regProcessStackPointer = topOfProcStack;
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}
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static __inline uint32_t __get_MSP(void)
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{
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register uint32_t __regMainStackPointer __asm("msp");
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return(__regMainStackPointer);
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}
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static __inline void __set_MSP(uint32_t topOfMainStack)
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{
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register uint32_t __regMainStackPointer __asm("msp");
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__regMainStackPointer = topOfMainStack;
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}
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static __inline uint32_t __get_PRIMASK(void)
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{
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register uint32_t __regPriMask __asm("primask");
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return(__regPriMask);
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}
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static __inline void __set_PRIMASK(uint32_t priMask)
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{
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register uint32_t __regPriMask __asm("primask");
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__regPriMask = (priMask);
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}
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#line 263 "..\\..\\..\\Library\\CMSIS\\Include\\cmsis_armcc.h"
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#line 297 "..\\..\\..\\Library\\CMSIS\\Include\\cmsis_armcc.h"
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__attribute__((section(".rev16_text"))) static __inline __asm uint32_t __REV16(uint32_t value)
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{
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rev16 r0, r0
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bx lr
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}
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__attribute__((section(".revsh_text"))) static __inline __asm int32_t __REVSH(int32_t value)
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{
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revsh r0, r0
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bx lr
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}
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__attribute__((always_inline)) static __inline uint32_t __RBIT(uint32_t value)
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{
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uint32_t result;
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int32_t s = 4 * 8 - 1;
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result = value;
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for (value >>= 1U; value; value >>= 1U)
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{
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result <<= 1U;
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result |= value & 1U;
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s--;
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}
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result <<= s;
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return(result);
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}
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#line 649 "..\\..\\..\\Library\\CMSIS\\Include\\cmsis_armcc.h"
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#line 731 "..\\..\\..\\Library\\CMSIS\\Include\\cmsis_armcc.h"
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#line 54 "..\\..\\..\\Library\\CMSIS\\Include\\core_cmInstr.h"
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#line 84 "..\\..\\..\\Library\\CMSIS\\Include\\core_cmInstr.h"
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#line 164 "..\\..\\..\\Library\\CMSIS\\Include\\core_cm0.h"
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#line 1 "..\\..\\..\\Library\\CMSIS\\Include\\core_cmFunc.h"
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#line 54 "..\\..\\..\\Library\\CMSIS\\Include\\core_cmFunc.h"
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#line 84 "..\\..\\..\\Library\\CMSIS\\Include\\core_cmFunc.h"
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#line 165 "..\\..\\..\\Library\\CMSIS\\Include\\core_cm0.h"
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#line 198 "..\\..\\..\\Library\\CMSIS\\Include\\core_cm0.h"
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#line 214 "..\\..\\..\\Library\\CMSIS\\Include\\core_cm0.h"
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typedef union
|
|
{
|
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struct
|
|
{
|
|
uint32_t _reserved0:28;
|
|
uint32_t V:1;
|
|
uint32_t C:1;
|
|
uint32_t Z:1;
|
|
uint32_t N:1;
|
|
} b;
|
|
uint32_t w;
|
|
} APSR_Type;
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typedef union
|
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{
|
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struct
|
|
{
|
|
uint32_t ISR:9;
|
|
uint32_t _reserved0:23;
|
|
} b;
|
|
uint32_t w;
|
|
} IPSR_Type;
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typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t ISR:9;
|
|
uint32_t _reserved0:15;
|
|
uint32_t T:1;
|
|
uint32_t _reserved1:3;
|
|
uint32_t V:1;
|
|
uint32_t C:1;
|
|
uint32_t Z:1;
|
|
uint32_t N:1;
|
|
} b;
|
|
uint32_t w;
|
|
} xPSR_Type;
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typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t _reserved0:1;
|
|
uint32_t SPSEL:1;
|
|
uint32_t _reserved1:30;
|
|
} b;
|
|
uint32_t w;
|
|
} CONTROL_Type;
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typedef struct
|
|
{
|
|
volatile uint32_t ISER[1U];
|
|
uint32_t RESERVED0[31U];
|
|
volatile uint32_t ICER[1U];
|
|
uint32_t RSERVED1[31U];
|
|
volatile uint32_t ISPR[1U];
|
|
uint32_t RESERVED2[31U];
|
|
volatile uint32_t ICPR[1U];
|
|
uint32_t RESERVED3[31U];
|
|
uint32_t RESERVED4[64U];
|
|
volatile uint32_t IP[8U];
|
|
} NVIC_Type;
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|
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typedef struct
|
|
{
|
|
volatile const uint32_t CPUID;
|
|
volatile uint32_t ICSR;
|
|
uint32_t RESERVED0;
|
|
volatile uint32_t AIRCR;
|
|
volatile uint32_t SCR;
|
|
volatile uint32_t CCR;
|
|
uint32_t RESERVED1;
|
|
volatile uint32_t SHP[2U];
|
|
volatile uint32_t SHCSR;
|
|
} SCB_Type;
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|
|
typedef struct
|
|
{
|
|
volatile uint32_t CTRL;
|
|
volatile uint32_t LOAD;
|
|
volatile uint32_t VAL;
|
|
volatile const uint32_t CALIB;
|
|
} SysTick_Type;
|
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|
|
static __inline void NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static __inline void NVIC_DisableIRQ(IRQn_Type IRQn)
|
|
{
|
|
((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
|
}
|
|
|
|
|
|
|
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|
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|
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|
|
|
|
|
|
|
|
static __inline uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
|
{
|
|
return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static __inline void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
|
{
|
|
((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static __inline void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
|
{
|
|
((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static __inline void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
if ((int32_t)(IRQn) < 0)
|
|
{
|
|
((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )] = ((uint32_t)(((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )] & ~(0xFFUL << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))) |
|
|
(((priority << (8U - 2)) & (uint32_t)0xFFUL) << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)));
|
|
}
|
|
else
|
|
{
|
|
((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )] = ((uint32_t)(((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )] & ~(0xFFUL << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))) |
|
|
(((priority << (8U - 2)) & (uint32_t)0xFFUL) << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)));
|
|
}
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static __inline uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
|
{
|
|
|
|
if ((int32_t)(IRQn) < 0)
|
|
{
|
|
return((uint32_t)(((((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )] >> ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) ) & (uint32_t)0xFFUL) >> (8U - 2)));
|
|
}
|
|
else
|
|
{
|
|
return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[ ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )] >> ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) ) & (uint32_t)0xFFUL) >> (8U - 2)));
|
|
}
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static __inline void NVIC_SystemReset(void)
|
|
{
|
|
do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U);
|
|
|
|
((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR = ((0x5FAUL << 16U) |
|
|
(1UL << 2U));
|
|
do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U);
|
|
|
|
for(;;)
|
|
{
|
|
__nop();
|
|
}
|
|
}
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
static __inline uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
if ((ticks - 1UL) > (0xFFFFFFUL ))
|
|
{
|
|
return (1UL);
|
|
}
|
|
|
|
((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->LOAD = (uint32_t)(ticks - 1UL);
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << 2) - 1UL);
|
|
((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->VAL = 0UL;
|
|
((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->CTRL = (1UL << 2U) |
|
|
(1UL << 1U) |
|
|
(1UL );
|
|
return (0UL);
|
|
}
|
|
|
|
|
|
|
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|
|
|
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|
|
|
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|
|
|
|
|
|
|
|
|
|
|
#line 134 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Include\\Mini58Series.h"
|
|
#line 1 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Include\\system_Mini58Series.h"
|
|
|
|
|
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|
|
#line 33 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Include\\system_Mini58Series.h"
|
|
|
|
extern uint32_t __HSI;
|
|
extern uint32_t SystemCoreClock;
|
|
extern uint32_t CyclesPerUs;
|
|
extern uint32_t PllClock;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
extern void SystemCoreClockUpdate (void);
|
|
extern void SystemInit (void);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#line 135 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Include\\Mini58Series.h"
|
|
#line 136 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Include\\Mini58Series.h"
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#pragma anon_unions
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
typedef struct {
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
volatile uint32_t CTL[2];
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
volatile uint32_t STATUS;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
volatile uint32_t VREF;
|
|
|
|
} ACMP_T;
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
typedef struct {
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
volatile const uint32_t DAT;
|
|
|
|
volatile const uint32_t RESERVED0[7];
|
|
|
|
|
|
|
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|
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|
|
|
|
|
|
volatile uint32_t CTL;
|
|
|
|
|
|
|
|
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volatile uint32_t CHEN;
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volatile uint32_t CMP0;
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volatile uint32_t CMP1;
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volatile uint32_t STATUS;
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|
|
volatile const uint32_t RESERVED1[4];
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volatile uint32_t TRGDLY;
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volatile uint32_t EXTSMPT;
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volatile uint32_t SEQCTL;
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|
volatile const uint32_t SEQDAT1;
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|
volatile const uint32_t SEQDAT2;
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|
|
} ADC_T;
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|
typedef struct {
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volatile uint32_t PWRCTL;
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volatile uint32_t AHBCLK;
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volatile uint32_t APBCLK;
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volatile uint32_t STATUS;
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volatile uint32_t CLKSEL0;
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volatile uint32_t CLKSEL1;
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volatile uint32_t CLKDIV;
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volatile uint32_t CLKSEL2;
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volatile uint32_t PLLCTL;
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volatile uint32_t CLKOCTL;
|
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|
|
} CLK_T;
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|
typedef struct {
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volatile uint32_t ISPCTL;
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volatile uint32_t ISPADDR;
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volatile uint32_t ISPDAT;
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volatile uint32_t ISPCMD;
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volatile uint32_t ISPTRG;
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volatile const uint32_t DFBA;
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volatile uint32_t FATCTL;
|
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|
|
volatile const uint32_t RESERVED0[9];
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volatile const uint32_t ISPSTS;
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|
|
} FMC_T;
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|
typedef struct {
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|
volatile uint32_t MODE;
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volatile uint32_t DINOFF;
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volatile uint32_t DOUT;
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volatile uint32_t DATMSK;
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volatile const uint32_t PIN;
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|
volatile uint32_t DBEN;
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|
volatile uint32_t INTTYPE;
|
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|
volatile uint32_t INTEN;
|
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|
volatile uint32_t INTSRC;
|
|
|
|
} GPIO_T;
|
|
|
|
typedef struct {
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|
volatile uint32_t DBCTL;
|
|
|
|
} GPIO_DB_T;
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|
typedef struct {
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|
volatile uint32_t CTL;
|
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|
volatile uint32_t ADDR0;
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|
volatile uint32_t DAT;
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|
volatile const uint32_t STATUS;
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|
volatile uint32_t CLKDIV;
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|
volatile uint32_t TOCTL;
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|
volatile uint32_t ADDR1;
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|
volatile uint32_t ADDR2;
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|
volatile uint32_t ADDR3;
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|
volatile uint32_t ADDRMSK0;
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|
volatile uint32_t ADDRMSK1;
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|
volatile uint32_t ADDRMSK2;
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|
|
volatile uint32_t ADDRMSK3;
|
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|
|
volatile const uint32_t RESERVED0[2];
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|
volatile uint32_t CTL1;
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|
volatile uint32_t STATUS1;
|
|
|
|
} I2C_T;
|
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|
|
typedef struct {
|
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|
|
volatile const uint32_t IRQ0_SRC;
|
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|
|
volatile const uint32_t IRQ1_SRC;
|
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|
|
volatile const uint32_t IRQ2_SRC;
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|
|
volatile const uint32_t IRQ3_SRC;
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|
|
volatile const uint32_t IRQ4_SRC;
|
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|
|
volatile const uint32_t IRQ5_SRC;
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|
volatile const uint32_t IRQ6_SRC;
|
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|
|
volatile const uint32_t IRQ7_SRC;
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|
volatile const uint32_t IRQ8_SRC;
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|
|
volatile const uint32_t IRQ9_SRC;
|
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|
|
uint32_t RESERVE0[2];
|
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|
volatile const uint32_t IRQ12_SRC;
|
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|
|
volatile const uint32_t IRQ13_SRC;
|
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|
|
volatile const uint32_t IRQ14_SRC;
|
|
|
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|
|
uint32_t RESERVE1[1];
|
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|
volatile const uint32_t IRQ16_SRC;
|
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|
|
volatile const uint32_t IRQ17_SRC;
|
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|
volatile const uint32_t IRQ18_SRC;
|
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|
|
volatile const uint32_t IRQ19_SRC;
|
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|
|
uint32_t RESERVE2[5];
|
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|
|
volatile const uint32_t IRQ25_SRC;
|
|
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|
|
uint32_t RESERVE3[2];
|
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|
|
volatile const uint32_t IRQ28_SRC;
|
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|
volatile const uint32_t IRQ29_SRC;
|
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|
volatile uint32_t CON;
|
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|
|
volatile uint32_t IRQ;
|
|
|
|
} INTR_T;
|
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|
typedef struct {
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|
volatile uint32_t CLKPSC;
|
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|
volatile uint32_t CLKDIV;
|
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|
|
volatile uint32_t CTL;
|
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|
volatile uint32_t PERIOD0;
|
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|
volatile uint32_t PERIOD1;
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|
volatile uint32_t PERIOD2;
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|
volatile uint32_t PERIOD3;
|
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|
volatile uint32_t PERIOD4;
|
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|
volatile uint32_t PERIOD5;
|
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|
|
|
|
|
|
volatile uint32_t CMPDAT0;
|
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|
|
|
|
|
|
volatile uint32_t CMPDAT1;
|
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|
|
|
|
|
|
|
volatile uint32_t CMPDAT2;
|
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|
|
|
|
|
|
|
volatile uint32_t CMPDAT3;
|
|
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|
|
|
|
|
|
|
|
volatile uint32_t CMPDAT4;
|
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|
|
volatile uint32_t CMPDAT5;
|
|
|
|
volatile const uint32_t RESERVED0[6];
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|
volatile uint32_t INTEN;
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volatile uint32_t INTSTS;
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|
volatile uint32_t POEN;
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|
volatile uint32_t BRKCTL;
|
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|
volatile uint32_t DTCTL;
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|
volatile uint32_t ADCTCTL0;
|
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|
volatile uint32_t ADCTCTL1;
|
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|
volatile uint32_t ADCTSTS0;
|
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|
volatile uint32_t ADCTSTS1;
|
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|
|
volatile uint32_t PHCHG;
|
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|
volatile uint32_t PHCHGNXT;
|
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|
volatile uint32_t PHCHGMSK;
|
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|
volatile uint32_t IFA;
|
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|
volatile uint32_t PCACTL;
|
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|
volatile uint32_t MSKALIGN;
|
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|
|
} PWM_T;
|
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typedef struct {
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|
volatile uint32_t CTL;
|
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|
|
volatile uint32_t CLKDIV;
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|
volatile uint32_t SSCTL;
|
|
|
|
volatile const uint32_t RESERVED0[1];
|
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|
|
volatile const uint32_t RX;
|
|
|
|
volatile const uint32_t RESERVED1[3];
|
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|
|
volatile uint32_t TX;
|
|
|
|
volatile const uint32_t RESERVED2[6];
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|
|
volatile uint32_t SLVCTL;
|
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|
volatile uint32_t FIFOCTL;
|
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|
|
volatile uint32_t STATUS;
|
|
|
|
} SPI_T;
|
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|
|
typedef struct {
|
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|
|
|
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|
|
volatile const uint32_t PDID;
|
|
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|
|
volatile uint32_t RSTSTS;
|
|
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|
|
volatile uint32_t IPRST0;
|
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|
|
volatile uint32_t IPRST1;
|
|
|
|
volatile const uint32_t RESERVED0[2];
|
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|
|
volatile uint32_t BODCTL;
|
|
|
|
volatile const uint32_t RESERVED1[5];
|
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|
|
volatile uint32_t P0_MFP;
|
|
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|
volatile uint32_t P1_MFP;
|
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volatile uint32_t P2_MFP;
|
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volatile uint32_t P3_MFP;
|
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volatile uint32_t P4_MFP;
|
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volatile uint32_t P5_MFP;
|
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|
|
volatile const uint32_t RESERVED2[14];
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|
volatile uint32_t IRCTCTL;
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|
volatile uint32_t IRCTIEN;
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|
volatile uint32_t IRCTISTS;
|
|
|
|
volatile const uint32_t RESERVED3[29];
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|
volatile uint32_t REGLCTL;
|
|
|
|
} SYS_T;
|
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|
typedef struct {
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|
volatile uint32_t CTL;
|
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|
|
volatile uint32_t CMP;
|
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|
|
volatile uint32_t INTSTS;
|
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|
|
volatile const uint32_t CNT;
|
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|
|
volatile const uint32_t CAP;
|
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|
volatile uint32_t EXTCTL;
|
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|
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|
|
volatile uint32_t EINTSTS;
|
|
|
|
} TIMER_T;
|
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|
typedef struct {
|
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|
|
volatile uint32_t DAT;
|
|
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|
|
volatile uint32_t INTEN;
|
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|
|
volatile uint32_t FIFO;
|
|
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|
|
volatile uint32_t LINE;
|
|
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|
|
volatile uint32_t MODEM;
|
|
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|
|
volatile uint32_t MODEMSTS;
|
|
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|
|
volatile uint32_t FIFOSTS;
|
|
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|
|
volatile uint32_t INTSTS;
|
|
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|
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|
|
volatile uint32_t TOUT;
|
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|
|
volatile uint32_t BAUD;
|
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|
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|
|
volatile uint32_t IRDA;
|
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|
|
volatile uint32_t ALTCTL;
|
|
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|
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|
|
volatile uint32_t FUNSEL;
|
|
|
|
} UART_T;
|
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|
|
typedef struct {
|
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|
|
volatile uint32_t CTL;
|
|
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|
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|
|
volatile uint32_t ALTCTL;
|
|
|
|
} WDT_T;
|
|
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|
|
typedef struct {
|
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|
|
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|
|
volatile uint32_t RLDCNT;
|
|
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|
|
volatile uint32_t CTL;
|
|
|
|
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|
|
volatile uint32_t STATUS;
|
|
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|
|
volatile const uint32_t CNT;
|
|
|
|
} WWDT_T;
|
|
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|
|
#pragma no_anon_unions
|
|
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|
|
#line 11669 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Include\\Mini58Series.h"
|
|
|
|
#line 11688 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Include\\Mini58Series.h"
|
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|
|
#line 11712 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Include\\Mini58Series.h"
|
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|
|
#line 11724 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Include\\Mini58Series.h"
|
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|
|
typedef volatile unsigned char vu8;
|
|
typedef volatile unsigned short vu16;
|
|
typedef volatile unsigned long vu32;
|
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|
|
#line 11912 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Include\\Mini58Series.h"
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|
|
#line 1 "..\\..\\..\\Library\\StdDriver\\inc\\sys.h"
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|
|
#line 44 "..\\..\\..\\Library\\StdDriver\\inc\\sys.h"
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|
|
#line 55 "..\\..\\..\\Library\\StdDriver\\inc\\sys.h"
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|
|
#line 106 "..\\..\\..\\Library\\StdDriver\\inc\\sys.h"
|
|
|
|
#line 113 "..\\..\\..\\Library\\StdDriver\\inc\\sys.h"
|
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|
|
#line 120 "..\\..\\..\\Library\\StdDriver\\inc\\sys.h"
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|
#line 168 "..\\..\\..\\Library\\StdDriver\\inc\\sys.h"
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|
|
static __inline void SYS_UnlockReg(void)
|
|
{
|
|
do
|
|
{
|
|
((SYS_T *) (((uint32_t)0x50000000) + 0x00000))->REGLCTL = 0x59;
|
|
((SYS_T *) (((uint32_t)0x50000000) + 0x00000))->REGLCTL = 0x16;
|
|
((SYS_T *) (((uint32_t)0x50000000) + 0x00000))->REGLCTL = 0x88;
|
|
}
|
|
while(((SYS_T *) (((uint32_t)0x50000000) + 0x00000))->REGLCTL == 0);
|
|
}
|
|
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|
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static __inline void SYS_LockReg(void)
|
|
{
|
|
((SYS_T *) (((uint32_t)0x50000000) + 0x00000))->REGLCTL = 0;
|
|
}
|
|
|
|
void SYS_ClearResetSrc(uint32_t u32Src);
|
|
uint32_t SYS_GetBODStatus(void);
|
|
uint32_t SYS_GetResetSrc(void);
|
|
uint32_t SYS_IsRegLocked(void);
|
|
uint32_t SYS_ReadPDID(void);
|
|
void SYS_ResetChip(void);
|
|
void SYS_ResetCPU(void);
|
|
void SYS_ResetModule(uint32_t u32ModuleIndex);
|
|
void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel);
|
|
void SYS_DisableBOD(void);
|
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#line 11937 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Include\\Mini58Series.h"
|
|
#line 1 "..\\..\\..\\Library\\StdDriver\\inc\\clk.h"
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#line 41 "..\\..\\..\\Library\\StdDriver\\inc\\clk.h"
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#line 65 "..\\..\\..\\Library\\StdDriver\\inc\\clk.h"
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#line 95 "..\\..\\..\\Library\\StdDriver\\inc\\clk.h"
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#line 109 "..\\..\\..\\Library\\StdDriver\\inc\\clk.h"
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#line 152 "..\\..\\..\\Library\\StdDriver\\inc\\clk.h"
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#line 161 "..\\..\\..\\Library\\StdDriver\\inc\\clk.h"
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#line 180 "..\\..\\..\\Library\\StdDriver\\inc\\clk.h"
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|
|
static __inline uint32_t CLK_GetPLLClockFreq(void)
|
|
{
|
|
uint32_t u32PllFreq = 0, u32PllReg;
|
|
uint32_t u32FIN, u32NF, u32NR, u32NO;
|
|
uint8_t au8NoTbl[4] = {1, 2, 2, 4};
|
|
|
|
u32PllReg = ((CLK_T *) (((uint32_t)0x50000000) + 0x00200))->PLLCTL;
|
|
|
|
if(u32PllReg & ((0x1ul << (16)) | (0x1ul << (18))))
|
|
return 0;
|
|
|
|
if(u32PllReg & 0x00080000UL)
|
|
u32FIN = (22118400UL);
|
|
else
|
|
u32FIN = (12000000UL);
|
|
|
|
if(u32PllReg & (0x1ul << (17)))
|
|
return u32FIN;
|
|
|
|
|
|
u32NO = au8NoTbl[((u32PllReg & (0x3ul << (14))) >> (14))];
|
|
u32NF = ((u32PllReg & (0x1fful << (0))) >> (0)) + 2;
|
|
u32NR = ((u32PllReg & (0x1ful << (9))) >> (9)) + 2;
|
|
|
|
|
|
u32PllFreq = (((u32FIN >> 2) * u32NF) / (u32NR * u32NO) << 2);
|
|
|
|
return u32PllFreq;
|
|
}
|
|
|
|
void CLK_DisableCKO(void);
|
|
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
|
|
void CLK_PowerDown(void);
|
|
void CLK_Idle(void);
|
|
uint32_t CLK_GetHXTFreq(void);
|
|
uint32_t CLK_GetLXTFreq(void);
|
|
uint32_t CLK_GetHCLKFreq(void);
|
|
uint32_t CLK_GetCPUFreq(void);
|
|
uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
|
|
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
|
|
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
|
|
void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
|
|
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
|
|
void CLK_DisableSysTick(void);
|
|
void CLK_EnableXtalRC(uint32_t u32ClkMask);
|
|
void CLK_DisableXtalRC(uint32_t u32ClkMask);
|
|
void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
|
|
void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
|
|
void CLK_SysTickDelay(uint32_t us);
|
|
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
|
|
void CLK_DisablePLL(void);
|
|
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
|
|
|
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|
|
#line 11938 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Include\\Mini58Series.h"
|
|
#line 1 "..\\..\\..\\Library\\StdDriver\\inc\\acmp.h"
|
|
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|
|
#line 72 "..\\..\\..\\Library\\StdDriver\\inc\\acmp.h"
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|
|
#line 116 "..\\..\\..\\Library\\StdDriver\\inc\\acmp.h"
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|
|
|
|
|
|
|
void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysteresisEn);
|
|
void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum);
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
#line 11939 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Include\\Mini58Series.h"
|
|
#line 1 "..\\..\\..\\Library\\StdDriver\\inc\\adc.h"
|
|
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|
|
#line 74 "..\\..\\..\\Library\\StdDriver\\inc\\adc.h"
|
|
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|
|
#line 202 "..\\..\\..\\Library\\StdDriver\\inc\\adc.h"
|
|
|
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|
|
#line 234 "..\\..\\..\\Library\\StdDriver\\inc\\adc.h"
|
|
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|
|
|
void ADC_Open(ADC_T *adc,
|
|
uint32_t u32InputMode,
|
|
uint32_t u32OpMode,
|
|
uint32_t u32ChMask);
|
|
void ADC_Close(ADC_T *adc);
|
|
void ADC_EnableHWTrigger(ADC_T *adc,
|
|
uint32_t u32Source,
|
|
uint32_t u32Param);
|
|
void ADC_DisableHWTrigger(ADC_T *adc);
|
|
void ADC_SetExtraSampleTime(ADC_T *adc,
|
|
uint32_t u32ChNum,
|
|
uint32_t u32SampleTime);
|
|
void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask);
|
|
void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask);
|
|
|
|
void ADC_SeqModeEnable(ADC_T *adc, uint32_t u32SeqTYPE, uint32_t u32ModeSel);
|
|
void ADC_SeqModeTriggerSrc(ADC_T *adc, uint32_t u32SeqModeTriSrc1, uint32_t u32SeqModeTriSrc2);
|
|
|
|
|
|
|
|
|
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|
|
#line 11940 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Include\\Mini58Series.h"
|
|
#line 1 "..\\..\\..\\Library\\StdDriver\\inc\\fmc.h"
|
|
|
|
|
|
|
|
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|
|
|
#line 40 "..\\..\\..\\Library\\StdDriver\\inc\\fmc.h"
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#line 58 "..\\..\\..\\Library\\StdDriver\\inc\\fmc.h"
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#line 79 "..\\..\\..\\Library\\StdDriver\\inc\\fmc.h"
|
|
|
|
|
|
extern void FMC_Close(void);
|
|
extern int32_t FMC_Erase(uint32_t u32PageAddr);
|
|
extern int32_t FMC_GetBootSource(void);
|
|
extern void FMC_Open(void);
|
|
extern uint32_t FMC_Read (uint32_t u32Addr);
|
|
extern uint32_t FMC_ReadCID(void);
|
|
extern uint32_t FMC_ReadPID(void);
|
|
extern uint32_t FMC_ReadUCID(uint32_t u32Index);
|
|
extern uint32_t FMC_ReadUID(uint32_t u32Index);
|
|
extern uint32_t FMC_ReadDataFlashBaseAddr(void);
|
|
extern void FMC_SetVectorPageAddr(uint32_t u32PageAddr);
|
|
extern uint32_t FMC_GetVectorPageAddr(void);
|
|
extern void FMC_Write(uint32_t u32Addr, uint32_t u32Data);
|
|
extern int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count);
|
|
extern int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count);
|
|
extern int32_t FMC_GetCRC32Sum(uint32_t addr, uint32_t count, uint32_t *chksum);
|
|
|
|
|
|
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|
|
#line 11941 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Include\\Mini58Series.h"
|
|
#line 1 "..\\..\\..\\Library\\StdDriver\\inc\\gpio.h"
|
|
|
|
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|
|
#line 81 "..\\..\\..\\Library\\StdDriver\\inc\\gpio.h"
|
|
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|
|
#line 143 "..\\..\\..\\Library\\StdDriver\\inc\\gpio.h"
|
|
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void GPIO_SetMode(GPIO_T *gpio, uint32_t u32PinMask, uint32_t u32Mode);
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void GPIO_EnableInt(GPIO_T *gpio, uint32_t u32Pin, uint32_t u32IntAttribs);
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void GPIO_DisableInt(GPIO_T *gpio, uint32_t u32Pin);
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#line 11942 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Include\\Mini58Series.h"
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#line 1 "..\\..\\..\\Library\\StdDriver\\inc\\i2c.h"
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uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock);
|
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void I2C_Close(I2C_T *i2c);
|
|
void I2C_ClearTimeoutFlag(I2C_T *i2c);
|
|
void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack);
|
|
void I2C_DisableInt(I2C_T *i2c);
|
|
void I2C_EnableInt(I2C_T *i2c);
|
|
uint32_t I2C_GetBusClockFreq(I2C_T *i2c);
|
|
uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock);
|
|
uint32_t I2C_GetIntFlag(I2C_T *i2c);
|
|
uint32_t I2C_GetStatus(I2C_T *i2c);
|
|
uint32_t I2C_GetData(I2C_T *i2c);
|
|
void I2C_SetData(I2C_T *i2c, uint8_t u8Data);
|
|
void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode);
|
|
void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask);
|
|
void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout);
|
|
void I2C_DisableTimeout(I2C_T *i2c);
|
|
void I2C_EnableWakeup(I2C_T *i2c);
|
|
void I2C_DisableWakeup(I2C_T *i2c);
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#line 11943 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Include\\Mini58Series.h"
|
|
#line 1 "..\\..\\..\\Library\\StdDriver\\inc\\pwm.h"
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#line 49 "..\\..\\..\\Library\\StdDriver\\inc\\pwm.h"
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#line 58 "..\\..\\..\\Library\\StdDriver\\inc\\pwm.h"
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#line 131 "..\\..\\..\\Library\\StdDriver\\inc\\pwm.h"
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uint32_t PWM_ConfigOutputChannel(PWM_T *pwm,
|
|
uint32_t u32ChannelNum,
|
|
uint32_t u32Frequency,
|
|
uint32_t u32DutyCycle);
|
|
void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask);
|
|
void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask);
|
|
void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask);
|
|
void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
|
|
void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum);
|
|
void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
|
|
uint32_t PWM_GetADCTriggerFlag (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
|
|
void PWM_EnableFaultBrake(PWM_T *pwm,
|
|
uint32_t u32ChannelMask,
|
|
uint32_t u32LevelMask,
|
|
uint32_t u32BrakeSource);
|
|
void PWM_ClearFaultBrakeFlag(PWM_T *pwm, uint32_t u32BrakeSource);
|
|
void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
|
|
void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
|
|
void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration);
|
|
void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum);
|
|
|
|
void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
|
|
void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum);
|
|
void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
|
uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
|
|
|
void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
|
|
void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
|
|
void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
|
|
uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
|
|
|
|
void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum);
|
|
void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum);
|
|
void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
|
uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
|
|
|
void PWM_EnableCenterInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
|
|
void PWM_DisableCenterInt(PWM_T *pwm, uint32_t u32ChannelNum);
|
|
void PWM_ClearCenterIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
|
uint32_t PWM_GetCenterIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
|
|
|
void PWM_EnableRiseInt(PWM_T *pwm, uint32_t u32ChannelNum);
|
|
void PWM_DisableRiseInt(PWM_T *pwm, uint32_t u32ChannelNum);
|
|
void PWM_ClearRiseIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
|
uint32_t PWM_GetRiseIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
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|
#line 11944 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Include\\Mini58Series.h"
|
|
#line 1 "..\\..\\..\\Library\\StdDriver\\inc\\spi.h"
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#line 50 "..\\..\\..\\Library\\StdDriver\\inc\\spi.h"
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static __inline void SPI_SET_SS_HIGH(SPI_T *spi)
|
|
{
|
|
spi->SSCTL &= ~(0x1ul << (3));
|
|
spi->SSCTL |= ((0x1ul << (5)) | (0x1ul << (2)) | (0x1ul << (0)));
|
|
}
|
|
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|
|
static __inline void SPI_SET_SS_LOW(SPI_T *spi)
|
|
{
|
|
spi->SSCTL &= ~(0x1ul << (3));
|
|
spi->SSCTL |= (0x1ul << (5));
|
|
spi->SSCTL &= ~(0x1ul << (2));
|
|
spi->SSCTL |= (0x1ul << (0));
|
|
}
|
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|
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static __inline void SPI_SET_DATA_WIDTH(SPI_T *spi, uint32_t u32Width)
|
|
{
|
|
if(u32Width == 32)
|
|
u32Width = 0;
|
|
|
|
spi->CTL = (spi->CTL & ~(0x1ful << (3))) | (u32Width << (3));
|
|
}
|
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|
|
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
|
|
void SPI_Close(SPI_T *spi);
|
|
void SPI_ClearRxFIFO(SPI_T *spi);
|
|
void SPI_ClearTxFIFO(SPI_T *spi);
|
|
void SPI_DisableAutoSS(SPI_T *spi);
|
|
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
|
|
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
|
|
void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
|
|
void SPI_DisableFIFO(SPI_T *spi);
|
|
uint32_t SPI_GetBusClock(SPI_T *spi);
|
|
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
|
|
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
|
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#line 11945 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Include\\Mini58Series.h"
|
|
#line 1 "..\\..\\..\\Library\\StdDriver\\inc\\timer.h"
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#line 47 "..\\..\\..\\Library\\StdDriver\\inc\\timer.h"
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static __inline void TIMER_Start(TIMER_T *timer)
|
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{
|
|
timer->CTL |= (0x1ul << (30));
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}
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static __inline void TIMER_Stop(TIMER_T *timer)
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{
|
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timer->CTL &= ~(0x1ul << (30));
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}
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static __inline void TIMER_EnableWakeup(TIMER_T *timer)
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{
|
|
timer->CTL |= (0x1ul << (23));
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}
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static __inline void TIMER_DisableWakeup(TIMER_T *timer)
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{
|
|
timer->CTL &= ~(0x1ul << (23));
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}
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static __inline void TIMER_EnableCaptureDebounce(TIMER_T *timer)
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{
|
|
timer->EXTCTL |= (0x1ul << (6));
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}
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static __inline void TIMER_DisableCaptureDebounce(TIMER_T *timer)
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{
|
|
timer->EXTCTL &= ~(0x1ul << (6));
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}
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static __inline void TIMER_EnableEventCounterDebounce(TIMER_T *timer)
|
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{
|
|
timer->EXTCTL |= (0x1ul << (7));
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|
}
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static __inline void TIMER_DisableEventCounterDebounce(TIMER_T *timer)
|
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{
|
|
timer->EXTCTL &= ~(0x1ul << (7));
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|
}
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static __inline void TIMER_EnableInt(TIMER_T *timer)
|
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{
|
|
timer->CTL |= (0x1ul << (29));
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|
}
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static __inline void TIMER_DisableInt(TIMER_T *timer)
|
|
{
|
|
timer->CTL &= ~(0x1ul << (29));
|
|
}
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static __inline void TIMER_EnableCaptureInt(TIMER_T *timer)
|
|
{
|
|
timer->EXTCTL |= (0x1ul << (5));
|
|
}
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static __inline void TIMER_DisableCaptureInt(TIMER_T *timer)
|
|
{
|
|
timer->EXTCTL &= ~(0x1ul << (5));
|
|
}
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static __inline uint32_t TIMER_GetIntFlag(TIMER_T *timer)
|
|
{
|
|
return(timer->INTSTS & (0x1ul << (0)) ? 1 : 0);
|
|
}
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static __inline void TIMER_ClearIntFlag(TIMER_T *timer)
|
|
{
|
|
timer->INTSTS = (0x1ul << (0));
|
|
}
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static __inline uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer)
|
|
{
|
|
return timer->EINTSTS;
|
|
}
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static __inline void TIMER_ClearCaptureIntFlag(TIMER_T *timer)
|
|
{
|
|
timer->EINTSTS = (0x1ul << (0));
|
|
}
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static __inline uint32_t TIMER_GetWakeupFlag(TIMER_T *timer)
|
|
{
|
|
return (timer->INTSTS & (0x1ul << (1)) ? 1 : 0);
|
|
}
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static __inline void TIMER_ClearWakeupFlag(TIMER_T *timer)
|
|
{
|
|
timer->INTSTS = (0x1ul << (1));
|
|
}
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static __inline uint32_t TIMER_GetCaptureData(TIMER_T *timer)
|
|
{
|
|
return timer->CAP;
|
|
}
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|
static __inline uint32_t TIMER_GetCounter(TIMER_T *timer)
|
|
{
|
|
return timer->CNT;
|
|
}
|
|
|
|
uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq);
|
|
void TIMER_Close(TIMER_T *timer);
|
|
void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec);
|
|
void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge);
|
|
void TIMER_DisableCapture(TIMER_T *timer);
|
|
void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge);
|
|
void TIMER_DisableEventCounter(TIMER_T *timer);
|
|
uint32_t TIMER_GetModuleClock(TIMER_T *timer);
|
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#line 11946 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Include\\Mini58Series.h"
|
|
#line 1 "..\\..\\..\\Library\\StdDriver\\inc\\uart.h"
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__inline void UART_CLEAR_RTS(UART_T* uart)
|
|
{
|
|
uart->MODEM |= (0x1ul << (9));
|
|
uart->MODEM &= ~(0x1ul << (1));
|
|
}
|
|
|
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|
|
|
|
|
|
|
__inline void UART_SET_RTS(UART_T* uart)
|
|
{
|
|
uart->MODEM |= (0x1ul << (9)) | (0x1ul << (1));
|
|
}
|
|
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|
|
void UART_ClearIntFlag(UART_T* uart , uint32_t u32InterruptFlag);
|
|
void UART_Close(UART_T* uart );
|
|
void UART_DisableFlowCtrl(UART_T* uart );
|
|
void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag );
|
|
void UART_EnableFlowCtrl(UART_T* uart );
|
|
void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag );
|
|
void UART_Open(UART_T* uart, uint32_t u32baudrate);
|
|
uint32_t UART_Read(UART_T* uart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes);
|
|
void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits);
|
|
void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC);
|
|
void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction);
|
|
void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr);
|
|
uint32_t UART_Write(UART_T* uart,uint8_t *pu8TxBuf, uint32_t u32WriteBytes);
|
|
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|
|
#line 11947 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Include\\Mini58Series.h"
|
|
#line 1 "..\\..\\..\\Library\\StdDriver\\inc\\wdt.h"
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|
|
#line 39 "..\\..\\..\\Library\\StdDriver\\inc\\wdt.h"
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|
void WDT_Open(uint32_t u32TimeoutInterval,
|
|
uint32_t u32ResetDelay,
|
|
uint32_t u32EnableReset,
|
|
uint32_t u32EnableWakeup);
|
|
void WDT_Close(void);
|
|
|
|
void WDT_EnableInt(void);
|
|
void WDT_DisableInt(void);
|
|
|
|
|
|
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|
|
#line 11948 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Include\\Mini58Series.h"
|
|
#line 1 "..\\..\\..\\Library\\StdDriver\\inc\\wwdt.h"
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|
|
|
|
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|
|
|
|
|
#line 47 "..\\..\\..\\Library\\StdDriver\\inc\\wwdt.h"
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|
|
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|
|
void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt);
|
|
|
|
|
|
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|
#line 11949 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Include\\Mini58Series.h"
|
|
|
|
|
|
|
|
|
|
|
|
#line 14 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Source\\system_Mini58Series.c"
|
|
|
|
|
|
|
|
|
|
|
|
uint32_t __HSI = (22118400UL);
|
|
uint32_t SystemCoreClock;
|
|
uint32_t PllClock = (22118400UL);
|
|
uint32_t CyclesPerUs;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
void SystemInit (void)
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
void SystemCoreClockUpdate (void)
|
|
{
|
|
uint32_t u32CoreFreq, u32ClkSrc;
|
|
|
|
|
|
PllClock = CLK_GetPLLClockFreq();
|
|
|
|
u32ClkSrc = ((CLK_T *) (((uint32_t)0x50000000) + 0x00200))->CLKSEL0 & (0x7ul << (0));
|
|
|
|
if (u32ClkSrc == 0)
|
|
u32CoreFreq = (12000000UL);
|
|
else if (u32ClkSrc ==2)
|
|
u32CoreFreq = PllClock;
|
|
else if (u32ClkSrc == 3)
|
|
u32CoreFreq = (10000UL);
|
|
else if (u32ClkSrc == 7)
|
|
u32CoreFreq = (22118400UL);
|
|
else
|
|
u32CoreFreq = (22118400UL);
|
|
|
|
SystemCoreClock = (u32CoreFreq/((((CLK_T *) (((uint32_t)0x50000000) + 0x00200))->CLKDIV & (0xful << (0))) + 1));
|
|
CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
|
|
}
|
|
|
|
#line 88 "..\\..\\..\\Library\\Device\\Nuvoton\\Mini58Series\\Source\\system_Mini58Series.c"
|
|
|
|
|