167 lines
6.1 KiB
C
167 lines
6.1 KiB
C
/*******************************************************************************
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* @note Copyright (C) 2017 Shanghai Panchip Microelectronics Co., Ltd.
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* All rights reserved.
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*
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* @file drv_pwm.c
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* @brief PWMÇý¶¯
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* ----------+----------+----------+----------
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* PWM0_CH0 | | P1.2(8) | P2.2(24)
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* ----------+----------+----------+----------
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* PWM0_CH1 | | P1.3(9) | P2.3(25)
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* ----------+----------+----------+----------
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* PWM0_CH2 | | | P2.4(26)
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* ----------+----------+----------+----------
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* PWM0_CH3 | | | P2.5(27)
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* ----------+----------+----------+----------
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* PWM0_CH4 | | P1.4(10) | P2.6(28)
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* ----------+----------+----------+----------
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* PWM0_CH5 | P0.4(15) | |
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* ----------+----------+----------+----------
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*
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* @history - V1.0, 2017-04-20, xiaoguolin, first implementation.
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* @history - V1.1, 2018-01-18, huoweibin, add pwm_pan159_setDuty.
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*******************************************************************************/
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#include "lib_driver_pwm_pan159.h"
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// <0x50=>PWM0_CH0_P12 (CHIP_PIN_8)
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// <0x90=>PWM0_CH0_P22 (CHIP_PIN_24)
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// <0x59=>PWM0_CH1_P13 (CHIP_PIN_9)
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// <0x99=>PWM0_CH1_P23 (CHIP_PIN_25)
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// <0xA2=>PWM0_CH2_P24 (CHIP_PIN_26)
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// <0xAB=>PWM0_CH3_P25 (CHIP_PIN_27)
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// <0x64=>PWM0_CH4_P14 (CHIP_PIN_10)
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// <0xB4=>PWM0_CH4_P26 (CHIP_PIN_28)
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// <0x25=>PWM0_CH5_P04 (CHIP_PIN_15)
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//#define __PWM_PAN159_M0 0xA2 //P24
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//#define __PWM_PAN159_M1 0x99 //P23
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//#define __PWM_PAN159_M2 0x90 //P22
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//#define __PWM_PAN159_M3 0xAB //P25
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/*******************************************************************************
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* @brief PWM³õʼ»¯
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* @param[in]
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* @return 1 - ³É¹¦
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* 0 - ʧ°Ü
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* @history - V1.0, 2017-09-12, xiaoguolin, first implementation.
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*******************************************************************************/
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void pwm_pan159_init(uint8_t psc)
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{
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//const uint32_t pwmch_module[] = {PWMCH01_MODULE,PWMCH23_MODULE,PWMCH45_MODULE};
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SYS_UnlockReg();
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CLK_EnableModuleClock(PWMCH01_MODULE); //moudle clk enable ch01
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CLK_EnableModuleClock(PWMCH23_MODULE); //moudle clk enable ch23
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// CLK_SetModuleClock(PWMCH01_MODULE,CLK_CLKSEL1_PWMCH01SEL_HCLK,0);//ʱÖÓ1·ÖƵ
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// CLK_SetModuleClock(PWMCH23_MODULE,CLK_CLKSEL1_PWMCH23SEL_HCLK,0);//ʱÖÓ1·ÖƵ
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//CLK_EnableModuleClock(PWMCH45_MODULE); //moudle clk enable ch45
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// CLK_EnableModuleClock(pwmch_module[0x03 >> 1]); //moudle clk enable ch3
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SystemCoreClockUpdate();
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SYS_LockReg();
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//P22
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SYS->P2_MFP &= ~SYS_MFP_P22_Msk;
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SYS->P2_MFP |= SYS_MFP_P22_PWM0_CH0;
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PWM->CTL |= PWM_CTL_CNTEN0_Msk | PWM_CTL_CNTMODE0_Msk;
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//P23
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SYS->P2_MFP &= ~SYS_MFP_P23_Msk;
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SYS->P2_MFP |= SYS_MFP_P23_PWM0_CH1;
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PWM->CTL |= PWM_CTL_CNTEN1_Msk | PWM_CTL_CNTMODE1_Msk;
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//P24
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SYS->P2_MFP &= ~SYS_MFP_P24_Msk;
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SYS->P2_MFP |= SYS_MFP_P24_PWM0_CH2;
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PWM->CTL |= PWM_CTL_CNTEN2_Msk | PWM_CTL_CNTMODE2_Msk;
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//P25
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SYS->P2_MFP &= ~SYS_MFP_P25_Msk;
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SYS->P2_MFP |= SYS_MFP_P25_PWM0_CH3;
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PWM->CTL |= PWM_CTL_CNTEN3_Msk | PWM_CTL_CNTMODE3_Msk;
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PWM_SET_PRESCALER(PWM,0x02,psc);
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PWM_SET_DIVIDER(PWM,0x02,PWM_CLK_DIV_1);
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//PWM_SET_ALIGNED_TYPE(PWM,0x02,0x80000000);//ÖÐÐĶÔÆë
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PWM_SET_ALIGNED_TYPE(PWM,0x02,PWM_EDGE_ALIGNED);//±ßÑضÔÆë
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PWM_SET_CMR(PWM,0x02,0);
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PWM_SET_CNR(PWM,0x02,1000);//PWM RANGE setting
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//PWM->CTL |= 1 << (PWM_CTL_PINV0_Pos + (((uint32_t)(0x02)) << 2));//Êä³öÈ¡·´
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PWM_SET_PRESCALER(PWM,0x01,psc);
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PWM_SET_DIVIDER(PWM,0x01,PWM_CLK_DIV_1);
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PWM_SET_ALIGNED_TYPE(PWM,0x01,PWM_EDGE_ALIGNED);
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PWM_SET_CMR(PWM,0x01,0);
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PWM_SET_CNR(PWM,0x01,1000);//PWM RANGE setting
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//PWM->CTL |= 1 << (PWM_CTL_PINV0_Pos + (((uint32_t)(0x01)) << 2));//Êä³öÈ¡·´
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PWM_SET_PRESCALER(PWM,0x00,psc);
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PWM_SET_DIVIDER(PWM,0x00,PWM_CLK_DIV_1);
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PWM_SET_ALIGNED_TYPE(PWM,0x00,PWM_EDGE_ALIGNED);
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PWM_SET_CMR(PWM,0x00,0);
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PWM_SET_CNR(PWM,0x00,1000);//PWM RANGE setting
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//PWM->CTL |= 1 << (PWM_CTL_PINV0_Pos + (((uint32_t)(0x00)) << 2));//Êä³öÈ¡·´
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PWM_SET_PRESCALER(PWM,0x03,psc);
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PWM_SET_DIVIDER(PWM,0x03,PWM_CLK_DIV_1);
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PWM_SET_ALIGNED_TYPE(PWM,0x03,PWM_EDGE_ALIGNED);
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PWM_SET_CMR(PWM,0x03,0);
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PWM_SET_CNR(PWM,0x03,1000);//PWM RANGE setting
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//PWM->CTL |= 1 << (PWM_CTL_PINV0_Pos + (((uint32_t)(0x03)) << 2));//Êä³öÈ¡·´
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/* ¿ªÆôPWM */
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PWM->CTL |= PWM_CTL_CNTEN0_Msk << (((uint32_t)0x00) << 2);
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PWM->CTL |= PWM_CTL_CNTEN0_Msk << (((uint32_t)0x01) << 2);
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PWM->CTL |= PWM_CTL_CNTEN0_Msk << (((uint32_t)0x02) << 2);
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PWM->CTL |= PWM_CTL_CNTEN0_Msk << (((uint32_t)0x03) << 2);
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PWM_PAN159_CHN_OUT(0x00,0);
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PWM_PAN159_CHN_OUT(0x01,0);
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PWM_PAN159_CHN_OUT(0x02,0);
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PWM_PAN159_CHN_OUT(0x03,0);
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//PWM_PAN159_CHN_UNLOCK(1<<chn);
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// return pwm_port;
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}
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/*******************************************************************************
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* @brief PWMÊä³ö
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* @param[in]
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* @return
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* @history - V1.0, 2018-01-18, huoweibin, first implementation.
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*******************************************************************************/
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void pwm_pan159_setDuty(uint16_t *duty)
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{
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register uint8_t lock = 0x00;
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register uint8_t unlock = 0x00;
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/*M1 - CH1 PWM out*/
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PWM_PAN159_CHN_OUT(0x01,duty[0]);
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if(duty[0] == 0){
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lock |= 1 << 0x01;
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}
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else{
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unlock |= 1 << 0x01;
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}
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/*M2 - CH3 PWM out*/
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PWM_PAN159_CHN_OUT(0x03,duty[1]);
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if(duty[1] == 0){
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lock |= 1 << 0x03;
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}
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else{
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unlock |= 1 << 0x03;
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}
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/*M3 - CH2 PWM out*/
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PWM_PAN159_CHN_OUT(0x02,duty[2]);
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if(duty[2] == 0){
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lock |= 1 << 0x02;
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}
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else{
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unlock |= 1 << 0x02;
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}
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/*M4 - CH0 PWM out*/
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PWM_PAN159_CHN_OUT(0x00,duty[3]);
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if(duty[3] == 0){
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lock |= 1 << 0x00;
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}
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else{
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unlock |= 1 << 0x00;
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}
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PWM_PAN159_CHN_LOCK(lock);
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PWM_PAN159_CHN_UNLOCK(unlock);
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}
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