添加PAN159资料
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{\rtf1\adeflang1025\ansi\ansicpg1252\uc1\adeff0\deff0\stshfdbch37\stshfloch37\stshfhich37\stshfbi0\deflang2057\deflangfe2057\themelang2057\themelangfe0\themelangcs0{\fonttbl{\f0\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\f1\fbidi \fswiss\fcharset0\fprq2{\*\panose 020b0604020202020204}Arial;}
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{\f2\fbidi \fmodern\fcharset0\fprq1{\*\panose 02070309020205020404}Courier New;}{\f3\fbidi \froman\fcharset2\fprq2{\*\panose 05050102010706020507}Symbol;}{\f10\fbidi \fnil\fcharset2\fprq2{\*\panose 05000000000000000000}Wingdings;}
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{\f14\fbidi \froman\fcharset136\fprq2{\*\panose 02020500000000000000}PMingLiU{\*\falt \'b7\'73\'b2\'d3\'a9\'fa\'c5\'e9};}{\f34\fbidi \froman\fcharset0\fprq2{\*\panose 02040503050406030204}Cambria Math;}
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{\f37\fbidi \fswiss\fcharset0\fprq2{\*\panose 020f0502020204030204}Calibri;}{\f38\fbidi \fswiss\fcharset0\fprq2{\*\panose 020b0604030504040204}Tahoma;}{\f39\fbidi \fmodern\fcharset0\fprq1{\*\panose 020b0609020204030204}Consolas;}
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{\f40\fbidi \froman\fcharset136\fprq2{\*\panose 02020500000000000000}@PMingLiU;}{\flomajor\f31500\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}
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{\fdbmajor\f31501\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\fhimajor\f31502\fbidi \froman\fcharset0\fprq2{\*\panose 02040503050406030204}Cambria;}
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{\fbimajor\f31503\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\flominor\f31504\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}
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{\fdbminor\f31505\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\fhiminor\f31506\fbidi \fswiss\fcharset0\fprq2{\*\panose 020f0502020204030204}Calibri;}
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{\fbiminor\f31507\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\f41\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}{\f42\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}
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{\f44\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\f45\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}{\f46\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\f47\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}
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{\f48\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\f49\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\f51\fbidi \fswiss\fcharset238\fprq2 Arial CE;}{\f52\fbidi \fswiss\fcharset204\fprq2 Arial Cyr;}
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{\f54\fbidi \fswiss\fcharset161\fprq2 Arial Greek;}{\f55\fbidi \fswiss\fcharset162\fprq2 Arial Tur;}{\f56\fbidi \fswiss\fcharset177\fprq2 Arial (Hebrew);}{\f57\fbidi \fswiss\fcharset178\fprq2 Arial (Arabic);}
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{\f58\fbidi \fswiss\fcharset186\fprq2 Arial Baltic;}{\f59\fbidi \fswiss\fcharset163\fprq2 Arial (Vietnamese);}{\f61\fbidi \fmodern\fcharset238\fprq1 Courier New CE;}{\f62\fbidi \fmodern\fcharset204\fprq1 Courier New Cyr;}
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{\f64\fbidi \fmodern\fcharset161\fprq1 Courier New Greek;}{\f65\fbidi \fmodern\fcharset162\fprq1 Courier New Tur;}{\f66\fbidi \fmodern\fcharset177\fprq1 Courier New (Hebrew);}{\f67\fbidi \fmodern\fcharset178\fprq1 Courier New (Arabic);}
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{\f68\fbidi \fmodern\fcharset186\fprq1 Courier New Baltic;}{\f69\fbidi \fmodern\fcharset163\fprq1 Courier New (Vietnamese);}{\f183\fbidi \froman\fcharset0\fprq2 PMingLiU Western{\*\falt \'b7\'73\'b2\'d3\'a9\'fa\'c5\'e9};}
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{\f381\fbidi \froman\fcharset238\fprq2 Cambria Math CE;}{\f382\fbidi \froman\fcharset204\fprq2 Cambria Math Cyr;}{\f384\fbidi \froman\fcharset161\fprq2 Cambria Math Greek;}{\f385\fbidi \froman\fcharset162\fprq2 Cambria Math Tur;}
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{\f388\fbidi \froman\fcharset186\fprq2 Cambria Math Baltic;}{\f389\fbidi \froman\fcharset163\fprq2 Cambria Math (Vietnamese);}{\f411\fbidi \fswiss\fcharset238\fprq2 Calibri CE;}{\f412\fbidi \fswiss\fcharset204\fprq2 Calibri Cyr;}
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{\f414\fbidi \fswiss\fcharset161\fprq2 Calibri Greek;}{\f415\fbidi \fswiss\fcharset162\fprq2 Calibri Tur;}{\f418\fbidi \fswiss\fcharset186\fprq2 Calibri Baltic;}{\f419\fbidi \fswiss\fcharset163\fprq2 Calibri (Vietnamese);}
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{\f421\fbidi \fswiss\fcharset238\fprq2 Tahoma CE;}{\f422\fbidi \fswiss\fcharset204\fprq2 Tahoma Cyr;}{\f424\fbidi \fswiss\fcharset161\fprq2 Tahoma Greek;}{\f425\fbidi \fswiss\fcharset162\fprq2 Tahoma Tur;}
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{\f426\fbidi \fswiss\fcharset177\fprq2 Tahoma (Hebrew);}{\f427\fbidi \fswiss\fcharset178\fprq2 Tahoma (Arabic);}{\f428\fbidi \fswiss\fcharset186\fprq2 Tahoma Baltic;}{\f429\fbidi \fswiss\fcharset163\fprq2 Tahoma (Vietnamese);}
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{\f430\fbidi \fswiss\fcharset222\fprq2 Tahoma (Thai);}{\f431\fbidi \fmodern\fcharset238\fprq1 Consolas CE;}{\f432\fbidi \fmodern\fcharset204\fprq1 Consolas Cyr;}{\f434\fbidi \fmodern\fcharset161\fprq1 Consolas Greek;}
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{\f435\fbidi \fmodern\fcharset162\fprq1 Consolas Tur;}{\f438\fbidi \fmodern\fcharset186\fprq1 Consolas Baltic;}{\f439\fbidi \fmodern\fcharset163\fprq1 Consolas (Vietnamese);}{\f443\fbidi \froman\fcharset0\fprq2 @PMingLiU Western;}
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{\flomajor\f31508\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}{\flomajor\f31509\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}{\flomajor\f31511\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}
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{\flomajor\f31512\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}{\flomajor\f31513\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\flomajor\f31514\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}
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{\flomajor\f31515\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\flomajor\f31516\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\fdbmajor\f31518\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}
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{\fdbmajor\f31519\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}{\fdbmajor\f31521\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\fdbmajor\f31522\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}
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{\fdbmajor\f31523\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\fdbmajor\f31524\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}{\fdbmajor\f31525\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}
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{\fdbmajor\f31526\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\fhimajor\f31528\fbidi \froman\fcharset238\fprq2 Cambria CE;}{\fhimajor\f31529\fbidi \froman\fcharset204\fprq2 Cambria Cyr;}
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{\fhimajor\f31531\fbidi \froman\fcharset161\fprq2 Cambria Greek;}{\fhimajor\f31532\fbidi \froman\fcharset162\fprq2 Cambria Tur;}{\fhimajor\f31535\fbidi \froman\fcharset186\fprq2 Cambria Baltic;}
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{\fhimajor\f31536\fbidi \froman\fcharset163\fprq2 Cambria (Vietnamese);}{\fbimajor\f31538\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}{\fbimajor\f31539\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}
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{\fbimajor\f31541\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\fbimajor\f31542\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}{\fbimajor\f31543\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}
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{\fbimajor\f31544\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}{\fbimajor\f31545\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\fbimajor\f31546\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}
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{\flominor\f31548\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}{\flominor\f31549\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}{\flominor\f31551\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}
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{\flominor\f31552\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}{\flominor\f31553\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\flominor\f31554\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}
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{\flominor\f31555\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\flominor\f31556\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\fdbminor\f31558\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}
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{\fdbminor\f31559\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}{\fdbminor\f31561\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\fdbminor\f31562\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}
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{\fdbminor\f31563\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\fdbminor\f31564\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}{\fdbminor\f31565\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}
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{\fdbminor\f31566\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\fhiminor\f31568\fbidi \fswiss\fcharset238\fprq2 Calibri CE;}{\fhiminor\f31569\fbidi \fswiss\fcharset204\fprq2 Calibri Cyr;}
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{\fhiminor\f31571\fbidi \fswiss\fcharset161\fprq2 Calibri Greek;}{\fhiminor\f31572\fbidi \fswiss\fcharset162\fprq2 Calibri Tur;}{\fhiminor\f31575\fbidi \fswiss\fcharset186\fprq2 Calibri Baltic;}
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{\fhiminor\f31576\fbidi \fswiss\fcharset163\fprq2 Calibri (Vietnamese);}{\fbiminor\f31578\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}{\fbiminor\f31579\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}
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{\fbiminor\f31581\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\fbiminor\f31582\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}{\fbiminor\f31583\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}
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{\fbiminor\f31584\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}{\fbiminor\f31585\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\fbiminor\f31586\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}}
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{\colortbl;\red0\green0\blue0;\red0\green0\blue255;\red0\green255\blue255;\red0\green255\blue0;\red255\green0\blue255;\red255\green0\blue0;\red255\green255\blue0;\red255\green255\blue255;\red0\green0\blue128;\red0\green128\blue128;\red0\green128\blue0;
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\red128\green0\blue128;\red128\green0\blue0;\red128\green128\blue0;\red128\green128\blue128;\red192\green192\blue192;\red34\green34\blue34;}{\*\defchp \loch\af37\hich\af37\dbch\af37 }{\*\defpap
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\ql \li0\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 }\noqfpromote {\stylesheet{\ql \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025
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\ltrch\fcs0 \fs22\lang2057\langfe1033\loch\f37\hich\af37\dbch\af37\cgrid\langnp2057\langfenp1033 \snext0 \sqformat \spriority0 Normal;}{\*\cs10 \additive \ssemihidden \sunhideused \spriority1 Default Paragraph Font;}{\*
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\ts11\tsrowd\trftsWidthB3\trpaddl108\trpaddr108\trpaddfl3\trpaddft3\trpaddfb3\trpaddfr3\tblind0\tblindtype3\tsvertalt\tsbrdrt\tsbrdrl\tsbrdrb\tsbrdrr\tsbrdrdgl\tsbrdrdgr\tsbrdrh\tsbrdrv
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\ql \li0\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang2057\langfe2057\loch\f37\hich\af37\dbch\af37\cgrid\langnp2057\langfenp2057
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\snext11 \ssemihidden \sunhideused \sqformat Normal Table;}{\s15\ql \li0\ri0\widctlpar
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\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af2\afs20\alang1025 \ltrch\fcs0
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\f2\fs20\lang2057\langfe2057\cgrid\langnp2057\langfenp2057 \sbasedon0 \snext15 \slink16 \ssemihidden \sunhideused HTML Preformatted;}{\*\cs16 \additive \f2\fs20\lang0\langfe2057\langfenp2057 \slink15 \slocked \ssemihidden HTML Preformatted Char;}{\*\cs17
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\additive \ul\cf2 \sunhideused Hyperlink;}{\*\cs18 \additive \fs16 \ssemihidden \sunhideused annotation reference;}{\s19\ql \li0\ri0\sa200\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025
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\ltrch\fcs0 \fs20\lang2057\langfe1033\loch\f37\hich\af37\dbch\af37\cgrid\langnp2057\langfenp1033 \sbasedon0 \snext19 \slink20 \ssemihidden \sunhideused annotation text;}{\*\cs20 \additive \fs20 \slink19 \slocked \ssemihidden Comment Text Char;}{
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\s21\ql \li0\ri0\sa200\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af0\afs20\alang1025 \ltrch\fcs0 \b\fs20\lang2057\langfe1033\loch\f37\hich\af37\dbch\af37\cgrid\langnp2057\langfenp1033
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\sbasedon19 \snext19 \slink22 \ssemihidden \sunhideused annotation subject;}{\*\cs22 \additive \b\fs20 \slink21 \slocked \ssemihidden Comment Subject Char;}{\s23\ql \li0\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0
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\rtlch\fcs1 \af38\afs16\alang1025 \ltrch\fcs0 \fs16\lang2057\langfe1033\loch\f38\hich\af38\dbch\af37\cgrid\langnp2057\langfenp1033 \sbasedon0 \snext23 \slink24 \ssemihidden \sunhideused Balloon Text;}{\*\cs24 \additive \f38\fs16
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\slink23 \slocked \ssemihidden Balloon Text Char;}{\s25\ql \li0\ri0\sa200\sl276\slmult1\widctlpar\tqc\tx4680\tqr\tx9360\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0
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\fs22\lang2057\langfe1033\loch\f37\hich\af37\dbch\af37\cgrid\langnp2057\langfenp1033 \sbasedon0 \snext25 \slink26 \sunhideused header;}{\*\cs26 \additive \fs22\lang2057\langfe0\langnp2057 \slink25 \slocked Header Char;}{
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\s27\ql \li0\ri0\sa200\sl276\slmult1\widctlpar\tqc\tx4680\tqr\tx9360\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0
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\fs22\lang2057\langfe1033\loch\f37\hich\af37\dbch\af37\cgrid\langnp2057\langfenp1033 \sbasedon0 \snext27 \slink28 \sunhideused \spriority0 footer;}{\*\cs28 \additive \fs22\lang2057\langfe0\langnp2057 \slink27 \slocked \ssemihidden Footer Char;}{\*\cs29
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\additive \rtlch\fcs1 \af0 \ltrch\fcs0 \sbasedon10 \spriority0 page number;}{\s30\ql \fi-425\li1134\ri0\sb120\sa120\widctlpar\tx1134\tqr\tx7920\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin1134\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0
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\fs18\lang2057\langfe1033\loch\f1\hich\af1\dbch\af14\cgrid\langnp2057\langfenp1033 \sbasedon0 \snext30 \spriority0 Indent;}{\s31\ql \li0\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025
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\ltrch\fcs0 \fs22\lang2057\langfe1033\loch\f37\hich\af37\dbch\af37\cgrid\langnp2057\langfenp1033 \snext31 \shidden \ssemihidden Revision;}{\s32\ql \li0\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1
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\af0\afs21\alang1025 \ltrch\fcs0 \f39\fs21\lang2057\langfe1033\cgrid\langnp2057\langfenp1033 \sbasedon0 \snext32 \slink33 \sunhideused Plain Text;}{\*\cs33 \additive \f39\fs21\lang0\langfe1033\langfenp1033 \slink32 \slocked Plain Text Char;}{
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\s34\ql \li720\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang2057\langfe1033\loch\f37\hich\af37\dbch\af37\cgrid\langnp2057\langfenp1033
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\sbasedon0 \snext34 \sqformat \spriority34 List Paragraph;}}{\*\listtable{\*\listpicture{\pict{\*\picprop\shplid1025{\sp{\sn shapeType}{\sv 75}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}{\sp{\sn fLine}{\sv 0}}{\sp{\sn borderTopColor}{\sv -16777216}}
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{\sp{\sn borderLeftColor}{\sv -16777216}}{\sp{\sn borderBottomColor}{\sv -16777216}}{\sp{\sn borderRightColor}{\sv -16777216}}{\sp{\sn fIsBullet}{\sv 1}}{\sp{\sn fLayoutInCell}{\sv 1}}}\picscalex100\picscaley100\piccropl0\piccropr0\piccropt0\piccropb0
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\picw7620\pich7620\picwgoal4320\pichgoal4320\wmetafile8\bliptag1621848657\blipupi-183{\*\blipuid 60ab72513f0584938171c3e04d1ffcc4}
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0100090000039100000002001c00000000000400000003010800050000000b0200000000050000000c0209070507040000002e0118001c000000fb02a4ff0000
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000000009001000000000440002243616c6962726900000000000000000000000000000000000000000000000000040000002d010000040000002d0100000400
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00002d010000040000002d010000040000002d010000040000002d0100000400000002010100050000000902000000020d000000320a57000000010004000000
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00000807080720003600050000000902000000021c000000fb021000070000000000bc02000000000102022253797374656d0076d0e132092cfb3d00d9e4497680014e76a4f2530a38fb3d00040000002d010100040000002d010100030000000000}}{\list\listtemplateid-492936738\listhybrid{\listlevel
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\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'02\'00.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li720\lin720 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0
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\levelstartat1\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li1440\lin1440 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext
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\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li2160\lin2160 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0
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\ltrch\fcs0 \fi-360\li2880\lin2880 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3600\lin3600 }{\listlevel\levelnfc2
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\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4320\lin4320 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1
|
||||
\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5040\lin5040 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext
|
||||
\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5760\lin5760 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0
|
||||
\ltrch\fcs0 \fi-180\li6480\lin6480 }{\listname ;}\listid39328222}{\list\listtemplateid-917765150\listhybrid{\listlevel\levelnfc2\levelnfcn2\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'03(\'00);}{\levelnumbers\'02;}
|
||||
\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-720\li1080\lin1080 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0
|
||||
\fi-360\li1440\lin1440 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li2160\lin2160 }{\listlevel
|
||||
\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li2880\lin2880 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0
|
||||
\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3600\lin3600 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative
|
||||
\levelspace0\levelindent0{\leveltext\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4320\lin4320 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext
|
||||
\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5040\lin5040 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1
|
||||
\af0 \ltrch\fcs0 \fi-360\li5760\lin5760 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li6480\lin6480 }
|
||||
{\listname ;}\listid144588935}{\list\listtemplateid-1026387870{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'01\'00;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0
|
||||
\fi-360\li360\lin360 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat2\levelspace0\levelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers\'01\'03;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-360\li360\lin360 }{\listlevel\levelnfc0
|
||||
\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-720\li720\lin720 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0
|
||||
\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'07\'00.\'01.\'02.\'03;}{\levelnumbers\'01\'03\'05\'07;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-720\li720\lin720 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0
|
||||
\levelstartat1\levelspace0\levelindent0{\leveltext\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'03\'05\'07\'09;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-720\li720\lin720 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1
|
||||
\levelspace0\levelindent0{\leveltext\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumbers\'01\'03\'05\'07\'09\'0b;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-1080\li1080\lin1080 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1
|
||||
\levelspace0\levelindent0{\leveltext\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-1080\li1080\lin1080 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0
|
||||
\levelstartat1\levelspace0\levelindent0{\leveltext\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-1440\li1440\lin1440 }{\listlevel\levelnfc0\levelnfcn0\leveljc0
|
||||
\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f\'11;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-1440\li1440\lin1440 }{\listname
|
||||
;}\listid155655221}{\list\listtemplateid466939434\listhybrid{\listlevel\levelnfc3\levelnfcn3\leveljc0\leveljcn0\levelfollow0\levelstartat6\levelspace0\levelindent0{\leveltext\'03(\'00);}{\levelnumbers\'02;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0
|
||||
\fi-360\li1080\lin1080 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li1800\lin1800 }{\listlevel
|
||||
\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li2520\lin2520 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0
|
||||
\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3240\lin3240 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative
|
||||
\levelspace0\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3960\lin3960 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext
|
||||
\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4680\lin4680 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1
|
||||
\af0 \ltrch\fcs0 \fi-360\li5400\lin5400 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li6120\lin6120 }
|
||||
{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li6840\lin6840 }{\listname ;}\listid207642902}
|
||||
{\list\listtemplateid-868587660\listhybrid{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'03(\'00);}{\levelnumbers\'02;}\rtlch\fcs1 \af0 \ltrch\fcs0 \cf1\dbch\af0\fbias0
|
||||
\fi-360\li720\lin720 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li1440\lin1440 }{\listlevel\levelnfc2
|
||||
\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li2160\lin2160 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0
|
||||
\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li2880\lin2880 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0
|
||||
\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3600\lin3600 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext
|
||||
\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4320\lin4320 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1
|
||||
\af0 \ltrch\fcs0 \fi-360\li5040\lin5040 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5760\lin5760 }
|
||||
{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li6480\lin6480 }{\listname ;}\listid244075828}
|
||||
{\list\listtemplateid-301287646\listhybrid{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'03(\'00);}{\levelnumbers\'02;}\rtlch\fcs1 \af0 \ltrch\fcs0 \cf1\dbch\af0\fbias0
|
||||
\fi-360\li720\lin720 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li1440\lin1440 }{\listlevel\levelnfc2
|
||||
\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li2160\lin2160 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0
|
||||
\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li2880\lin2880 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0
|
||||
\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3600\lin3600 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext
|
||||
\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4320\lin4320 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1
|
||||
\af0 \ltrch\fcs0 \fi-360\li5040\lin5040 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5760\lin5760 }
|
||||
{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li6480\lin6480 }{\listname ;}\listid358317280}
|
||||
{\list\listtemplateid572415416\listhybrid{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'03(\'00);}{\levelnumbers\'02;}\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\dbch\af37\fbias0
|
||||
\fi-360\li786\lin786 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li1506\lin1506 }{\listlevel\levelnfc2
|
||||
\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li2226\lin2226 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0
|
||||
\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li2946\lin2946 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0
|
||||
\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3666\lin3666 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext
|
||||
\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4386\lin4386 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1
|
||||
\af0 \ltrch\fcs0 \fi-360\li5106\lin5106 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5826\lin5826 }
|
||||
{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li6546\lin6546 }{\listname ;}\listid423112302}
|
||||
{\list\listtemplateid-1459612926\listhybrid{\listlevel\levelnfc3\levelnfcn3\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'02\'00.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-360\li1275\lin1275 }
|
||||
{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li1995\lin1995 }{\listlevel\levelnfc2\levelnfcn2\leveljc2
|
||||
\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li2715\lin2715 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1
|
||||
\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3435\lin3435 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0
|
||||
{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li4155\lin4155 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'05.;}{\levelnumbers\'01;}
|
||||
\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4875\lin4875 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0
|
||||
\fi-360\li5595\lin5595 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li6315\lin6315 }{\listlevel
|
||||
\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li7035\lin7035 }{\listname ;}\listid454718230}
|
||||
{\list\listtemplateid-551514274\listhybrid{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat2\levelspace0\levelindent0{\leveltext\'01-;}{\levelnumbers;}\loch\af1\hich\af1\dbch\af0\fbias0 \fi-360\li1080\lin1080 }{\listlevel
|
||||
\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01o;}{\levelnumbers;}\f2\fbias0 \fi-360\li1800\lin1800 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0
|
||||
\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fbias0 \fi-360\li2520\lin2520 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0
|
||||
{\leveltext\'01\u-3913 ?;}{\levelnumbers;}\f3\fbias0 \fi-360\li3240\lin3240 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01o;}{\levelnumbers;}\f2\fbias0
|
||||
\fi-360\li3960\lin3960 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fbias0 \fi-360\li4680\lin4680 }{\listlevel\levelnfc23\levelnfcn23
|
||||
\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3913 ?;}{\levelnumbers;}\f3\fbias0 \fi-360\li5400\lin5400 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative
|
||||
\levelspace0\levelindent0{\leveltext\'01o;}{\levelnumbers;}\f2\fbias0 \fi-360\li6120\lin6120 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}
|
||||
\f10\fbias0 \fi-360\li6840\lin6840 }{\listname ;}\listid474840100}{\list\listtemplateid-1601537400{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'01\u-3913 ?;}{\levelnumbers;}
|
||||
\f3\fs20\fbias0 \fi-360\li720\jclisttab\tx720\lin720 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01o;}{\levelnumbers;}\f2\fs20\fbias0 \levelpicture0\fi-360\li1440
|
||||
\jclisttab\tx1440\lin1440 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fs20\fbias0 \fi-360\li2160\jclisttab\tx2160\lin2160 }
|
||||
{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fs20\fbias0 \fi-360\li2880\jclisttab\tx2880\lin2880 }{\listlevel\levelnfc23\levelnfcn23
|
||||
\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fs20\fbias0 \fi-360\li3600\jclisttab\tx3600\lin3600 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0
|
||||
\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fs20\fbias0 \fi-360\li4320\jclisttab\tx4320\lin4320 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative
|
||||
\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fs20\fbias0 \fi-360\li5040\jclisttab\tx5040\lin5040 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext
|
||||
\'01\u-3929 ?;}{\levelnumbers;}\f10\fs20\fbias0 \fi-360\li5760\jclisttab\tx5760\lin5760 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}
|
||||
\f10\fs20\fbias0 \fi-360\li6480\jclisttab\tx6480\lin6480 }{\listname ;}\listid891499942}{\list\listtemplateid-2106560774\listhybrid{\listlevel\levelnfc3\levelnfcn3\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext
|
||||
\'02\'00.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-360\li720\lin720 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}
|
||||
\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li1440\lin1440 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0
|
||||
\fi-180\li2160\lin2160 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li2880\lin2880 }{\listlevel
|
||||
\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3600\lin3600 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2
|
||||
\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4320\lin4320 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative
|
||||
\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5040\lin5040 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext
|
||||
\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5760\lin5760 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1
|
||||
\af0 \ltrch\fcs0 \fi-180\li6480\lin6480 }{\listname ;}\listid939029968}{\list\listtemplateid1475657882\listhybrid{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat2\levelspace0\levelindent0{\leveltext\'01-;}{\levelnumbers;}
|
||||
\loch\af1\hich\af1\dbch\af0\fbias0 \fi-360\li1440\lin1440 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'01o;}{\levelnumbers;}\f2\fbias0 \fi-360\li2160\lin2160 }{\listlevel\levelnfc23
|
||||
\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fbias0 \fi-360\li2880\lin2880 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1
|
||||
\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3913 ?;}{\levelnumbers;}\f3\fbias0 \fi-360\li3600\lin3600 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext
|
||||
\'01o;}{\levelnumbers;}\f2\fbias0 \fi-360\li4320\lin4320 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fbias0 \fi-360\li5040\lin5040 }
|
||||
{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3913 ?;}{\levelnumbers;}\f3\fbias0 \fi-360\li5760\lin5760 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0
|
||||
\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01o;}{\levelnumbers;}\f2\fbias0 \fi-360\li6480\lin6480 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0
|
||||
{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fbias0 \fi-360\li7200\lin7200 }{\listname ;}\listid1080055287}{\list\listtemplateid345380616\listhybrid{\listlevel\levelnfc2\levelnfcn2\leveljc0\leveljcn0\levelfollow0\levelstartat2\levelspace0\levelindent0
|
||||
{\leveltext\'03(\'00);}{\levelnumbers\'02;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-720\li1864\lin1864 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext
|
||||
\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li2224\lin2224 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1
|
||||
\af0 \ltrch\fcs0 \fi-180\li2944\lin2944 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3664\lin3664 }
|
||||
{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li4384\lin4384 }{\listlevel\levelnfc2\levelnfcn2\leveljc2
|
||||
\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li5104\lin5104 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1
|
||||
\lvltentative\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5824\lin5824 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0
|
||||
{\leveltext\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li6544\lin6544 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}
|
||||
\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li7264\lin7264 }{\listname ;}\listid1198470673}{\list\listtemplateid-1488150726\listhybrid{\listlevel\levelnfc2\levelnfcn2\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext
|
||||
\'03(\'00);}{\levelnumbers\'02;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-720\li1080\lin1080 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}
|
||||
\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li1440\lin1440 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0
|
||||
\fi-180\li2160\lin2160 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li2880\lin2880 }{\listlevel
|
||||
\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3600\lin3600 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2
|
||||
\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4320\lin4320 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative
|
||||
\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5040\lin5040 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext
|
||||
\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5760\lin5760 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1
|
||||
\af0 \ltrch\fcs0 \fi-180\li6480\lin6480 }{\listname ;}\listid1264800667}{\list\listtemplateid1709371634{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'01\'00;}{\levelnumbers\'01;}
|
||||
\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-360\li360\lin360 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat2\levelspace0\levelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers\'01\'03;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0
|
||||
\fi-360\li360\lin360 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-720\li720\lin720 }{\listlevel
|
||||
\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'07\'00.\'01.\'02.\'03;}{\levelnumbers\'01\'03\'05\'07;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-720\li720\lin720 }{\listlevel\levelnfc0\levelnfcn0
|
||||
\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'03\'05\'07\'09;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-720\li720\lin720 }{\listlevel\levelnfc0\levelnfcn0\leveljc0
|
||||
\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumbers\'01\'03\'05\'07\'09\'0b;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-1080\li1080\lin1080 }{\listlevel\levelnfc0\levelnfcn0\leveljc0
|
||||
\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-1080\li1080\lin1080 }{\listlevel\levelnfc0\levelnfcn0
|
||||
\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-1440\li1440\lin1440 }{\listlevel
|
||||
\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f\'11;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0
|
||||
\fi-1440\li1440\lin1440 }{\listname ;}\listid1335182434}{\list\listtemplateid-1861725538\listhybrid{\listlevel\levelnfc3\levelnfcn3\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'02\'00.;}{\levelnumbers\'01;}
|
||||
\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-360\li720\lin720 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0
|
||||
\fi-360\li1440\lin1440 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li2160\lin2160 }{\listlevel
|
||||
\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li2880\lin2880 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0
|
||||
\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3600\lin3600 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative
|
||||
\levelspace0\levelindent0{\leveltext\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4320\lin4320 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext
|
||||
\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5040\lin5040 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1
|
||||
\af0 \ltrch\fcs0 \fi-360\li5760\lin5760 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li6480\lin6480 }
|
||||
{\listname ;}\listid1556695208}{\list\listtemplateid-301287646\listhybrid{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'03(\'00);}{\levelnumbers\'02;}\rtlch\fcs1 \af0 \ltrch\fcs0
|
||||
\cf1\dbch\af0\fbias0 \fi-360\li720\lin720 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li1440\lin1440 }
|
||||
{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li2160\lin2160 }{\listlevel\levelnfc0\levelnfcn0\leveljc0
|
||||
\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li2880\lin2880 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1
|
||||
\lvltentative\levelspace0\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3600\lin3600 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0
|
||||
{\leveltext\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4320\lin4320 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;}
|
||||
\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5040\lin5040 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0
|
||||
\fi-360\li5760\lin5760 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li6480\lin6480 }{\listname
|
||||
;}\listid1583906200}{\list\listtemplateid1806592008\listhybrid{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'03(\'00);}{\levelnumbers\'02;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0
|
||||
\fi-360\li720\lin720 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li1440\lin1440 }{\listlevel\levelnfc2
|
||||
\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li2160\lin2160 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0
|
||||
\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li2880\lin2880 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0
|
||||
\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3600\lin3600 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext
|
||||
\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4320\lin4320 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1
|
||||
\af0 \ltrch\fcs0 \fi-360\li5040\lin5040 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5760\lin5760 }
|
||||
{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li6480\lin6480 }{\listname ;}\listid1801338294}
|
||||
{\list\listtemplateid-1056679890\listhybrid{\listlevel\levelnfc2\levelnfcn2\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'03(\'00);}{\levelnumbers\'02;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-720\li1429
|
||||
\jclisttab\tx1429\lin1429 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li1789\jclisttab\tx1789\lin1789 }
|
||||
{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li2509\jclisttab\tx2509\lin2509 }{\listlevel\levelnfc0
|
||||
\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3229\jclisttab\tx3229\lin3229 }{\listlevel\levelnfc4\levelnfcn4\leveljc0
|
||||
\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3949\jclisttab\tx3949\lin3949 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0
|
||||
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{\title LEC-PRE-00489 ~ EULA for CMSIS Deliverables}{\author Emily Drea}{\operator Joachim Krech}{\creatim\yr2015\mo8\dy27\hr7\min15}{\revtim\yr2015\mo8\dy27\hr7\min15}{\printim\yr2015\mo8\dy18\hr8\min33}{\version2}{\edmins1}{\nofpages5}{\nofwords2395}
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|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636
|
||||
\par THIS END USER LICENCE AGREEMENT ("LICENCE") IS A LEGAL AGREEMENT BETWEEN YOU (EITHER A }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid5861575
|
||||
SINGLE INDIVIDUAL, OR SINGLE LEGAL ENTITY) AND ARM LIMITED ("ARM") FOR THE USE OF THE CMSIS }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid5861575 . ARM IS ONLY WILLING TO LICENSE THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS DELIVERABLES }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid5861575 TO YOU ON CONDITION THAT YOU ACCEPT ALL OF THE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 TERMS IN THIS LICENCE. BY CLICKING "I AGREE", OR BY INSTALLING OR OTHERWISE USING OR COPYING THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS DELIVERABLES }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636
|
||||
YOU INDICATE THAT YOU AGREE TO BE BOUND BY ALL THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE YOU TO USE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 OF }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 AND YOU MAY NOT INSTALL, USE OR COPY THE }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 .
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'93Deliverables\'94
|
||||
means (i) the CMSIS Deliverables; (ii) CMSIS-DAP Specification; (iii) CMSIS-DAP Firmware; and (iv) RDDI DLL.
|
||||
\par \'93CMSIS-DAP Specification\'94 means any documentation defining the application programming interface, naming and coding conventions of the Cortex Microcontroller Software Interface Standard Debug Access Port (\'93CMSIS-DAP\'94). }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 \hich\f1 Notwithstanding the foregoing, \'93}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 CMSIS-DAP }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 \hich\f1 Specification\'94\loch\f1 shall not include}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 :}{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 (i) the implementation of other published specifications referenced in th}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496
|
||||
\hich\af1\dbch\af37\loch\f1 e}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 CMSIS-DAP }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 Specific\hich\af1\dbch\af37\loch\f1 ation; }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 and }{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 (ii) any enabling technologies that may be necessary to make or use any product or portion}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496
|
||||
\hich\af1\dbch\af37\loch\f1 s}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 thereof that complies with the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496
|
||||
\hich\af1\dbch\af37\loch\f1 CMSIS-DAP }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 Specification, but are not themselves expressly set forth in th}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 e}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1
|
||||
CMSIS-DAP }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 Specification (e.g. compiler front en\hich\af1\dbch\af37\loch\f1
|
||||
ds, code generators, back ends, libraries or other compiler, assembler or linker technologies; validation or debug software or hardware; applications, operating system or driver software; RISC architecture; }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 and }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 processor microarchitecture)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496
|
||||
\hich\af1\dbch\af37\loch\f1 . }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'93}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid11929640 \hich\af1\dbch\af37\loch\f1 CMSIS-DAP Fi\hich\af1\dbch\af37\loch\f1
|
||||
rmware}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'94
|
||||
means the C programming language source code accompanying this Licence which implements the functionality of the application programming interface as defined in the CMSIS-DAP Specification and any updates, patches and modifications ARM may make ava
|
||||
ilable under the terms of this Licence.
|
||||
\par \'93CMSIS Deliverables\'94 means the following components: (i) CMSIS-CORE; (ii) CMSIS-DRIVER; (iii) CMSIS-DSP; (iv) CMSIS-PACK; (v) CMSIS-RTOS API; and (vi) CMSIS-SVD .
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx0\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'93CMSIS-CORE
|
||||
\'94 means the specification defining the application programming interface, naming and coding conventions for the Cortex-M processor cores.
|
||||
\par \'94}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid488451 \hich\af1\dbch\af37\loch\f1 CMSIS-DRIVER}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'94}{\rtlch\fcs1 \af0 \ltrch\fcs0
|
||||
\insrsid14553496 \hich\af37\dbch\af37\loch\f37 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid488451 \hich\af1\dbch\af37\loch\f1 means the specification defining }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496
|
||||
\hich\af1\dbch\af37\loch\f1 a generic}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid488451 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 p}{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid488451 \hich\af1\dbch\af37\loch\f1 eripheral }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 d}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\insrsid14553496\charrsid488451 \hich\af1\dbch\af37\loch\f1 river application programming interface, naming and coding conventions}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid14553496 .
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'93CMSIS-DSP\'94
|
||||
means the digital signal process (DSP) library specification defining the application programming interface of a DSP library implementation}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15023647 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx0\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'93}{
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid13240697 \hich\af1\dbch\af37\loch\f1 CMSIS-PACK}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'94}{\rtlch\fcs1 \af0 \ltrch\fcs0
|
||||
\insrsid14553496\charrsid13240697 \hich\af37\dbch\af37\loch\f37 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid13240697 \hich\af1\dbch\af37\loch\f1 means the specification defining a software pack file format}{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 , verification utility, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid13240697 \hich\af1\dbch\af37\loch\f1 and the associated XML
|
||||
\hich\af1\dbch\af37\loch\f1 schema file}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid14553496\charrsid13240697 .}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid14553496
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'93CMSIS-RTOS API\'94
|
||||
means the real-time operating system (RTOS) specification defining a generic application programming interface layer for a RTOS system}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15023647 .}{
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'93CMSIS-SVD\'94 }{
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid9306407 means }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
the specification defining the System View Description (SVD), verification utility, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf17\lang1033\langfe2057\langnp1033\langfenp2057\insrsid14553496\charrsid9306407 and associated XML}{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\cf17\lang1033\langfe2057\langnp1033\langfenp2057\insrsid14553496 schema}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf17\lang1033\langfe2057\langnp1033\langfenp2057\insrsid14553496\charrsid9306407 files. }{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid9306407
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'93Firmware\'94 means firmware that complies with the CMSIS-DAP Specification.
|
||||
\par \'93RDDI DLL\'94 means the reference implementation of a device driver }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6236778 accompanying this Licence}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 in object code form and any updates, patch
|
||||
es and modifications ARM may agree to make available under the terms of this Licence and is used with targets containing microprocessors manufactured or simulated under licence from ARM.
|
||||
\par \'93Separate Files\'94 means the components }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid10227990 identified}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 in the Schedule.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid3618484 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par \'93Target Connection Product\'94 means a target connection product that complies with the CMSIS-DAP Specification and is used on or with a target containing microprocessors manufactured or simulated under licence from ARM.
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid5577184 \hich\af1\dbch\af37\loch\f1
|
||||
Notwithstanding the foregoing, the Deliverables shall not include: (i) the implementation of other published specifications referenced in the Deliverables; (ii) any enabling technologies that may be necessary to make or use any product or portion thereof
|
||||
\hich\af1\dbch\af37\loch\f1
|
||||
that complies with the Deliverables, but are not themselves expressly set forth in the Deliverables (e.g. compiler front ends, code generators, back ends, libraries or other compiler, assembler or linker technologies; validation or debug software or hard
|
||||
\hich\af1\dbch\af37\loch\f1 w\hich\af1\dbch\af37\loch\f1
|
||||
are; applications, operating system or driver software; RISC architecture; processor microarchitecture); (iii) maskworks and physical layouts of integrated circuit designs; or (iv) RTL or other high level representations of integrated circuit designs.}{
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 1. LICENCE GRANTS.
|
||||
\par }\pard \ltrpar\qj \li0\ri0\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 1.1}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS DELIVERABLES
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135 ARM hereby grants to you, subject to the terms and conditions of this Licence, a non-exclusive, non-transferable }{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid1317547 licence, to use and copy the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS D}{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135 for the purpose of: }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar
|
||||
\tx426\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135 (i) subject to clause 1.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 5(i)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135 , developing, having developed, manufacturing, having manufactured, offering to sell, selling, supplying or otherwise distributing products that comply with the }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135 ; and
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid1317547 (ii) distributing and having distributed (directly or through your customers and authorised distributors) the CMSIS-D}{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid1317547 unmodified, with the products}{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135 you have developed under }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Clause 1.1 (i) }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135 provided you preserve any copyright notices which are included with the CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135 . }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par 1.2 CMSIS-DAP SPECIFICATION
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 ARM hereby grants to you, subject to the terms and conditions of this Licence, a non-exclusive, non-transferable licence, to }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid3605578 use and copy the CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 -DAP }{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6386005 Specification}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 for the purposes of:
|
||||
\par }\pard \ltrpar\qj \fi-567\li567\ri0\sl276\slmult1\widctlpar\tx567\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin567\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 (a)\tab }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid11225765
|
||||
developing, having developed, manufacturing, having manufactured, offering to sell, selling, supplying}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
, distributing or having distributed a Target Connection Product}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 ;}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par }\pard \ltrpar\qj \fi-567\li567\ri0\sl276\slmult1\widctlpar\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin567\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 (b)\tab }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid11225765 developing, having developed, }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 subject to clause 1.5(ii) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid11225765
|
||||
offering to sell, selling, supplying}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 , }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid11225765
|
||||
distributing}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 or having distributed }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1
|
||||
(directly or through your cus\hich\af1\dbch\af37\loch\f1 tomers and authorised distributors) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Firmware to run on a Target Connection Product; and
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 (c)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \tab subject to clause 1.5(ii), }{
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 distributing }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 and }{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 having distributed }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1
|
||||
(directly or through your customers and authorised distributors) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 the CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 -}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 DAP }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14559761 Specification unmodified}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 ,}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14559761 with}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 either or both the}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 Target Connection Products and Firmware}{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 , developed under the licences granted in this Clause 1.2}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar
|
||||
\tx426\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par 1.3 CMSIS-DAP FIRMWARE
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sl276\slmult1\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496
|
||||
\cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 ARM hereby grants to you, subject to the terms and conditions of this Licence, a non-exclusive, non-trans\hich\af1\dbch\af37\loch\f1 ferable licence, to:
|
||||
|
||||
\par }\pard \ltrpar\qj \fi-567\li567\ri0\sl276\slmult1\widctlpar
|
||||
\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin567\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 (a)\tab }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid10356267 \hich\af1\dbch\af37\loch\f1 use, copy}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid2558325
|
||||
\hich\af1\dbch\af37\loch\f1 , and modify the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 CMSIS-DAP Firmware }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
for the purposes of developing and having developed }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid8745136 firmware to run on}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 a Target Connection Product; and
|
||||
\par (b)\tab subject to clause 1.5(ii), offer to sell, selling, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid5058240 supply}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 , supplying, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid8745136 distributing}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 or having distributed }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1
|
||||
(directly or through your customers and authorised distributors)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS-DAP Firmware or any modified version created under Clause 1.3 (a) }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid8745136 in}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6192099 object code form only }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 to run on a Target Connection Product. }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid9913780 }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar
|
||||
\tx426\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 1.4 RDDI DLL
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sl276\slmult1\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496
|
||||
\cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 ARM hereby grants to you, subject to the terms and conditions of this Licence, a non-exclusive, non-transferable licence, to:
|
||||
\par }\pard \ltrpar\qj \fi-567\li567\ri0\sl276\slmult1\widctlpar
|
||||
\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin567\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 (a)\tab use and copy the RDDI DLL for the purpose }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid13793259 of connecting }{
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 a Target Connection Product }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid11805076
|
||||
running CMSIS-DAP compatible firmware }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 (either the Firmware or the firmware created pursuant to Clause 1.3) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid11805076 to }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 software debug tools installed on }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid11805076 a host }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 computer running a Windows platform}{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid11805076 ; and}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par (b)\tab subject to clause 1.5(ii), offer to sell, selling, supplying, distributing or having distributed }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 (directly or
|
||||
\hich\af1\dbch\af37\loch\f1 through your customers and authorised distributors) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 the RDDI DLL in object code form only.
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar
|
||||
\tx426\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135
|
||||
\par }\pard \ltrpar\qj \li0\ri0\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 1.5}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 CONDITIONS ON REDISTRIBUTION}{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496
|
||||
\cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 (i) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid1928237
|
||||
\hich\af1\dbch\af37\loch\f1 If you distribute (directly or through your customers and authorised distributors) the products you have created pursuant \hich\af1\dbch\af37\loch\f1 to Clause 1.1}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid1928237 \hich\af1\dbch\af37\loch\f1 (i) you agree: (a) not to use ARM
|
||||
\hich\f1 \rquote \loch\f1 s name, logo or trademarks to market any or all of the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid1928237 products created under Clause 1.1 (i); }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid1928237 \hich\af1\dbch\af37\loch\f1 (b) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 to }{
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid1928237 \hich\af1\dbch\af37\loch\f1 pr}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 e}{
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid1928237 \hich\af1\dbch\af37\loch\f1 serve any copyright notices included in the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 CMSIS D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid1928237 \hich\af1\dbch\af37\loch\f1 ; and (c) to ensure your customers and aut\hich\af1\dbch\af37\loch\f1 horised distributors comply with this Clause 1.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 5(i)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid1928237 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1
|
||||
(ii) If you are authorised and choose to distribute (directly or through your customers and authorised distributors) the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 CMSIS}{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 -}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 DAP }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14559761 Specification}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 , }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 Firmware, CMSIS-DAP Firmware or any modified version \hich\af1\dbch\af37\loch\f1
|
||||
thereof, or the RDDI DLL, you agree; (a) to ensure that they are licensed for use with targets containing microprocessors manufactured or simulated under licence from ARM; (b) to preserve any copyright notices which are included with the }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 -}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 DAP }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14559761 Specification}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 , CMSIS-DAP Firmware}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1
|
||||
, and include valid copyright notices in; (i) any modified version of the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS-DAP Firmware}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 ; and (ii) the Firmware; (c) not to use ARM\hich\f1 \rquote \loch\f1 s name, logo or trademarks to market -any or all of the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 -}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 DAP }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14559761 Specification}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 , Firmware,}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 CMSI\hich\af1\dbch\af37\loch\f1
|
||||
S-DAP Firmware or any modified version therof, the RDDI DLL or the Target Connection Products; and (d) to ensure your customers and authorised distributors comply with this Clause 1.5(ii).
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496
|
||||
\cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 2. RESTRICTIONS ON USE OF THE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 DELIVERABLES
|
||||
}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 .
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496
|
||||
\cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 PERMITTED USERS: The }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 shall be used only by you (either a single individual, or single legal entity) your employees, or by your }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 on-site }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636
|
||||
bona fide sub-contractors for whose acts and omissions you hereby agree to be responsible to ARM}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 for}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 to the same extent as }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 you are for }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 your employees, and provided always that such sub-contractors}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 :}{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 (i) are contractually obligated to use the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 only for your benefit}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 ;}{
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 and (i}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 i}{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 ) agree to assign all their work product and any rights they create therein in the supply of such work to you.
|
||||
\par COPYRIGHT AND RESERVATION OF RIGHTS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14488502 : The }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14488502
|
||||
are owned by ARM or its licensors and are protected by copyright and other intellectual property laws and international treaties. The }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Deliverables}{
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14488502 are licensed not sold. Except as expressly licensed herein, you acquire no right, title or interest in the }{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14488502
|
||||
or any intellectual property therein. In no event shall the licences granted herein be construed as granting you, expressly or by implication, estoppels or otherwise, a licence to use any ARM technology except the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14488502 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 3}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 . SUPPORT.
|
||||
\par ARM is not obligated to support the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Deliverables but}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 may do so entirely at ARM's discretion.
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 4}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 . }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 NO }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 WARRANT}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Y.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636
|
||||
\par YOU AGREE THAT THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 DELIVERABLES ARE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636
|
||||
LICENSED "AS IS", AND THAT ARM EXPRESSLY DISCLA
|
||||
IMS ALL REPRESENTATIONS, WARRANTIES, CONDITIONS OR OTHER TERMS, EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF NON-INFRINGEMENT, SATISFACTORY QUALITY, AND FITNESS FOR A PARTICULAR PURPOSE.}{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 THE DELIVERABLES MAY CONTAIN ERRORS. }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 5}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 . LIMITATION OF LIABILITY.
|
||||
\par THE MAXIMUM LIABILITY OF ARM TO YOU IN AGGREGATE FOR ALL CLAIMS MADE AGAINST ARM IN CONTRACT}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 ,}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 TORT OR OTHERWISE UNDER OR IN CONNECTION WITH THE SUBJECT MATTER OF THIS LICENCE SHALL NOT EXCEED }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 THE GREATER OF (I) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 THE TO
|
||||
TAL OF SUMS PAID BY YOU TO ARM (IF ANY) FOR THIS LICENCE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 AND (II) US$10.00}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
THE LIMITATIONS, EXCLUSIONS AND DISCLAIMERS IN THIS LICENCE SHALL APPLY TO THE MAXIMUM EXTENT ALLOWED BY APPLICABLE LAW.
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 6
|
||||
}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid13830602 \hich\af1\dbch\af37\loch\f1 . THIRD PARTY RIGHTS.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid13830602
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid13830602 \hich\af1\dbch\af37\loch\f1 The Separate Files are delivered su\hich\af1\dbch\af37\loch\f1 \hich\f1
|
||||
bject to and your use is governed by their own separate licence agreements. This Licence does not apply to such Separate Files and they are not included in the term \'93}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid13830602 \loch\af1\dbch\af37\hich\f1 \'94\loch\f1
|
||||
under this Licence. You agree to comply with all terms and conditions impose\hich\af1\dbch\af37\loch\f1 \hich\f1 d on you in respect of such Separate Files including those identified in the Schedule (\'93\loch\f1 \hich\f1 Third Party Terms\'94\loch\f1
|
||||
).
|
||||
\par \hich\af1\dbch\af37\loch\f1 ARM HEREBY DISCLAIMS ANY AND ALL WARRANTIES EXPRESS OR IMPLIED FROM ANY THIRD PARTIES REGARDING ANY SEPARATE FILES, ANY THIRD PARTY MATERIALS INC\hich\af1\dbch\af37\loch\f1 \hich\f1
|
||||
LUDED IN THE SOFTWARE, ANY THIRD PARTY MATERIALS FROM WHICH THE SOFTWARE IS DERIVED (COLLECTIVELY \'93\loch\f1 \hich\f1 OTHER CODE\'94\loch\f1
|
||||
), AND THE USE OF ANY OR ALL THE OTHER CODE IN CONNECTION WITH THE SOFTWARE, INCLUDING (WITHOUT LIMITATION) ANY WARRANTIES OF SATISFACTORY QUALIT\hich\af1\dbch\af37\loch\f1 Y\hich\af1\dbch\af37\loch\f1 OR FITNESS FOR A PARTICULAR PURPOSE.
|
||||
\par \hich\af1\dbch\af37\loch\f1 NO THIRD PARTY LICENSORS OF OTHER CODE SHALL HAVE ANY LIABILITY FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND WHETHER
|
||||
\hich\af1\dbch\af37\loch\f1
|
||||
MADE UNDER CONTRACT, TORT OR OTHER LEGAL THEORY, ARISING IN ANY WAY OUT OF THE USE OR DISTRIBUTION OF THE OTHER CODE OR THE EXERCISE OF ANY RIGHTS GRANTED UNDER EITHER OR BOTH THIS LICENCE AND THE LEGAL TERMS APPLICABLE TO ANY SEPARATE FILES, EVEN IF ADV
|
||||
\hich\af1\dbch\af37\loch\f1 I\hich\af1\dbch\af37\loch\f1 SED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 7}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 . U.S. GOVERNMENT END USERS.
|
||||
\par US Government Restrictions: Use, duplication, reproduction, release, modification, disclosure or transfer of this commercial product and accompanying documentation is restricted in accordance with the terms of this Licence.
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 8}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 . TERM AND TERMINATION.
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 8.1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636
|
||||
This Licence shall remain in force until terminated }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 in accordance with the terms of Clause 8.2 or Clause 8.3 below}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 . }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par 8.2 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 Without prejudice to any of its other rights if you are in breach of
|
||||
any of the terms and conditions of this Licence then ARM may terminate this Licence immediately upon giving written notice to you}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid7630822
|
||||
. You may terminate this Licence at any time. }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7106724 \hich\af1\dbch\af37\loch\f1
|
||||
8.3 This Licence shall immediately terminate and shall be unavailable to you i\hich\af1\dbch\af37\loch\f1
|
||||
f you or any party affiliated to you asserts any patents against ARM, ARM affiliates, third parties who have a valid licence from ARM for the Deliverables, or any customers or distributors of any of them based upon a claim that your (or your affiliate) pa
|
||||
\hich\af1\dbch\af37\loch\f1 t\hich\af1\dbch\af37\loch\f1 ent is Necessary to implement the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\insrsid14553496\charrsid7106724 \hich\af1\dbch\af37\loch\f1 . In this Licence}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 :}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7106724
|
||||
\hich\af1\dbch\af37\loch\f1 (i) "affiliate" means any entity controlling, controlled by or under common control with a party (in fact or in law, via voting securities, management control or otherwise) and "affiliated" s\hich\af1\dbch\af37\loch\f1
|
||||
hall be construed accordingly; (ii) "assert" means to allege infringement in legal or administrative proceedings, or proceedings before any other competent trade, arbitral or international authority; }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 and }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7106724 \hich\af1\dbch\af37\loch\f1 \hich\f1 (iii) \'93\loch\f1 \hich\f1 Necessary\'94\loch\f1
|
||||
means with respect to any claims o\hich\af1\dbch\af37\loch\f1 f any patent, those claims which, without the appropriate permission of the patent owner, will be infringed when implementing the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496
|
||||
\hich\af1\dbch\af37\loch\f1 Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7106724 \hich\af1\dbch\af37\loch\f1 because no alternative, commercially reasonable, non-infringing way of implementing the }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7106724 \hich\af1\dbch\af37\loch\f1 is known.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\insrsid14553496\charrsid5900444 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 8.4 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid7630822 Upon termination of this Licence,}{
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 you shall stop }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15098396
|
||||
using the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15098396
|
||||
and destroy all copies of the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15098396 in your possession. The provisions of clauses 5, 6, 7, 8 and 9 shall survive termination of this Licence.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 9}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 . GENERAL.
|
||||
\par This Licence is governed by English Law. Except where ARM agrees otherwise in a written contract signed by you and ARM, this is the only agreement between you and ARM relating to the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636
|
||||
and it may only be modified by written agreement between you and ARM. Except a
|
||||
s expressly agreed in writing, this Licence may not be modified by purchase orders, advertising or other representation by any person. If any clause or sentence in this Licence is held by a court of law to be illegal or unenforceable the remaining provisi
|
||||
o
|
||||
ns of this Licence shall not be affected thereby. The failure by ARM to enforce any of the provisions of this Licence, unless waived in writing, shall not constitute a waiver of ARM's rights to enforce such provision or any other provision of this Licence
|
||||
in the future.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 This Licence may not be assigned without the prior written consent of ARM.
|
||||
\par }\pard \ltrpar\qc \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \page SCHEDULE
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Separate Files
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 The }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15098396 package }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 also }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15098396 includes the components}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 contained in the following directories}{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15098396 :}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid14553496 \hich\af1\dbch\af0\loch\f1 (a)\tab}}\pard \ltrpar
|
||||
\qj \fi-360\li720\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\ls16\adjustright\rin0\lin720\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 ./}{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7090778
|
||||
\hich\af1\dbch\af37\loch\f1 DSP_Lib}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 - }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15098396
|
||||
DSP Library sources and examples}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 ;
|
||||
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid14553496 \hich\af1\dbch\af0\loch\f1 (b)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 ./}{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMS\hich\af1\dbch\af37\loch\f1 IS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\insrsid14553496\charrsid7090778 \hich\af1\dbch\af37\loch\f1 Include}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 - Header files;
|
||||
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid14553496 \hich\af1\dbch\af0\loch\f1 (c)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 ./}{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7090778
|
||||
\hich\af1\dbch\af37\loch\f1 Lib}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 - }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7090778 \hich\af1\dbch\af37\loch\f1
|
||||
DSP Library build for various toolchains}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 ;
|
||||
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid14553496 \hich\af1\dbch\af0\loch\f1 (d)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 ./}{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7090778
|
||||
\hich\af1\dbch\af37\loch\f1 RTOS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 - }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7090778 \hich\af1\dbch\af37\loch\f1
|
||||
Header file template for CMSIS-RTOS implementation}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 ; and
|
||||
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid14553496 \hich\af1\dbch\af0\loch\f1 (e)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 .}{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 /Device - T}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid14488502 \hich\af1\dbch\af37\loch\f1 emplate files and implementations for Cortex-M class processors}{
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 .
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496
|
||||
\par \hich\af1\dbch\af37\loch\f1 All of the above com\hich\af1\dbch\af37\loch\f1 ponents (a\hich\f1 \endash \loch\f1 e) are licensed to you under the terms of the BSD licence, which is incorporated within or alongside the above components.
|
||||
\par }\pard \ltrpar\qj \li284\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin284\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\insrsid14553496\charrsid13975144 \hich\af1\dbch\af37\loch\f1 (f)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid13975144
|
||||
\hich\af1\dbch\af37\loch\f1 ./CMSIS/Driver \hich\f1 \endash \loch\f1 CMSIS-Driver header files}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid13975144 \hich\af1\dbch\af37\loch\f1 (g)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid14553496
|
||||
\hich\af37\dbch\af37\loch\f37 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 ./CMSIS/Pack \hich\f1 \endash \loch\f1 Example Device Family Pack}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid14553496\charrsid13975144
|
||||
|
||||
\par }\pard\plain \ltrpar\s32\ql \li0\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \rtlch\fcs1 \af0\afs21\alang1025 \ltrch\fcs0 \f39\fs21\lang2057\langfe1033\cgrid\langnp2057\langfenp1033 {\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496
|
||||
\par The above components (f \endash g) are licensed to you under the terms of the zlib licence, which is incorporated within or alongside the above components.
|
||||
\par
|
||||
\par
|
||||
\par }\pard\plain \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0
|
||||
\fs22\lang2057\langfe1033\loch\af37\hich\af37\dbch\af37\cgrid\langnp2057\langfenp1033 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid2958685 \hich\af1\dbch\af37\loch\f1 ARM contract reference LEC-PRE-00489}{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 - v4.0}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid2958685
|
||||
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{\*\latentstyles\lsdstimax267\lsdlockeddef0\lsdsemihiddendef1\lsdunhideuseddef1\lsdqformatdef0\lsdprioritydef99{\lsdlockedexcept \lsdsemihidden0 \lsdunhideused0 \lsdqformat1 \lsdpriority0 \lsdlocked0 Normal;
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000500072006f00700065007200740069006500
|
||||
7300000000000000000000000000000000000000000000000000000000000000000000000000000000000000000016000200ffffffffffffffffffffffff00000000000000000000000000000000000000000000000000000000000000000000000066000000400400000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ffffffffffffffffffffffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ffffffffffffffffffffffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
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||||
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ffffffffffffffffffffffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006e733a64733d22687474
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
6d61732e6d6963726f736f66742e636f6d2f696e7465726e616c2f6f6264222f3e3c2f64733a736368656d61526566733e3c2f64733a6461746173746f72654974656d3e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
0000000000000105000000000000}}
|
||||
BIN
PAN159/PAN159-Template/Library/CMSIS/DAP/CMSIS-DAP EULA.pdf
Normal file
BIN
PAN159/PAN159-Template/Library/CMSIS/DAP/CMSIS-DAP EULA.pdf
Normal file
Binary file not shown.
@ -0,0 +1,390 @@
|
||||
/**************************************************************************//**
|
||||
* @file DAP_config.h
|
||||
* @brief CMSIS-DAP Configuration File (Template)
|
||||
* @version V1.10
|
||||
* @date 20. May 2015
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2012-2015 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __DAP_CONFIG_H__
|
||||
#define __DAP_CONFIG_H__
|
||||
|
||||
|
||||
//**************************************************************************************************
|
||||
/**
|
||||
\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
|
||||
\ingroup DAP_ConfigIO_gr
|
||||
@{
|
||||
Provides definitions about the hardware and configuration of the Debug Unit.
|
||||
|
||||
This information includes:
|
||||
- Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
|
||||
- Debug Unit communication packet size.
|
||||
- Debug Access Port communication mode (JTAG or SWD).
|
||||
- Optional information about a connected Target Device (for Evaluation Boards).
|
||||
*/
|
||||
|
||||
#include "device.h" // Debug Unit Cortex-M Processor Header File
|
||||
|
||||
/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
|
||||
/// This value is used to calculate the SWD/JTAG clock speed.
|
||||
#define CPU_CLOCK 100000000U ///< Specifies the CPU Clock in Hz
|
||||
|
||||
/// Number of processor cycles for I/O Port write operations.
|
||||
/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
|
||||
/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
|
||||
/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
|
||||
/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
|
||||
/// required.
|
||||
#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
|
||||
|
||||
/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
|
||||
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
|
||||
#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available
|
||||
|
||||
/// Indicate that JTAG communication mode is available at the Debug Port.
|
||||
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
|
||||
#define DAP_JTAG 1 ///< JTAG Mode: 1 = available, 0 = not available.
|
||||
|
||||
/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
|
||||
/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
|
||||
#define DAP_JTAG_DEV_CNT 8U ///< Maximum number of JTAG devices on scan chain
|
||||
|
||||
/// Default communication mode on the Debug Access Port.
|
||||
/// Used for the command \ref DAP_Connect when Port Default mode is selected.
|
||||
#define DAP_DEFAULT_PORT 1U ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
|
||||
|
||||
/// Default communication speed on the Debug Access Port for SWD and JTAG mode.
|
||||
/// Used to initialize the default SWD/JTAG clock frequency.
|
||||
/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
|
||||
#define DAP_DEFAULT_SWJ_CLOCK 1000000U ///< Default SWD/JTAG clock frequency in Hz.
|
||||
|
||||
/// Maximum Package Size for Command and Response data.
|
||||
/// This configuration settings is used to optimized the communication performance with the
|
||||
/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
|
||||
#define DAP_PACKET_SIZE 64U ///< USB: 64 = Full-Speed, 1024 = High-Speed.
|
||||
|
||||
/// Maximum Package Buffers for Command and Response data.
|
||||
/// This configuration settings is used to optimized the communication performance with the
|
||||
/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
|
||||
/// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
|
||||
#define DAP_PACKET_COUNT 64U ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
|
||||
|
||||
/// Indicate that UART Serial Wire Output (SWO) trace is available.
|
||||
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
|
||||
#define SWO_UART 1 ///< SWO UART: 1 = available, 0 = not available
|
||||
|
||||
/// Maximum SWO UART Baudrate
|
||||
#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz
|
||||
|
||||
/// Indicate that Manchester Serial Wire Output (SWO) trace is available.
|
||||
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
|
||||
#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available
|
||||
|
||||
/// SWO Trace Buffer Size.
|
||||
#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n)
|
||||
|
||||
|
||||
/// Debug Unit is connected to fixed Target Device.
|
||||
/// The Debug Unit may be part of an evaluation board and always connected to a fixed
|
||||
/// known device. In this case a Device Vendor and Device Name string is stored which
|
||||
/// may be used by the debugger or IDE to configure device parameters.
|
||||
#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
|
||||
|
||||
#if TARGET_DEVICE_FIXED
|
||||
#define TARGET_DEVICE_VENDOR "ARM" ///< String indicating the Silicon Vendor
|
||||
#define TARGET_DEVICE_NAME "Cortex-M4" ///< String indicating the Target Device
|
||||
#endif
|
||||
|
||||
///@}
|
||||
|
||||
|
||||
//**************************************************************************************************
|
||||
/**
|
||||
\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
|
||||
\ingroup DAP_ConfigIO_gr
|
||||
@{
|
||||
|
||||
Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
|
||||
and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
|
||||
interface of a device. The following I/O Pins are provided:
|
||||
|
||||
JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
|
||||
---------------------------- | -------------------- | ---------------------------------------------
|
||||
TCK: Test Clock | SWCLK: Clock | Output Push/Pull
|
||||
TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
|
||||
TDI: Test Data Input | | Output Push/Pull
|
||||
TDO: Test Data Output | | Input
|
||||
nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
|
||||
nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
|
||||
|
||||
|
||||
DAP Hardware I/O Pin Access Functions
|
||||
-------------------------------------
|
||||
The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
|
||||
these I/O Pins.
|
||||
|
||||
For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
|
||||
This functions are provided to achieve faster I/O that is possible with some advanced GPIO
|
||||
peripherals that can independently write/read a single I/O pin without affecting any other pins
|
||||
of the same I/O port. The following SWDIO I/O Pin functions are provided:
|
||||
- \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
|
||||
- \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
|
||||
- \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
|
||||
- \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
|
||||
*/
|
||||
|
||||
|
||||
// Configure DAP I/O pins ------------------------------
|
||||
|
||||
/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
|
||||
Configures the DAP Hardware I/O pins for JTAG mode:
|
||||
- TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
|
||||
- TDO to input mode.
|
||||
*/
|
||||
static __inline void PORT_JTAG_SETUP (void) {
|
||||
;
|
||||
}
|
||||
|
||||
/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
|
||||
Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
|
||||
- SWCLK, SWDIO, nRESET to output mode and set to default high level.
|
||||
- TDI, nTRST to HighZ mode (pins are unused in SWD mode).
|
||||
*/
|
||||
static __inline void PORT_SWD_SETUP (void) {
|
||||
;
|
||||
}
|
||||
|
||||
/** Disable JTAG/SWD I/O Pins.
|
||||
Disables the DAP Hardware I/O pins which configures:
|
||||
- TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
|
||||
*/
|
||||
static __inline void PORT_OFF (void) {
|
||||
;
|
||||
}
|
||||
|
||||
|
||||
// SWCLK/TCK I/O pin -------------------------------------
|
||||
|
||||
/** SWCLK/TCK I/O pin: Get Input.
|
||||
\return Current status of the SWCLK/TCK DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_SWCLK_TCK_IN (void) {
|
||||
return (0U);
|
||||
}
|
||||
|
||||
/** SWCLK/TCK I/O pin: Set Output to High.
|
||||
Set the SWCLK/TCK DAP hardware I/O pin to high level.
|
||||
*/
|
||||
static __forceinline void PIN_SWCLK_TCK_SET (void) {
|
||||
;
|
||||
}
|
||||
|
||||
/** SWCLK/TCK I/O pin: Set Output to Low.
|
||||
Set the SWCLK/TCK DAP hardware I/O pin to low level.
|
||||
*/
|
||||
static __forceinline void PIN_SWCLK_TCK_CLR (void) {
|
||||
;
|
||||
}
|
||||
|
||||
|
||||
// SWDIO/TMS Pin I/O --------------------------------------
|
||||
|
||||
/** SWDIO/TMS I/O pin: Get Input.
|
||||
\return Current status of the SWDIO/TMS DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_SWDIO_TMS_IN (void) {
|
||||
return (0U);
|
||||
}
|
||||
|
||||
/** SWDIO/TMS I/O pin: Set Output to High.
|
||||
Set the SWDIO/TMS DAP hardware I/O pin to high level.
|
||||
*/
|
||||
static __forceinline void PIN_SWDIO_TMS_SET (void) {
|
||||
;
|
||||
}
|
||||
|
||||
/** SWDIO/TMS I/O pin: Set Output to Low.
|
||||
Set the SWDIO/TMS DAP hardware I/O pin to low level.
|
||||
*/
|
||||
static __forceinline void PIN_SWDIO_TMS_CLR (void) {
|
||||
;
|
||||
}
|
||||
|
||||
/** SWDIO I/O pin: Get Input (used in SWD mode only).
|
||||
\return Current status of the SWDIO DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_SWDIO_IN (void) {
|
||||
return (0U);
|
||||
}
|
||||
|
||||
/** SWDIO I/O pin: Set Output (used in SWD mode only).
|
||||
\param bit Output value for the SWDIO DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline void PIN_SWDIO_OUT (uint32_t bit) {
|
||||
;
|
||||
}
|
||||
|
||||
/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
|
||||
Configure the SWDIO DAP hardware I/O pin to output mode. This function is
|
||||
called prior \ref PIN_SWDIO_OUT function calls.
|
||||
*/
|
||||
static __forceinline void PIN_SWDIO_OUT_ENABLE (void) {
|
||||
;
|
||||
}
|
||||
|
||||
/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
|
||||
Configure the SWDIO DAP hardware I/O pin to input mode. This function is
|
||||
called prior \ref PIN_SWDIO_IN function calls.
|
||||
*/
|
||||
static __forceinline void PIN_SWDIO_OUT_DISABLE (void) {
|
||||
;
|
||||
}
|
||||
|
||||
|
||||
// TDI Pin I/O ---------------------------------------------
|
||||
|
||||
/** TDI I/O pin: Get Input.
|
||||
\return Current status of the TDI DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_TDI_IN (void) {
|
||||
return (0U);
|
||||
}
|
||||
|
||||
/** TDI I/O pin: Set Output.
|
||||
\param bit Output value for the TDI DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline void PIN_TDI_OUT (uint32_t bit) {
|
||||
;
|
||||
}
|
||||
|
||||
|
||||
// TDO Pin I/O ---------------------------------------------
|
||||
|
||||
/** TDO I/O pin: Get Input.
|
||||
\return Current status of the TDO DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_TDO_IN (void) {
|
||||
return (0U);
|
||||
}
|
||||
|
||||
|
||||
// nTRST Pin I/O -------------------------------------------
|
||||
|
||||
/** nTRST I/O pin: Get Input.
|
||||
\return Current status of the nTRST DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_nTRST_IN (void) {
|
||||
return (0U);
|
||||
}
|
||||
|
||||
/** nTRST I/O pin: Set Output.
|
||||
\param bit JTAG TRST Test Reset pin status:
|
||||
- 0: issue a JTAG TRST Test Reset.
|
||||
- 1: release JTAG TRST Test Reset.
|
||||
*/
|
||||
static __forceinline void PIN_nTRST_OUT (uint32_t bit) {
|
||||
;
|
||||
}
|
||||
|
||||
// nRESET Pin I/O------------------------------------------
|
||||
|
||||
/** nRESET I/O pin: Get Input.
|
||||
\return Current status of the nRESET DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_nRESET_IN (void) {
|
||||
return (0U);
|
||||
}
|
||||
|
||||
/** nRESET I/O pin: Set Output.
|
||||
\param bit target device hardware reset pin status:
|
||||
- 0: issue a device hardware reset.
|
||||
- 1: release device hardware reset.
|
||||
*/
|
||||
static __forceinline void PIN_nRESET_OUT (uint32_t bit) {
|
||||
;
|
||||
}
|
||||
|
||||
///@}
|
||||
|
||||
|
||||
//**************************************************************************************************
|
||||
/**
|
||||
\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
|
||||
\ingroup DAP_ConfigIO_gr
|
||||
@{
|
||||
|
||||
CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
|
||||
|
||||
It is recommended to provide the following LEDs for status indication:
|
||||
- Connect LED: is active when the DAP hardware is connected to a debugger.
|
||||
- Running LED: is active when the debugger has put the target device into running state.
|
||||
*/
|
||||
|
||||
/** Debug Unit: Set status of Connected LED.
|
||||
\param bit status of the Connect LED.
|
||||
- 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
|
||||
- 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
|
||||
*/
|
||||
static __inline void LED_CONNECTED_OUT (uint32_t bit) {}
|
||||
|
||||
/** Debug Unit: Set status Target Running LED.
|
||||
\param bit status of the Target Running LED.
|
||||
- 1: Target Running LED ON: program execution in target started.
|
||||
- 0: Target Running LED OFF: program execution in target stopped.
|
||||
*/
|
||||
static __inline void LED_RUNNING_OUT (uint32_t bit) {}
|
||||
|
||||
///@}
|
||||
|
||||
|
||||
//**************************************************************************************************
|
||||
/**
|
||||
\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
|
||||
\ingroup DAP_ConfigIO_gr
|
||||
@{
|
||||
|
||||
CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
|
||||
*/
|
||||
|
||||
/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
|
||||
This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
|
||||
Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
|
||||
- I/O clock system enabled.
|
||||
- all I/O pins: input buffer enabled, output pins are set to HighZ mode.
|
||||
- for nTRST, nRESET a weak pull-up (if available) is enabled.
|
||||
- LED output pins are enabled and LEDs are turned off.
|
||||
*/
|
||||
static __inline void DAP_SETUP (void) {
|
||||
;
|
||||
}
|
||||
|
||||
/** Reset Target Device with custom specific I/O pin or command sequence.
|
||||
This function allows the optional implementation of a device specific reset sequence.
|
||||
It is called when the command \ref DAP_ResetTarget and is for example required
|
||||
when a device needs a time-critical unlock sequence that enables the debug port.
|
||||
\return 0 = no device specific reset sequence is implemented.\n
|
||||
1 = a device specific reset sequence is implemented.
|
||||
*/
|
||||
static __inline uint8_t RESET_TARGET (void) {
|
||||
return (0U); // change to '1' when a device reset sequence is implemented
|
||||
}
|
||||
|
||||
///@}
|
||||
|
||||
|
||||
#endif /* __DAP_CONFIG_H__ */
|
||||
@ -0,0 +1 @@
|
||||
CMSIS-DAP USB HID Firmware for NXP LPC-Link-II board.
|
||||
File diff suppressed because one or more lines are too long
@ -0,0 +1,306 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>LPC4320 SPIFI</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>8</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<nTsel>1</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\UL2CM3.DLL</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>-UV0001BDE -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC180000000 -TP21 -TDS802F -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD10000000 -FC4000 -FN1 -FF0LPC18xx43xx_S25FL032 -FS014000000 -FL0400000</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>1</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>0</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>Source</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>1</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\main.c</PathWithFileName>
|
||||
<FilenameWithoutPath>main.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>2</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\USBD_User_HID_0.c</PathWithFileName>
|
||||
<FilenameWithoutPath>USBD_User_HID_0.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>Documentation</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>2</GroupNumber>
|
||||
<FileNumber>3</FileNumber>
|
||||
<FileType>5</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\Abstract.txt</PathWithFileName>
|
||||
<FilenameWithoutPath>Abstract.txt</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>CMSIS DAP</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>4</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\Source\DAP.c</PathWithFileName>
|
||||
<FilenameWithoutPath>DAP.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>5</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\Source\JTAG_DP.c</PathWithFileName>
|
||||
<FilenameWithoutPath>JTAG_DP.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>6</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\Source\SW_DP.c</PathWithFileName>
|
||||
<FilenameWithoutPath>SW_DP.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>7</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\Source\SWO.c</PathWithFileName>
|
||||
<FilenameWithoutPath>SWO.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::CMSIS Driver</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::Device</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::USB</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
@ -0,0 +1,665 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>LPC4320 SPIFI</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>LPC4320:Cortex-M4</Device>
|
||||
<Vendor>NXP</Vendor>
|
||||
<PackID>Keil.LPC4300_DFP.2.4.0</PackID>
|
||||
<PackURL>http://www.keil.com/pack/</PackURL>
|
||||
<Cpu>IRAM(0x10000000,0x18000) IRAM2(0x20000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD10000000 -FC1000)</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:LPC4320$Device\Include\LPC43xx.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:LPC4320$SVD\LPC43xx.svd</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\Objects\</OutputDirectory>
|
||||
<OutputName>CMSIS_DAP</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments> -MPU</SimDllArguments>
|
||||
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments> -MPU</TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
<Simulator>
|
||||
<UseSimulator>0</UseSimulator>
|
||||
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||
<RunToMain>1</RunToMain>
|
||||
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||
<RestoreFunctions>1</RestoreFunctions>
|
||||
<RestoreToolbox>1</RestoreToolbox>
|
||||
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
|
||||
<RestoreSysVw>1</RestoreSysVw>
|
||||
</Simulator>
|
||||
<Target>
|
||||
<UseTarget>1</UseTarget>
|
||||
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||
<RunToMain>1</RunToMain>
|
||||
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||
<RestoreFunctions>0</RestoreFunctions>
|
||||
<RestoreToolbox>1</RestoreToolbox>
|
||||
<RestoreTracepoints>1</RestoreTracepoints>
|
||||
<RestoreSysVw>1</RestoreSysVw>
|
||||
</Target>
|
||||
<RunDebugAfterBuild>0</RunDebugAfterBuild>
|
||||
<TargetSelection>1</TargetSelection>
|
||||
<SimDlls>
|
||||
<CpuDll></CpuDll>
|
||||
<CpuDllArguments></CpuDllArguments>
|
||||
<PeripheralDll></PeripheralDll>
|
||||
<PeripheralDllArguments></PeripheralDllArguments>
|
||||
<InitializationFile></InitializationFile>
|
||||
</SimDlls>
|
||||
<TargetDlls>
|
||||
<CpuDll></CpuDll>
|
||||
<CpuDllArguments></CpuDllArguments>
|
||||
<PeripheralDll></PeripheralDll>
|
||||
<PeripheralDllArguments></PeripheralDllArguments>
|
||||
<InitializationFile></InitializationFile>
|
||||
<Driver>BIN\UL2CM3.DLL</Driver>
|
||||
</TargetDlls>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4096</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3>"" ()</Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M4"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>1</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>0</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>1</RvdsVP>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>1</StupSel>
|
||||
<useUlib>1</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<RoSelD>0</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>1</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>0</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x10000000</StartAddress>
|
||||
<Size>0x18000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x14000000</StartAddress>
|
||||
<Size>0x400000</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x10000000</StartAddress>
|
||||
<Size>0x18000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x10000</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>4</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>0</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>0</uC99>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>0</v6Lang>
|
||||
<v6LangP>0</v6LangP>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath>.;..\..\Include</IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>1</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x10000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile></ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>Source</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>main.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\main.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>USBD_User_HID_0.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\USBD_User_HID_0.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Documentation</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>Abstract.txt</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Abstract.txt</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>CMSIS DAP</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>DAP.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Source\DAP.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>JTAG_DP.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Source\JTAG_DP.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>SW_DP.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Source\SW_DP.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>SWO.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Source\SWO.c</FilePath>
|
||||
<FileOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>2</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>2</IncludeInBuild>
|
||||
<AlwaysBuild>2</AlwaysBuild>
|
||||
<GenerateAssemblyFile>2</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>2</AssembleAssemblyFile>
|
||||
<PublicsOnly>2</PublicsOnly>
|
||||
<StopOnExitCode>11</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<FileArmAds>
|
||||
<Cads>
|
||||
<interw>2</interw>
|
||||
<Optim>0</Optim>
|
||||
<oTime>2</oTime>
|
||||
<SplitLS>2</SplitLS>
|
||||
<OneElfS>2</OneElfS>
|
||||
<Strict>2</Strict>
|
||||
<EnumInt>2</EnumInt>
|
||||
<PlainCh>2</PlainCh>
|
||||
<Ropi>2</Ropi>
|
||||
<Rwpi>2</Rwpi>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>2</uThumb>
|
||||
<uSurpInc>2</uSurpInc>
|
||||
<uC99>2</uC99>
|
||||
<useXO>2</useXO>
|
||||
<v6Lang>0</v6Lang>
|
||||
<v6LangP>0</v6LangP>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define>USART_PORT=1</Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
</FileArmAds>
|
||||
</FileOption>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::CMSIS Driver</GroupName>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::Device</GroupName>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::USB</GroupName>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis>
|
||||
<api Capiversion="2.01" Cclass="CMSIS Driver" Cgroup="USART" exclusive="0">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</api>
|
||||
<api Capiversion="2.01" Cclass="CMSIS Driver" Cgroup="USB Device" exclusive="0">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</api>
|
||||
<api Capiversion="1.0" Cclass="CMSIS" Cgroup="RTOS" exclusive="1">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</api>
|
||||
</apis>
|
||||
<components>
|
||||
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="4.1.0" condition="CMSIS Core">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cvendor="ARM" Cversion="4.78.0" condition="Cortex-M Device Startup">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="CORE" Cvendor="Keil" Cversion="6.4.0" condition="USB Core">
|
||||
<package name="MDK-Middleware" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="6.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Device" Cvendor="Keil" Cversion="6.4.0" condition="USB Core and Device Driver" maxInstances="4">
|
||||
<package name="MDK-Middleware" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="6.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Device" Csub="HID" Cvendor="Keil" Cversion="6.4.0" condition="USB Device" maxInstances="4">
|
||||
<package name="MDK-Middleware" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="6.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Capiversion="2.01" Cclass="CMSIS Driver" Cgroup="USART" Cvendor="Keil" Cversion="2.07" condition="LPC4300 CMSIS SCU GPDMA">
|
||||
<package name="LPC4300_DFP" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="2.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Capiversion="2.01" Cclass="CMSIS Driver" Cgroup="USB Device" Csub="USB0" Cvendor="Keil" Cversion="2.07" condition="LPC4300 CMSIS SCU">
|
||||
<package name="LPC4300_DFP" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="2.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="GPDMA" Cvendor="Keil" Cversion="1.03" condition="LPC4300 CMSIS">
|
||||
<package name="LPC4300_DFP" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="2.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="SCU" Cvendor="Keil" Cversion="1.00" condition="LPC4300 CMSIS">
|
||||
<package name="LPC4300_DFP" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="2.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="LPC4300 CMSIS">
|
||||
<package name="LPC4300_DFP" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="2.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI">
|
||||
<c>
|
||||
<Define>USE_SPIFI=1</Define>
|
||||
</c>
|
||||
<asm>
|
||||
<Define>NO_CRP</Define>
|
||||
</asm>
|
||||
</targetInfo>
|
||||
</targetInfos>
|
||||
</component>
|
||||
</components>
|
||||
<files>
|
||||
<file attr="config" category="source" name="CMSIS\RTOS\RTX\Templates\RTX_Conf_CM.c" version="4.70.1">
|
||||
<instance index="0">RTE\CMSIS\RTX_Conf_CM.c</instance>
|
||||
<component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cvendor="ARM" Cversion="4.78.0" condition="Cortex-M Device Startup"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="header" name="RTE_Driver\Config\RTE_Device.h" version="2.00">
|
||||
<instance index="0">RTE\Device\LPC4320_Cortex-M4\RTE_Device.h</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="LPC4300 CMSIS"/>
|
||||
<package name="LPC4300_DFP" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="2.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="source" condition="CM4 ARM Compiler" name="Device\Source\ARM\startup_LPC43xx.s">
|
||||
<instance index="0">RTE\Device\LPC4320_Cortex-M4\startup_LPC43xx.s</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="LPC4300 CMSIS"/>
|
||||
<package name="LPC4300_DFP" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="2.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="source" condition="CM4" name="Device\Source\system_LPC43xx.c">
|
||||
<instance index="0">RTE\Device\LPC4320_Cortex-M4\system_LPC43xx.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="LPC4300 CMSIS"/>
|
||||
<package name="LPC4300_DFP" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="2.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="source" name="USB\Config\USBD_Config.c" version="5.00">
|
||||
<instance index="0">RTE\USB\USBD_Config_0.c</instance>
|
||||
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Device" Cvendor="Keil" Cversion="6.4.0" condition="USB Core and Device Driver" maxInstances="4"/>
|
||||
<package name="MDK-Middleware" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="6.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="source" name="USB\Config\USBD_Config_HID.h" version="5.0.1">
|
||||
<instance index="0">RTE\USB\USBD_Config_HID_0.h</instance>
|
||||
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Device" Csub="HID" Cvendor="Keil" Cversion="6.4.0" condition="USB Device" maxInstances="4"/>
|
||||
<package name="MDK-Middleware" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="6.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
</files>
|
||||
</RTE>
|
||||
|
||||
</Project>
|
||||
@ -0,0 +1,506 @@
|
||||
/**************************************************************************//**
|
||||
* @file DAP_config.h
|
||||
* @brief CMSIS-DAP Configuration File for LPC-Link-II
|
||||
* @version V1.10
|
||||
* @date 20. May 2015
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2012-2015 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __DAP_CONFIG_H__
|
||||
#define __DAP_CONFIG_H__
|
||||
|
||||
|
||||
//**************************************************************************************************
|
||||
/**
|
||||
\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
|
||||
\ingroup DAP_ConfigIO_gr
|
||||
@{
|
||||
Provides definitions about the hardware and configuration of the Debug Unit.
|
||||
|
||||
This information includes:
|
||||
- Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
|
||||
- Debug Unit communication packet size.
|
||||
- Debug Access Port communication mode (JTAG or SWD).
|
||||
- Optional information about a connected Target Device (for Evaluation Boards).
|
||||
*/
|
||||
|
||||
#include "LPC43xx.h" // Debug Unit Cortex-M Processor Header File
|
||||
|
||||
/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
|
||||
/// This value is used to calculate the SWD/JTAG clock speed.
|
||||
#define CPU_CLOCK 180000000U ///< Specifies the CPU Clock in Hz
|
||||
|
||||
/// Number of processor cycles for I/O Port write operations.
|
||||
/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
|
||||
/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
|
||||
/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
|
||||
/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
|
||||
/// required.
|
||||
#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
|
||||
|
||||
/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
|
||||
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
|
||||
#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available
|
||||
|
||||
/// Indicate that JTAG communication mode is available at the Debug Port.
|
||||
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
|
||||
#define DAP_JTAG 1 ///< JTAG Mode: 1 = available, 0 = not available.
|
||||
|
||||
/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
|
||||
/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
|
||||
#define DAP_JTAG_DEV_CNT 8U ///< Maximum number of JTAG devices on scan chain
|
||||
|
||||
/// Default communication mode on the Debug Access Port.
|
||||
/// Used for the command \ref DAP_Connect when Port Default mode is selected.
|
||||
#define DAP_DEFAULT_PORT 1U ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
|
||||
|
||||
/// Default communication speed on the Debug Access Port for SWD and JTAG mode.
|
||||
/// Used to initialize the default SWD/JTAG clock frequency.
|
||||
/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
|
||||
#define DAP_DEFAULT_SWJ_CLOCK 1000000U ///< Default SWD/JTAG clock frequency in Hz.
|
||||
|
||||
/// Maximum Package Size for Command and Response data.
|
||||
/// This configuration settings is used to optimized the communication performance with the
|
||||
/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
|
||||
#define DAP_PACKET_SIZE 1024U ///< USB: 64 = Full-Speed, 1024 = High-Speed.
|
||||
|
||||
/// Maximum Package Buffers for Command and Response data.
|
||||
/// This configuration settings is used to optimized the communication performance with the
|
||||
/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
|
||||
/// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
|
||||
#define DAP_PACKET_COUNT 4U ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
|
||||
|
||||
/// Indicate that UART Serial Wire Output (SWO) trace is available.
|
||||
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
|
||||
#define SWO_UART 1 ///< SWO UART: 1 = available, 0 = not available
|
||||
|
||||
/// Maximum SWO UART Baudrate
|
||||
#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz
|
||||
|
||||
/// Indicate that Manchester Serial Wire Output (SWO) trace is available.
|
||||
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
|
||||
#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available
|
||||
|
||||
/// SWO Trace Buffer Size.
|
||||
#define SWO_BUFFER_SIZE 8192U ///< SWO Trace Buffer Size in bytes (must be 2^n)
|
||||
|
||||
|
||||
/// Debug Unit is connected to fixed Target Device.
|
||||
/// The Debug Unit may be part of an evaluation board and always connected to a fixed
|
||||
/// known device. In this case a Device Vendor and Device Name string is stored which
|
||||
/// may be used by the debugger or IDE to configure device parameters.
|
||||
#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
|
||||
|
||||
#if TARGET_DEVICE_FIXED
|
||||
#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor
|
||||
#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device
|
||||
#endif
|
||||
|
||||
///@}
|
||||
|
||||
|
||||
// LPC43xx peripheral register bit masks (used by macros)
|
||||
#define CCU_CLK_CFG_RUN (1U << 0)
|
||||
#define CCU_CLK_CFG_AUTO (1U << 1)
|
||||
#define CCU_CLK_STAT_RUN (1U << 0)
|
||||
#define SCU_SFS_EPD (1U << 3)
|
||||
#define SCU_SFS_EPUN (1U << 4)
|
||||
#define SCU_SFS_EHS (1U << 5)
|
||||
#define SCU_SFS_EZI (1U << 6)
|
||||
#define SCU_SFS_ZIF (1U << 7)
|
||||
|
||||
|
||||
// Debug Port I/O Pins
|
||||
|
||||
// SWCLK/TCK Pin P1_17: GPIO0[12]
|
||||
#define PIN_SWCLK_TCK_PORT 0
|
||||
#define PIN_SWCLK_TCK_BIT 12
|
||||
|
||||
// SWDIO/TMS Pin P1_6: GPIO1[9]
|
||||
#define PIN_SWDIO_TMS_PORT 1
|
||||
#define PIN_SWDIO_TMS_BIT 9
|
||||
|
||||
// SWDIO Output Enable Pin P1_5: GPIO1[8]
|
||||
#define PIN_SWDIO_OE_PORT 1
|
||||
#define PIN_SWDIO_OE_BIT 8
|
||||
|
||||
// TDI Pin P1_18: GPIO0[13]
|
||||
#define PIN_TDI_PORT 0
|
||||
#define PIN_TDI_BIT 13
|
||||
|
||||
// TDO Pin P1_14: GPIO1[7]
|
||||
#define PIN_TDO_PORT 1
|
||||
#define PIN_TDO_BIT 7
|
||||
|
||||
// nTRST Pin Not available
|
||||
#define PIN_nTRST_PORT
|
||||
#define PIN_nTRST_BIT
|
||||
|
||||
// nRESET Pin P2_5: GPIO5[5]
|
||||
#define PIN_nRESET_PORT 5
|
||||
#define PIN_nRESET_BIT 5
|
||||
|
||||
// nRESET Output Enable Pin P2_6: GPIO5[6]
|
||||
#define PIN_nRESET_OE_PORT 5
|
||||
#define PIN_nRESET_OE_BIT 6
|
||||
|
||||
|
||||
// Debug Unit LEDs
|
||||
|
||||
// Connected LED P1_1: GPIO0[8]
|
||||
#define LED_CONNECTED_PORT 0
|
||||
#define LED_CONNECTED_BIT 8
|
||||
|
||||
// Target Running LED Not available
|
||||
|
||||
|
||||
//**************************************************************************************************
|
||||
/**
|
||||
\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
|
||||
\ingroup DAP_ConfigIO_gr
|
||||
@{
|
||||
|
||||
Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
|
||||
and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
|
||||
interface of a device. The following I/O Pins are provided:
|
||||
|
||||
JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
|
||||
---------------------------- | -------------------- | ---------------------------------------------
|
||||
TCK: Test Clock | SWCLK: Clock | Output Push/Pull
|
||||
TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
|
||||
TDI: Test Data Input | | Output Push/Pull
|
||||
TDO: Test Data Output | | Input
|
||||
nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
|
||||
nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
|
||||
|
||||
|
||||
DAP Hardware I/O Pin Access Functions
|
||||
-------------------------------------
|
||||
The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
|
||||
these I/O Pins.
|
||||
|
||||
For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
|
||||
This functions are provided to achieve faster I/O that is possible with some advanced GPIO
|
||||
peripherals that can independently write/read a single I/O pin without affecting any other pins
|
||||
of the same I/O port. The following SWDIO I/O Pin functions are provided:
|
||||
- \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
|
||||
- \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
|
||||
- \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
|
||||
- \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
|
||||
*/
|
||||
|
||||
|
||||
// Configure DAP I/O pins ------------------------------
|
||||
|
||||
// LPC-Link-II HW uses buffers for debug port pins. Therefore it is not
|
||||
// possible to disable outputs SWCLK/TCK, TDI and they are left active.
|
||||
// Only SWDIO/TMS output can be disabled but it is also left active.
|
||||
// nRESET is configured for open drain mode.
|
||||
|
||||
/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
|
||||
Configures the DAP Hardware I/O pins for JTAG mode:
|
||||
- TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
|
||||
- TDO to input mode.
|
||||
*/
|
||||
static __inline void PORT_JTAG_SETUP (void) {
|
||||
LPC_GPIO_PORT->MASK[PIN_SWDIO_TMS_PORT] = 0U;
|
||||
LPC_GPIO_PORT->MASK[PIN_TDI_PORT] = ~(1U << PIN_TDI_BIT);
|
||||
}
|
||||
|
||||
/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
|
||||
Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
|
||||
- SWCLK, SWDIO, nRESET to output mode and set to default high level.
|
||||
- TDI, nTRST to HighZ mode (pins are unused in SWD mode).
|
||||
*/
|
||||
static __inline void PORT_SWD_SETUP (void) {
|
||||
LPC_GPIO_PORT->MASK[PIN_TDI_PORT] = 0U;
|
||||
LPC_GPIO_PORT->MASK[PIN_SWDIO_TMS_PORT] = ~(1U << PIN_SWDIO_TMS_BIT);
|
||||
}
|
||||
|
||||
/** Disable JTAG/SWD I/O Pins.
|
||||
Disables the DAP Hardware I/O pins which configures:
|
||||
- TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
|
||||
*/
|
||||
static __inline void PORT_OFF (void) {
|
||||
LPC_GPIO_PORT->SET[PIN_SWCLK_TCK_PORT] = (1U << PIN_SWCLK_TCK_BIT);
|
||||
LPC_GPIO_PORT->SET[PIN_SWDIO_TMS_PORT] = (1U << PIN_SWDIO_TMS_BIT);
|
||||
LPC_GPIO_PORT->SET[PIN_SWDIO_OE_PORT] = (1U << PIN_SWDIO_OE_BIT);
|
||||
LPC_GPIO_PORT->SET[PIN_TDI_PORT] = (1U << PIN_TDI_BIT);
|
||||
LPC_GPIO_PORT->DIR[PIN_nRESET_PORT] &= ~(1U << PIN_nRESET_BIT);
|
||||
LPC_GPIO_PORT->CLR[PIN_nRESET_OE_PORT] = (1U << PIN_nRESET_OE_BIT);
|
||||
}
|
||||
|
||||
|
||||
// SWCLK/TCK I/O pin -------------------------------------
|
||||
|
||||
/** SWCLK/TCK I/O pin: Get Input.
|
||||
\return Current status of the SWCLK/TCK DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_SWCLK_TCK_IN (void) {
|
||||
return ((LPC_GPIO_PORT->PIN[PIN_SWCLK_TCK_PORT] >> PIN_SWCLK_TCK_BIT) & 1U);
|
||||
}
|
||||
|
||||
/** SWCLK/TCK I/O pin: Set Output to High.
|
||||
Set the SWCLK/TCK DAP hardware I/O pin to high level.
|
||||
*/
|
||||
static __forceinline void PIN_SWCLK_TCK_SET (void) {
|
||||
LPC_GPIO_PORT->SET[PIN_SWCLK_TCK_PORT] = 1U << PIN_SWCLK_TCK_BIT;
|
||||
}
|
||||
|
||||
/** SWCLK/TCK I/O pin: Set Output to Low.
|
||||
Set the SWCLK/TCK DAP hardware I/O pin to low level.
|
||||
*/
|
||||
static __forceinline void PIN_SWCLK_TCK_CLR (void) {
|
||||
LPC_GPIO_PORT->CLR[PIN_SWCLK_TCK_PORT] = 1U << PIN_SWCLK_TCK_BIT;
|
||||
}
|
||||
|
||||
|
||||
// SWDIO/TMS Pin I/O --------------------------------------
|
||||
|
||||
/** SWDIO/TMS I/O pin: Get Input.
|
||||
\return Current status of the SWDIO/TMS DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_SWDIO_TMS_IN (void) {
|
||||
return ((LPC_GPIO_PORT->PIN[PIN_SWDIO_TMS_PORT] >> PIN_SWDIO_TMS_BIT) & 1U);
|
||||
}
|
||||
|
||||
/** SWDIO/TMS I/O pin: Set Output to High.
|
||||
Set the SWDIO/TMS DAP hardware I/O pin to high level.
|
||||
*/
|
||||
static __forceinline void PIN_SWDIO_TMS_SET (void) {
|
||||
LPC_GPIO_PORT->SET[PIN_SWDIO_TMS_PORT] = 1U << PIN_SWDIO_TMS_BIT;
|
||||
}
|
||||
|
||||
/** SWDIO/TMS I/O pin: Set Output to Low.
|
||||
Set the SWDIO/TMS DAP hardware I/O pin to low level.
|
||||
*/
|
||||
static __forceinline void PIN_SWDIO_TMS_CLR (void) {
|
||||
LPC_GPIO_PORT->CLR[PIN_SWDIO_TMS_PORT] = 1U << PIN_SWDIO_TMS_BIT;
|
||||
}
|
||||
|
||||
/** SWDIO I/O pin: Get Input (used in SWD mode only).
|
||||
\return Current status of the SWDIO DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_SWDIO_IN (void) {
|
||||
return (LPC_GPIO_PORT->MPIN[PIN_SWDIO_TMS_PORT] >> PIN_SWDIO_TMS_BIT);
|
||||
}
|
||||
|
||||
/** SWDIO I/O pin: Set Output (used in SWD mode only).
|
||||
\param bit Output value for the SWDIO DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline void PIN_SWDIO_OUT (uint32_t bit) {
|
||||
LPC_GPIO_PORT->MPIN[PIN_SWDIO_TMS_PORT] = bit << PIN_SWDIO_TMS_BIT;
|
||||
}
|
||||
|
||||
/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
|
||||
Configure the SWDIO DAP hardware I/O pin to output mode. This function is
|
||||
called prior \ref PIN_SWDIO_OUT function calls.
|
||||
*/
|
||||
static __forceinline void PIN_SWDIO_OUT_ENABLE (void) {
|
||||
LPC_GPIO_PORT->SET[PIN_SWDIO_OE_PORT] = 1U << PIN_SWDIO_OE_BIT;
|
||||
}
|
||||
|
||||
/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
|
||||
Configure the SWDIO DAP hardware I/O pin to input mode. This function is
|
||||
called prior \ref PIN_SWDIO_IN function calls.
|
||||
*/
|
||||
static __forceinline void PIN_SWDIO_OUT_DISABLE (void) {
|
||||
LPC_GPIO_PORT->CLR[PIN_SWDIO_OE_PORT] = 1U << PIN_SWDIO_OE_BIT;
|
||||
}
|
||||
|
||||
|
||||
// TDI Pin I/O ---------------------------------------------
|
||||
|
||||
/** TDI I/O pin: Get Input.
|
||||
\return Current status of the TDI DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_TDI_IN (void) {
|
||||
return ((LPC_GPIO_PORT->PIN [PIN_TDI_PORT] >> PIN_TDI_BIT) & 1U);
|
||||
}
|
||||
|
||||
/** TDI I/O pin: Set Output.
|
||||
\param bit Output value for the TDI DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline void PIN_TDI_OUT (uint32_t bit) {
|
||||
LPC_GPIO_PORT->MPIN[PIN_TDI_PORT] = bit << PIN_TDI_BIT;
|
||||
}
|
||||
|
||||
|
||||
// TDO Pin I/O ---------------------------------------------
|
||||
|
||||
/** TDO I/O pin: Get Input.
|
||||
\return Current status of the TDO DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_TDO_IN (void) {
|
||||
return ((LPC_GPIO_PORT->PIN[PIN_TDO_PORT] >> PIN_TDO_BIT) & 1U);
|
||||
}
|
||||
|
||||
|
||||
// nTRST Pin I/O -------------------------------------------
|
||||
|
||||
/** nTRST I/O pin: Get Input.
|
||||
\return Current status of the nTRST DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_nTRST_IN (void) {
|
||||
return (0U); // Not available
|
||||
}
|
||||
|
||||
/** nTRST I/O pin: Set Output.
|
||||
\param bit JTAG TRST Test Reset pin status:
|
||||
- 0: issue a JTAG TRST Test Reset.
|
||||
- 1: release JTAG TRST Test Reset.
|
||||
*/
|
||||
static __forceinline void PIN_nTRST_OUT (uint32_t bit) {
|
||||
; // Not available
|
||||
}
|
||||
|
||||
// nRESET Pin I/O------------------------------------------
|
||||
|
||||
/** nRESET I/O pin: Get Input.
|
||||
\return Current status of the nRESET DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_nRESET_IN (void) {
|
||||
return ((LPC_GPIO_PORT->PIN[PIN_nRESET_PORT] >> PIN_nRESET_BIT) & 1U);
|
||||
}
|
||||
|
||||
/** nRESET I/O pin: Set Output.
|
||||
\param bit target device hardware reset pin status:
|
||||
- 0: issue a device hardware reset.
|
||||
- 1: release device hardware reset.
|
||||
*/
|
||||
static __forceinline void PIN_nRESET_OUT (uint32_t bit) {
|
||||
if (bit) {
|
||||
LPC_GPIO_PORT->DIR[PIN_nRESET_PORT] &= ~(1U << PIN_nRESET_BIT);
|
||||
LPC_GPIO_PORT->CLR[PIN_nRESET_OE_PORT] = (1U << PIN_nRESET_OE_BIT);
|
||||
} else {
|
||||
LPC_GPIO_PORT->SET[PIN_nRESET_OE_PORT] = (1U << PIN_nRESET_OE_BIT);
|
||||
LPC_GPIO_PORT->DIR[PIN_nRESET_PORT] |= (1U << PIN_nRESET_BIT);
|
||||
}
|
||||
}
|
||||
|
||||
///@}
|
||||
|
||||
|
||||
//**************************************************************************************************
|
||||
/**
|
||||
\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
|
||||
\ingroup DAP_ConfigIO_gr
|
||||
@{
|
||||
|
||||
CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
|
||||
|
||||
It is recommended to provide the following LEDs for status indication:
|
||||
- Connect LED: is active when the DAP hardware is connected to a debugger.
|
||||
- Running LED: is active when the debugger has put the target device into running state.
|
||||
*/
|
||||
|
||||
/** Debug Unit: Set status of Connected LED.
|
||||
\param bit status of the Connect LED.
|
||||
- 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
|
||||
- 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
|
||||
*/
|
||||
static __inline void LED_CONNECTED_OUT (uint32_t bit) {
|
||||
LPC_GPIO_PORT->B[32*LED_CONNECTED_PORT + LED_CONNECTED_BIT] = bit;
|
||||
}
|
||||
|
||||
/** Debug Unit: Set status Target Running LED.
|
||||
\param bit status of the Target Running LED.
|
||||
- 1: Target Running LED ON: program execution in target started.
|
||||
- 0: Target Running LED OFF: program execution in target stopped.
|
||||
*/
|
||||
static __inline void LED_RUNNING_OUT (uint32_t bit) {
|
||||
; // Not available
|
||||
}
|
||||
|
||||
///@}
|
||||
|
||||
|
||||
//**************************************************************************************************
|
||||
/**
|
||||
\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
|
||||
\ingroup DAP_ConfigIO_gr
|
||||
@{
|
||||
|
||||
CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
|
||||
*/
|
||||
|
||||
/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
|
||||
This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
|
||||
Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
|
||||
- I/O clock system enabled.
|
||||
- all I/O pins: input buffer enabled, output pins are set to HighZ mode.
|
||||
- for nTRST, nRESET a weak pull-up (if available) is enabled.
|
||||
- LED output pins are enabled and LEDs are turned off.
|
||||
*/
|
||||
static __inline void DAP_SETUP (void) {
|
||||
|
||||
/* Enable clock and init GPIO outputs */
|
||||
LPC_CCU1->CLK_M4_GPIO_CFG = CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN;
|
||||
while (!(LPC_CCU1->CLK_M4_GPIO_STAT & CCU_CLK_STAT_RUN));
|
||||
|
||||
/* Configure I/O pins: function number, input buffer enabled, */
|
||||
/* no pull-up/down except nRESET (pull-up) */
|
||||
LPC_SCU->SFSP1_17 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* SWCLK/TCK: GPIO0[12] */
|
||||
LPC_SCU->SFSP1_6 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* SWDIO/TMS: GPIO1[9] */
|
||||
LPC_SCU->SFSP1_5 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* SWDIO_OE: GPIO1[8] */
|
||||
LPC_SCU->SFSP1_18 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* TDI: GPIO0[13] */
|
||||
LPC_SCU->SFSP1_14 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* TDO: GPIO1[7] */
|
||||
LPC_SCU->SFSP2_5 = 4U | SCU_SFS_EZI; /* nRESET: GPIO5[5] */
|
||||
LPC_SCU->SFSP2_6 = 4U | SCU_SFS_EPUN|SCU_SFS_EZI; /* nRESET_OE: GPIO5[6] */
|
||||
LPC_SCU->SFSP1_1 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* LED: GPIO0[8] */
|
||||
|
||||
/* Configure: SWCLK/TCK, SWDIO/TMS, SWDIO_OE, TDI as outputs (high level) */
|
||||
/* TDO as input */
|
||||
/* nRESET as input with output latch set to low level */
|
||||
/* nRESET_OE as output (low level) */
|
||||
LPC_GPIO_PORT->SET[PIN_SWCLK_TCK_PORT] = (1U << PIN_SWCLK_TCK_BIT);
|
||||
LPC_GPIO_PORT->SET[PIN_SWDIO_TMS_PORT] = (1U << PIN_SWDIO_TMS_BIT);
|
||||
LPC_GPIO_PORT->SET[PIN_SWDIO_OE_PORT] = (1U << PIN_SWDIO_OE_BIT);
|
||||
LPC_GPIO_PORT->SET[PIN_TDI_PORT] = (1U << PIN_TDI_BIT);
|
||||
LPC_GPIO_PORT->CLR[PIN_nRESET_PORT] = (1U << PIN_nRESET_BIT);
|
||||
LPC_GPIO_PORT->CLR[PIN_nRESET_OE_PORT] = (1U << PIN_nRESET_OE_BIT);
|
||||
LPC_GPIO_PORT->DIR[PIN_SWCLK_TCK_PORT] |= (1U << PIN_SWCLK_TCK_BIT);
|
||||
LPC_GPIO_PORT->DIR[PIN_SWDIO_TMS_PORT] |= (1U << PIN_SWDIO_TMS_BIT);
|
||||
LPC_GPIO_PORT->DIR[PIN_SWDIO_OE_PORT] |= (1U << PIN_SWDIO_OE_BIT);
|
||||
LPC_GPIO_PORT->DIR[PIN_TDI_PORT] |= (1U << PIN_TDI_BIT);
|
||||
LPC_GPIO_PORT->DIR[PIN_TDO_PORT] &= ~(1U << PIN_TDO_BIT);
|
||||
LPC_GPIO_PORT->DIR[PIN_nRESET_PORT] &= ~(1U << PIN_nRESET_BIT);
|
||||
LPC_GPIO_PORT->DIR[PIN_nRESET_OE_PORT] |= (1U << PIN_nRESET_OE_BIT);
|
||||
|
||||
/* Configure: LED as output (turned off) */
|
||||
LPC_GPIO_PORT->CLR[LED_CONNECTED_PORT] = (1U << LED_CONNECTED_BIT);
|
||||
LPC_GPIO_PORT->DIR[LED_CONNECTED_PORT] |= (1U << LED_CONNECTED_BIT);
|
||||
|
||||
/* Configure Peripheral Interrupt Priorities */
|
||||
NVIC_SetPriority(USB0_IRQn, 1U);
|
||||
}
|
||||
|
||||
/** Reset Target Device with custom specific I/O pin or command sequence.
|
||||
This function allows the optional implementation of a device specific reset sequence.
|
||||
It is called when the command \ref DAP_ResetTarget and is for example required
|
||||
when a device needs a time-critical unlock sequence that enables the debug port.
|
||||
\return 0 = no device specific reset sequence is implemented.\n
|
||||
1 = a device specific reset sequence is implemented.
|
||||
*/
|
||||
static __inline uint32_t RESET_TARGET (void) {
|
||||
return (0); // change to '1' when a device reset sequence is implemented
|
||||
}
|
||||
|
||||
///@}
|
||||
|
||||
|
||||
#endif /* __DAP_CONFIG_H__ */
|
||||
@ -0,0 +1,311 @@
|
||||
/*----------------------------------------------------------------------------
|
||||
* CMSIS-RTOS - RTX
|
||||
*----------------------------------------------------------------------------
|
||||
* Name: RTX_Conf_CM.C
|
||||
* Purpose: Configuration of CMSIS RTX Kernel for Cortex-M
|
||||
* Rev.: V4.70.1
|
||||
*----------------------------------------------------------------------------
|
||||
*
|
||||
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
|
||||
* All rights reserved.
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* - Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without
|
||||
* specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#include "cmsis_os.h"
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* RTX User configuration part BEGIN
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
|
||||
//
|
||||
// <h>Thread Configuration
|
||||
// =======================
|
||||
//
|
||||
// <o>Number of concurrent running user threads <1-250>
|
||||
// <i> Defines max. number of user threads that will run at the same time.
|
||||
// <i> Default: 6
|
||||
#ifndef OS_TASKCNT
|
||||
#define OS_TASKCNT 4
|
||||
#endif
|
||||
|
||||
// <o>Default Thread stack size [bytes] <64-4096:8><#/4>
|
||||
// <i> Defines default stack size for threads with osThreadDef stacksz = 0
|
||||
// <i> Default: 200
|
||||
#ifndef OS_STKSIZE
|
||||
#define OS_STKSIZE 64 // this stack size value is in words
|
||||
#endif
|
||||
|
||||
// <o>Main Thread stack size [bytes] <64-32768:8><#/4>
|
||||
// <i> Defines stack size for main thread.
|
||||
// <i> Default: 200
|
||||
#ifndef OS_MAINSTKSIZE
|
||||
#define OS_MAINSTKSIZE 128 // this stack size value is in words
|
||||
#endif
|
||||
|
||||
// <o>Number of threads with user-provided stack size <0-250>
|
||||
// <i> Defines the number of threads with user-provided stack size.
|
||||
// <i> Default: 0
|
||||
#ifndef OS_PRIVCNT
|
||||
#define OS_PRIVCNT 3
|
||||
#endif
|
||||
|
||||
// <o>Total stack size [bytes] for threads with user-provided stack size <0-1048576:8><#/4>
|
||||
// <i> Defines the combined stack size for threads with user-provided stack size.
|
||||
// <i> Default: 0
|
||||
#ifndef OS_PRIVSTKSIZE
|
||||
#define OS_PRIVSTKSIZE 384 // this stack size value is in words
|
||||
#endif
|
||||
|
||||
// <q>Stack overflow checking
|
||||
// <i> Enable stack overflow checks at thread switch.
|
||||
// <i> Enabling this option increases slightly the execution time of a thread switch.
|
||||
#ifndef OS_STKCHECK
|
||||
#define OS_STKCHECK 1
|
||||
#endif
|
||||
|
||||
// <q>Stack usage watermark
|
||||
// <i> Initialize thread stack with watermark pattern for analyzing stack usage (current/maximum) in System and Thread Viewer.
|
||||
// <i> Enabling this option increases significantly the execution time of osThreadCreate.
|
||||
#ifndef OS_STKINIT
|
||||
#define OS_STKINIT 0
|
||||
#endif
|
||||
|
||||
// <o>Processor mode for thread execution
|
||||
// <0=> Unprivileged mode
|
||||
// <1=> Privileged mode
|
||||
// <i> Default: Privileged mode
|
||||
#ifndef OS_RUNPRIV
|
||||
#define OS_RUNPRIV 1
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>RTX Kernel Timer Tick Configuration
|
||||
// ======================================
|
||||
// <q> Use Cortex-M SysTick timer as RTX Kernel Timer
|
||||
// <i> Cortex-M processors provide in most cases a SysTick timer that can be used as
|
||||
// <i> as time-base for RTX.
|
||||
#ifndef OS_SYSTICK
|
||||
#define OS_SYSTICK 1
|
||||
#endif
|
||||
//
|
||||
// <o>RTOS Kernel Timer input clock frequency [Hz] <1-1000000000>
|
||||
// <i> Defines the input frequency of the RTOS Kernel Timer.
|
||||
// <i> When the Cortex-M SysTick timer is used, the input clock
|
||||
// <i> is on most systems identical with the core clock.
|
||||
#ifndef OS_CLOCK
|
||||
#define OS_CLOCK 180000000
|
||||
#endif
|
||||
|
||||
// <o>RTX Timer tick interval value [us] <1-1000000>
|
||||
// <i> The RTX Timer tick interval value is used to calculate timeout values.
|
||||
// <i> When the Cortex-M SysTick timer is enabled, the value also configures the SysTick timer.
|
||||
// <i> Default: 1000 (1ms)
|
||||
#ifndef OS_TICK
|
||||
#define OS_TICK 1000
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>System Configuration
|
||||
// =======================
|
||||
//
|
||||
// <e>Round-Robin Thread switching
|
||||
// ===============================
|
||||
//
|
||||
// <i> Enables Round-Robin Thread switching.
|
||||
#ifndef OS_ROBIN
|
||||
#define OS_ROBIN 1
|
||||
#endif
|
||||
|
||||
// <o>Round-Robin Timeout [ticks] <1-1000>
|
||||
// <i> Defines how long a thread will execute before a thread switch.
|
||||
// <i> Default: 5
|
||||
#ifndef OS_ROBINTOUT
|
||||
#define OS_ROBINTOUT 5
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e>User Timers
|
||||
// ==============
|
||||
// <i> Enables user Timers
|
||||
#ifndef OS_TIMERS
|
||||
#define OS_TIMERS 1
|
||||
#endif
|
||||
|
||||
// <o>Timer Thread Priority
|
||||
// <1=> Low
|
||||
// <2=> Below Normal <3=> Normal <4=> Above Normal
|
||||
// <5=> High
|
||||
// <6=> Realtime (highest)
|
||||
// <i> Defines priority for Timer Thread
|
||||
// <i> Default: High
|
||||
#ifndef OS_TIMERPRIO
|
||||
#define OS_TIMERPRIO 5
|
||||
#endif
|
||||
|
||||
// <o>Timer Thread stack size [bytes] <64-4096:8><#/4>
|
||||
// <i> Defines stack size for Timer thread.
|
||||
// <i> Default: 200
|
||||
#ifndef OS_TIMERSTKSZ
|
||||
#define OS_TIMERSTKSZ 128 // this stack size value is in words
|
||||
#endif
|
||||
|
||||
// <o>Timer Callback Queue size <1-32>
|
||||
// <i> Number of concurrent active timer callback functions.
|
||||
// <i> Default: 4
|
||||
#ifndef OS_TIMERCBQS
|
||||
#define OS_TIMERCBQS 4
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <o>ISR FIFO Queue size<4=> 4 entries <8=> 8 entries
|
||||
// <12=> 12 entries <16=> 16 entries
|
||||
// <24=> 24 entries <32=> 32 entries
|
||||
// <48=> 48 entries <64=> 64 entries
|
||||
// <96=> 96 entries
|
||||
// <i> ISR functions store requests to this buffer,
|
||||
// <i> when they are called from the interrupt handler.
|
||||
// <i> Default: 16 entries
|
||||
#ifndef OS_FIFOSZ
|
||||
#define OS_FIFOSZ 16
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
//------------- <<< end of configuration section >>> -----------------------
|
||||
|
||||
// Standard library system mutexes
|
||||
// ===============================
|
||||
// Define max. number system mutexes that are used to protect
|
||||
// the arm standard runtime library. For microlib they are not used.
|
||||
#ifndef OS_MUTEXCNT
|
||||
#define OS_MUTEXCNT 8
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* RTX User configuration part END
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Global Functions
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
/*--------------------------- os_idle_demon ---------------------------------*/
|
||||
|
||||
/// \brief The idle demon is running when no other thread is ready to run
|
||||
void os_idle_demon (void) {
|
||||
|
||||
for (;;) {
|
||||
/* HERE: include optional user code to be executed when no thread runs.*/
|
||||
}
|
||||
}
|
||||
|
||||
#if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer
|
||||
|
||||
/*--------------------------- os_tick_init ----------------------------------*/
|
||||
|
||||
/// \brief Initializes an alternative hardware timer as RTX kernel timer
|
||||
/// \return IRQ number of the alternative hardware timer
|
||||
int os_tick_init (void) {
|
||||
return (-1); /* Return IRQ number of timer (0..239) */
|
||||
}
|
||||
|
||||
/*--------------------------- os_tick_val -----------------------------------*/
|
||||
|
||||
/// \brief Get alternative hardware timer's current value (0 .. OS_TRV)
|
||||
/// \return Current value of the alternative hardware timer
|
||||
uint32_t os_tick_val (void) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*--------------------------- os_tick_ovf -----------------------------------*/
|
||||
|
||||
/// \brief Get alternative hardware timer's overflow flag
|
||||
/// \return Overflow flag\n
|
||||
/// - 1 : overflow
|
||||
/// - 0 : no overflow
|
||||
uint32_t os_tick_ovf (void) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*--------------------------- os_tick_irqack --------------------------------*/
|
||||
|
||||
/// \brief Acknowledge alternative hardware timer interrupt
|
||||
void os_tick_irqack (void) {
|
||||
/* ... */
|
||||
}
|
||||
|
||||
#endif // (OS_SYSTICK == 0)
|
||||
|
||||
/*--------------------------- os_error --------------------------------------*/
|
||||
|
||||
/* OS Error Codes */
|
||||
#define OS_ERROR_STACK_OVF 1
|
||||
#define OS_ERROR_FIFO_OVF 2
|
||||
#define OS_ERROR_MBX_OVF 3
|
||||
#define OS_ERROR_TIMER_OVF 4
|
||||
|
||||
extern osThreadId svcThreadGetId (void);
|
||||
|
||||
/// \brief Called when a runtime error is detected
|
||||
/// \param[in] error_code actual error code that has been detected
|
||||
void os_error (uint32_t error_code) {
|
||||
|
||||
/* HERE: include optional code to be executed on runtime error. */
|
||||
switch (error_code) {
|
||||
case OS_ERROR_STACK_OVF:
|
||||
/* Stack overflow detected for the currently running task. */
|
||||
/* Thread can be identified by calling svcThreadGetId(). */
|
||||
break;
|
||||
case OS_ERROR_FIFO_OVF:
|
||||
/* ISR FIFO Queue buffer overflow detected. */
|
||||
break;
|
||||
case OS_ERROR_MBX_OVF:
|
||||
/* Mailbox overflow detected. */
|
||||
break;
|
||||
case OS_ERROR_TIMER_OVF:
|
||||
/* User Timer Callback Queue overflow detected. */
|
||||
break;
|
||||
}
|
||||
for (;;);
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* RTX Configuration Functions
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#include "RTX_CM_lib.h"
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* end of file
|
||||
*---------------------------------------------------------------------------*/
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,333 @@
|
||||
;/**************************************************************************//**
|
||||
; * @file LPC43xx.s
|
||||
; * @brief CMSIS Cortex-M4 Core Device Startup File for
|
||||
; * NXP LPC43xxDevice Series
|
||||
; * @version V1.00
|
||||
; * @date 03. September 2013
|
||||
; *
|
||||
; * @note
|
||||
; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
|
||||
; *
|
||||
; * @par
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * @par
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000200
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
|
||||
Sign_Value EQU 0x5A5A5A5A
|
||||
|
||||
__Vectors DCD __initial_sp ; 0 Top of Stack
|
||||
DCD Reset_Handler ; 1 Reset Handler
|
||||
DCD NMI_Handler ; 2 NMI Handler
|
||||
DCD HardFault_Handler ; 3 Hard Fault Handler
|
||||
DCD MemManage_Handler ; 4 MPU Fault Handler
|
||||
DCD BusFault_Handler ; 5 Bus Fault Handler
|
||||
DCD UsageFault_Handler ; 6 Usage Fault Handler
|
||||
DCD Sign_Value ; 7 Reserved
|
||||
DCD 0 ; 8 Reserved
|
||||
DCD 0 ; 9 Reserved
|
||||
DCD 0 ; 10 Reserved
|
||||
DCD SVC_Handler ; 11 SVCall Handler
|
||||
DCD DebugMon_Handler ; 12 Debug Monitor Handler
|
||||
DCD 0 ; 13 Reserved
|
||||
DCD PendSV_Handler ; 14 PendSV Handler
|
||||
DCD SysTick_Handler ; 15 SysTick Handler
|
||||
|
||||
; External LPC43xx/M4 Interrupts
|
||||
DCD DAC_IRQHandler ; 0 DAC interrupt
|
||||
DCD M0APP_IRQHandler ; 1 Cortex-M0APP; Latched TXEV; for M4-M0APP communication
|
||||
DCD DMA_IRQHandler ; 2 DMA interrupt
|
||||
DCD 0 ; 3 Reserved
|
||||
DCD FLASHEEPROM_IRQHandler ; 4 flash bank A, flash bank B, EEPROM ORed interrupt
|
||||
DCD ETHERNET_IRQHandler ; 5 Ethernet interrupt
|
||||
DCD SDIO_IRQHandler ; 6 SD/MMC interrupt
|
||||
DCD LCD_IRQHandler ; 7 LCD interrupt
|
||||
DCD USB0_IRQHandler ; 8 OTG interrupt
|
||||
DCD USB1_IRQHandler ; 9 USB1 interrupt
|
||||
DCD SCT_IRQHandler ; 10 SCT combined interrupt
|
||||
DCD RITIMER_IRQHandler ; 11 RI Timer interrupt
|
||||
DCD TIMER0_IRQHandler ; 12 Timer 0 interrupt
|
||||
DCD TIMER1_IRQHandler ; 13 Timer 1 interrupt
|
||||
DCD TIMER2_IRQHandler ; 14 Timer 2 interrupt
|
||||
DCD TIMER3_IRQHandler ; 15 Timer 3 interrupt
|
||||
DCD MCPWM_IRQHandler ; 16 Motor control PWM interrupt
|
||||
DCD ADC0_IRQHandler ; 17 ADC0 interrupt
|
||||
DCD I2C0_IRQHandler ; 18 I2C0 interrupt
|
||||
DCD I2C1_IRQHandler ; 19 I2C1 interrupt
|
||||
DCD SPI_IRQHandler ; 20 SPI interrupt
|
||||
DCD ADC1_IRQHandler ; 21 ADC1 interrupt
|
||||
DCD SSP0_IRQHandler ; 22 SSP0 interrupt
|
||||
DCD SSP1_IRQHandler ; 23 SSP1 interrupt
|
||||
DCD USART0_IRQHandler ; 24 USART0 interrupt
|
||||
DCD UART1_IRQHandler ; 25 Combined UART1, Modem interrupt
|
||||
DCD USART2_IRQHandler ; 26 USART2 interrupt
|
||||
DCD USART3_IRQHandler ; 27 Combined USART3, IrDA interrupt
|
||||
DCD I2S0_IRQHandler ; 28 I2S0 interrupt
|
||||
DCD I2S1_IRQHandler ; 29 I2S1 interrupt
|
||||
DCD SPIFI_IRQHandler ; 30 SPISI interrupt
|
||||
DCD SGPIO_IRQHandler ; 31 SGPIO interrupt
|
||||
DCD PIN_INT0_IRQHandler ; 32 GPIO pin interrupt 0
|
||||
DCD PIN_INT1_IRQHandler ; 33 GPIO pin interrupt 1
|
||||
DCD PIN_INT2_IRQHandler ; 34 GPIO pin interrupt 2
|
||||
DCD PIN_INT3_IRQHandler ; 35 GPIO pin interrupt 3
|
||||
DCD PIN_INT4_IRQHandler ; 36 GPIO pin interrupt 4
|
||||
DCD PIN_INT5_IRQHandler ; 37 GPIO pin interrupt 5
|
||||
DCD PIN_INT6_IRQHandler ; 38 GPIO pin interrupt 6
|
||||
DCD PIN_INT7_IRQHandler ; 39 GPIO pin interrupt 7
|
||||
DCD GINT0_IRQHandler ; 40 GPIO global interrupt 0
|
||||
DCD GINT1_IRQHandler ; 41 GPIO global interrupt 1
|
||||
DCD EVENTROUTER_IRQHandler ; 42 Event router interrupt
|
||||
DCD C_CAN1_IRQHandler ; 43 C_CAN1 interrupt
|
||||
DCD 0 ; 44 Reserved
|
||||
DCD ADCHS_IRQHandler ; 45 ADCHS combined interrupt
|
||||
DCD ATIMER_IRQHandler ; 46 Alarm timer interrupt
|
||||
DCD RTC_IRQHandler ; 47 RTC interrupt
|
||||
DCD 0 ; 48 Reserved
|
||||
DCD WWDT_IRQHandler ; 49 WWDT interrupt
|
||||
DCD M0SUB_IRQHandler ; 50 TXEV instruction from the M0 subsystem core interrupt
|
||||
DCD C_CAN0_IRQHandler ; 51 C_CAN0 interrupt
|
||||
DCD QEI_IRQHandler ; 52 QEI interrupt
|
||||
|
||||
|
||||
;CRP address at offset 0x2FC relative to the BOOT Bank address
|
||||
IF :LNOT::DEF:NO_CRP
|
||||
SPACE (0x2FC - (. - __Vectors))
|
||||
; EXPORT CRP_Key
|
||||
CRP_Key DCD 0xFFFFFFFF
|
||||
; 0xFFFFFFFF => CRP Disabled
|
||||
; 0x12345678 => CRP Level 1
|
||||
; 0x87654321 => CRP Level 2
|
||||
; 0x43218765 => CRP Level 3 (ARE YOU SURE?)
|
||||
; 0x4E697370 => NO ISP (ARE YOU SURE?)
|
||||
ENDIF
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT DAC_IRQHandler [WEAK]
|
||||
EXPORT M0APP_IRQHandler [WEAK]
|
||||
EXPORT DMA_IRQHandler [WEAK]
|
||||
EXPORT FLASHEEPROM_IRQHandler [WEAK]
|
||||
EXPORT ETHERNET_IRQHandler [WEAK]
|
||||
EXPORT SDIO_IRQHandler [WEAK]
|
||||
EXPORT LCD_IRQHandler [WEAK]
|
||||
EXPORT USB0_IRQHandler [WEAK]
|
||||
EXPORT USB1_IRQHandler [WEAK]
|
||||
EXPORT SCT_IRQHandler [WEAK]
|
||||
EXPORT RITIMER_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT TIMER3_IRQHandler [WEAK]
|
||||
EXPORT MCPWM_IRQHandler [WEAK]
|
||||
EXPORT ADC0_IRQHandler [WEAK]
|
||||
EXPORT I2C0_IRQHandler [WEAK]
|
||||
EXPORT I2C1_IRQHandler [WEAK]
|
||||
EXPORT SPI_IRQHandler [WEAK]
|
||||
EXPORT ADC1_IRQHandler [WEAK]
|
||||
EXPORT SSP0_IRQHandler [WEAK]
|
||||
EXPORT SSP1_IRQHandler [WEAK]
|
||||
EXPORT USART0_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT I2S0_IRQHandler [WEAK]
|
||||
EXPORT I2S1_IRQHandler [WEAK]
|
||||
EXPORT SPIFI_IRQHandler [WEAK]
|
||||
EXPORT SGPIO_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT0_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT1_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT2_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT3_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT4_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT5_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT6_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT7_IRQHandler [WEAK]
|
||||
EXPORT GINT0_IRQHandler [WEAK]
|
||||
EXPORT GINT1_IRQHandler [WEAK]
|
||||
EXPORT EVENTROUTER_IRQHandler [WEAK]
|
||||
EXPORT C_CAN1_IRQHandler [WEAK]
|
||||
EXPORT ADCHS_IRQHandler [WEAK]
|
||||
EXPORT ATIMER_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT WWDT_IRQHandler [WEAK]
|
||||
EXPORT M0SUB_IRQHandler [WEAK]
|
||||
EXPORT C_CAN0_IRQHandler [WEAK]
|
||||
EXPORT QEI_IRQHandler [WEAK]
|
||||
|
||||
DAC_IRQHandler
|
||||
M0APP_IRQHandler
|
||||
DMA_IRQHandler
|
||||
FLASHEEPROM_IRQHandler
|
||||
ETHERNET_IRQHandler
|
||||
SDIO_IRQHandler
|
||||
LCD_IRQHandler
|
||||
USB0_IRQHandler
|
||||
USB1_IRQHandler
|
||||
SCT_IRQHandler
|
||||
RITIMER_IRQHandler
|
||||
TIMER0_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
TIMER3_IRQHandler
|
||||
MCPWM_IRQHandler
|
||||
ADC0_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
SPI_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
SSP0_IRQHandler
|
||||
SSP1_IRQHandler
|
||||
USART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
I2S0_IRQHandler
|
||||
I2S1_IRQHandler
|
||||
SPIFI_IRQHandler
|
||||
SGPIO_IRQHandler
|
||||
PIN_INT0_IRQHandler
|
||||
PIN_INT1_IRQHandler
|
||||
PIN_INT2_IRQHandler
|
||||
PIN_INT3_IRQHandler
|
||||
PIN_INT4_IRQHandler
|
||||
PIN_INT5_IRQHandler
|
||||
PIN_INT6_IRQHandler
|
||||
PIN_INT7_IRQHandler
|
||||
GINT0_IRQHandler
|
||||
GINT1_IRQHandler
|
||||
EVENTROUTER_IRQHandler
|
||||
C_CAN1_IRQHandler
|
||||
ADCHS_IRQHandler
|
||||
ATIMER_IRQHandler
|
||||
RTC_IRQHandler
|
||||
WWDT_IRQHandler
|
||||
M0SUB_IRQHandler
|
||||
C_CAN0_IRQHandler
|
||||
QEI_IRQHandler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
@ -0,0 +1,910 @@
|
||||
/* -----------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 - 2014 ARM Ltd.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied warranty.
|
||||
* In no event will the authors be held liable for any damages arising from
|
||||
* the use of this software. Permission is granted to anyone to use this
|
||||
* software for any purpose, including commercial applications, and to alter
|
||||
* it and redistribute it freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software in
|
||||
* a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
*
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
*
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* $Date: 16/06/16 3:27p $Revision: V5.00
|
||||
*
|
||||
* Project: NXP LPC43xx System initialization
|
||||
* -------------------------------------------------------------------------- */
|
||||
|
||||
#include "LPC43xx.h"
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
This file configures the clocks as follows:
|
||||
-----------------------------------------------------------------------------
|
||||
Clock Unit | Output clock | Source clock | Note
|
||||
-----------------------------------------------------------------------------
|
||||
PLL0USB | 480 MHz | XTAL | External crystal @ 12 MHz
|
||||
-----------------------------------------------------------------------------
|
||||
PLL1 | 180 MHz | XTAL | External crystal @ 12 MHz
|
||||
-----------------------------------------------------------------------------
|
||||
CPU | 180 MHz | PLL1 | CPU Clock == BASE_M4_CLK
|
||||
-----------------------------------------------------------------------------
|
||||
IDIV A | 60 MHz | PLL1 | To the USB1 peripheral
|
||||
-----------------------------------------------------------------------------
|
||||
IDIV B | 25 MHz | ENET_TX_CLK | ENET_TX_CLK @ 50MHz
|
||||
-----------------------------------------------------------------------------
|
||||
IDIV C | 12 MHz | IRC | Internal oscillator @ 12 MHz
|
||||
-----------------------------------------------------------------------------
|
||||
IDIV D | 12 MHz | IRC | Internal oscillator @ 12 MHz
|
||||
-----------------------------------------------------------------------------
|
||||
IDIV E | 5.3 MHz | PLL1 | To the LCD controller
|
||||
-----------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock source selection definitions (do not change)
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define CLK_SRC_32KHZ 0x00
|
||||
#define CLK_SRC_IRC 0x01
|
||||
#define CLK_SRC_ENET_RX 0x02
|
||||
#define CLK_SRC_ENET_TX 0x03
|
||||
#define CLK_SRC_GP_CLKIN 0x04
|
||||
#define CLK_SRC_XTAL 0x06
|
||||
#define CLK_SRC_PLL0U 0x07
|
||||
#define CLK_SRC_PLL0A 0x08
|
||||
#define CLK_SRC_PLL1 0x09
|
||||
#define CLK_SRC_IDIVA 0x0C
|
||||
#define CLK_SRC_IDIVB 0x0D
|
||||
#define CLK_SRC_IDIVC 0x0E
|
||||
#define CLK_SRC_IDIVD 0x0F
|
||||
#define CLK_SRC_IDIVE 0x10
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define external input frequency values
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define CLK_32KHZ 32768UL /* 32 kHz oscillator frequency */
|
||||
#define CLK_IRC 12000000UL /* Internal oscillator frequency */
|
||||
#define CLK_ENET_RX 50000000UL /* Ethernet Rx frequency */
|
||||
#define CLK_ENET_TX 50000000UL /* Ethernet Tx frequency */
|
||||
#define CLK_GP_CLKIN 12000000UL /* General purpose clock input freq. */
|
||||
#define CLK_XTAL 12000000UL /* Crystal oscilator frequency */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clock sources
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define PLL1_CLK_SEL CLK_SRC_XTAL /* PLL1 input clock: XTAL */
|
||||
#define PLL0USB_CLK_SEL CLK_SRC_XTAL /* PLL0USB input clock: XTAL */
|
||||
#define IDIVA_CLK_SEL CLK_SRC_PLL1 /* IDIVA input clock: PLL1 */
|
||||
#define IDIVB_CLK_SEL CLK_SRC_ENET_TX /* IDIVB input clock: ENET TX */
|
||||
#define IDIVC_CLK_SEL CLK_SRC_IRC /* IDIVC input clock: IRC */
|
||||
#define IDIVD_CLK_SEL CLK_SRC_IRC /* IDIVD input clock: IRC */
|
||||
#define IDIVE_CLK_SEL CLK_SRC_PLL1 /* IDIVD input clock: PLL1 */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Configure integer divider values
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define IDIVA_IDIV 2 /* Divide input clock by 3 */
|
||||
#define IDIVB_IDIV 1 /* Divide input clock by 2 */
|
||||
#define IDIVC_IDIV 0 /* Divide input clock by 1 */
|
||||
#define IDIVD_IDIV 0 /* Divide input clock by 1 */
|
||||
#define IDIVE_IDIV 33 /* Divide input clock by 34 */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define CPU clock input
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define CPU_CLK_SEL CLK_SRC_PLL1 /* Default CPU clock source is PLL1 */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Configure external memory controller options
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define USE_EXT_STAT_MEM_CS0 1 /* Use ext. static memory with CS0 */
|
||||
#define USE_EXT_DYN_MEM_CS0 1 /* Use ext. dynamic memory with CS0 */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Configure PLL1
|
||||
*----------------------------------------------------------------------------
|
||||
* Integer mode:
|
||||
* - PLL1_DIRECT = 0 (Post divider enabled)
|
||||
* - PLL1_FBSEL = 1 (Feedback divider runs from PLL output)
|
||||
* - Output frequency:
|
||||
* FCLKOUT = (FCLKIN / N) * M
|
||||
* FCCO = FCLKOUT * 2 * P
|
||||
*
|
||||
* Non-integer:
|
||||
* - PLL1_DIRECT = 0 (Post divider enabled)
|
||||
* - PLL1_FBSEL = 0 (Feedback divider runs from CCO clock)
|
||||
* - Output frequency:
|
||||
* FCLKOUT = (FCLKIN / N) * M / (2 * P)
|
||||
* FCCO = FCLKOUT * 2 * P
|
||||
*
|
||||
* Direct mode:
|
||||
* - PLL1_DIRECT = 1 (Post divider disabled)
|
||||
* - PLL1_FBSEL = dont care (Feedback divider runs from CCO clock)
|
||||
* - Output frequency:
|
||||
* FCLKOUT = (FCLKIN / N) * M
|
||||
* FCCO = FCLKOUT
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
* PLL1 requirements:
|
||||
* | Frequency | Minimum | Maximum | Note |
|
||||
* | FCLKIN | 1MHz | 25MHz | Clock source is external crystal |
|
||||
* | FCLKIN | 1MHz | 50MHz | |
|
||||
* | FCCO | 156MHz | 320MHz | |
|
||||
* | FCLKOUT | 9.75MHz | 320MHz | |
|
||||
*----------------------------------------------------------------------------
|
||||
* Configuration examples:
|
||||
* | Fclkout | Fcco | N | M | P | DIRECT | FBSEL | BYPASS |
|
||||
* | 36MHz | 288MHz | 1 | 24 | 4 | 0 | 0 | 0 |
|
||||
* | 72MHz | 288MHz | 1 | 24 | 2 | 0 | 0 | 0 |
|
||||
* | 100MHz | 200MHz | 3 | 50 | 1 | 0 | 0 | 0 |
|
||||
* | 120MHz | 240MHz | 1 | 20 | 1 | 0 | 0 | 0 |
|
||||
* | 160MHz | 160MHz | 3 | 40 | x | 1 | 0 | 0 |
|
||||
* | 180MHz | 180MHz | 1 | 15 | x | 1 | 0 | 0 |
|
||||
* | 204MHz | 204MHz | 1 | 17 | x | 1 | 0 | 0 |
|
||||
*----------------------------------------------------------------------------
|
||||
* Relations beetwen PLL dividers and definitions:
|
||||
* N = PLL1_NSEL + 1, M = PLL1_MSEL + 1, P = 2 ^ PLL1_PSEL
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/* PLL1 output clock: 180MHz, Fcco: 180MHz, N = 1, M = 15, P = x */
|
||||
#define PLL1_NSEL 0 /* Range [0 - 3]: Pre-divider ratio N */
|
||||
#define PLL1_MSEL 14 /* Range [0 - 255]: Feedback-divider ratio M */
|
||||
#define PLL1_PSEL 0 /* Range [0 - 3]: Post-divider ratio P */
|
||||
|
||||
#define PLL1_BYPASS 0 /* 0: Use PLL, 1: PLL is bypassed */
|
||||
#define PLL1_DIRECT 1 /* 0: Use PSEL, 1: Don't use PSEL */
|
||||
#define PLL1_FBSEL 0 /* 0: FCCO is used as PLL feedback */
|
||||
/* 1: FCLKOUT is used as PLL feedback */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Configure PLL0USB
|
||||
*----------------------------------------------------------------------------
|
||||
*
|
||||
* Normal operating mode without post-divider and without pre-divider
|
||||
* - PLL0USB_DIRECTI = 1
|
||||
* - PLL0USB_DIRECTO = 1
|
||||
* - PLL0USB_BYPASS = 0
|
||||
* - Output frequency:
|
||||
* FOUT = FIN * 2 * M
|
||||
* FCCO = FOUT
|
||||
*
|
||||
* Normal operating mode with post-divider and without pre-divider
|
||||
* - PLL0USB_DIRECTI = 1
|
||||
* - PLL0USB_DIRECTO = 0
|
||||
* - PLL0USB_BYPASS = 0
|
||||
* - Output frequency:
|
||||
* FOUT = FIN * (M / P)
|
||||
* FCCO = FOUT * 2 * P
|
||||
*
|
||||
* Normal operating mode without post-divider and with pre-divider
|
||||
* - PLL0USB_DIRECTI = 0
|
||||
* - PLL0USB_DIRECTO = 1
|
||||
* - PLL0USB_BYPASS = 0
|
||||
* - Output frequency:
|
||||
* FOUT = FIN * 2 * M / N
|
||||
* FCCO = FOUT
|
||||
*
|
||||
* Normal operating mode with post-divider and with pre-divider
|
||||
* - PLL0USB_DIRECTI = 0
|
||||
* - PLL0USB_DIRECTO = 0
|
||||
* - PLL0USB_BYPASS = 0
|
||||
* - Output frequency:
|
||||
* FOUT = FIN * M / (P * N)
|
||||
* FCCO = FOUT * 2 * P
|
||||
*----------------------------------------------------------------------------
|
||||
* PLL0 requirements:
|
||||
* | Frequency | Minimum | Maximum | Note |
|
||||
* | FCLKIN | 14kHz | 25MHz | Clock source is external crystal |
|
||||
* | FCLKIN | 14kHz | 150MHz | |
|
||||
* | FCCO | 275MHz | 550MHz | |
|
||||
* | FCLKOUT | 4.3MHz | 550MHz | |
|
||||
*----------------------------------------------------------------------------
|
||||
* Configuration examples:
|
||||
* | Fclkout | Fcco | N | M | P | DIRECTI | DIRECTO | BYPASS |
|
||||
* | 120MHz | 480MHz | x | 20 | 2 | 1 | 0 | 0 |
|
||||
* | 480MHz | 480MHz | 1 | 20 | 1 | 1 | 1 | 0 |
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/* PLL0USB output clock: 480MHz, Fcco: 480MHz, N = 1, M = 20, P = 1 */
|
||||
#define PLL0USB_N 1 /* Range [1 - 256]: Pre-divider */
|
||||
#define PLL0USB_M 20 /* Range [1 - 2^15]: Feedback-divider */
|
||||
#define PLL0USB_P 1 /* Range [1 - 32]: Post-divider */
|
||||
|
||||
#define PLL0USB_DIRECTI 1 /* 0: Use N_DIV, 1: Don't use N_DIV */
|
||||
#define PLL0USB_DIRECTO 1 /* 0: Use P_DIV, 1: Don't use P_DIV */
|
||||
#define PLL0USB_BYPASS 0 /* 0: Use PLL, 1: PLL is bypassed */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
End of configuration
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/* PLL0 Setting Check */
|
||||
#if (PLL0USB_BYPASS == 0)
|
||||
#if (PLL0USB_CLK_SEL == CLK_SRC_XTAL)
|
||||
#define PLL0USB_CLKIN CLK_XTAL
|
||||
#else
|
||||
#define PLL0USB_CLKIN CLK_IRC
|
||||
#endif
|
||||
|
||||
#if ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 1)) /* Mode 1a */
|
||||
#define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M)
|
||||
#define PLL0USB_FCCO (PLL0USB_FOUT)
|
||||
#elif ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 0)) /* Mode 1b */
|
||||
#define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / PLL0USB_P)
|
||||
#define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
|
||||
#elif ((PLL0USB_DIRECTI == 0) && (PLL0USB_DIRECTO == 1)) /* Mode 1c */
|
||||
#define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M / PLL0USB_N)
|
||||
#define PLL0USB_FCCO (PLL0USB_FOUT)
|
||||
#else /* Mode 1d */
|
||||
#define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / (PLL0USB_P * PLL0USB_N))
|
||||
#define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
|
||||
#endif
|
||||
|
||||
#if (PLL0USB_FCCO < 275000000UL || PLL0USB_FCCO > 550000000UL)
|
||||
#error "PLL0USB Fcco frequency out of range! (275MHz >= Fcco <= 550MHz)"
|
||||
#endif
|
||||
#if (PLL0USB_FOUT < 4300000UL || PLL0USB_FOUT > 550000000UL)
|
||||
#error "PLL0USB output frequency out of range! (4.3MHz >= Fclkout <= 550MHz)"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* PLL1 Setting Check */
|
||||
#if (PLL1_BYPASS == 0)
|
||||
#if (PLL1_CLK_SEL == CLK_SRC_XTAL)
|
||||
#define PLL1_CLKIN CLK_XTAL
|
||||
#else
|
||||
#define PLL1_CLKIN CLK_IRC
|
||||
#endif
|
||||
|
||||
#if (PLL1_DIRECT == 1) /* Direct Mode */
|
||||
#define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
|
||||
#define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
|
||||
#elif (PLL1_FBSEL == 1) /* Integer Mode */
|
||||
#define PLL1_FCCO ((2 * (1 << PLL1_PSEL)) * (PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
|
||||
#define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
|
||||
#else /* Noninteger Mode */
|
||||
#define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
|
||||
#define PLL1_FOUT (PLL1_FCCO / (2 * (1 << PLL1_PSEL)))
|
||||
#endif
|
||||
#if (PLL1_FCCO < 156000000UL || PLL1_FCCO > 320000000UL)
|
||||
#error "PLL1 Fcco frequency out of range! (156MHz >= Fcco <= 320MHz)"
|
||||
#endif
|
||||
#if (PLL1_FOUT < 9750000UL || PLL1_FOUT > 204000000UL)
|
||||
#error "PLL1 output frequency out of range! (9.75MHz >= Fclkout <= 204MHz)"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Core Clock variable
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = CLK_IRC; /* System Clock Frequency (Core Clock) */
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* SetClock
|
||||
******************************************************************************/
|
||||
void SetClock (void) {
|
||||
uint32_t x, i;
|
||||
uint32_t selp, seli;
|
||||
|
||||
/* Set flash wait states to maximum */
|
||||
LPC_EMC->STATICWAITRD0 = 0x1F;
|
||||
|
||||
/* Switch BASE_M4_CLOCK to IRC */
|
||||
LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */
|
||||
(CLK_SRC_IRC << 24) ; /* Set clock source */
|
||||
|
||||
/* Configure input to crystal oscilator */
|
||||
LPC_CGU->XTAL_OSC_CTRL = (0 << 0) | /* Enable oscillator-pad */
|
||||
(0 << 1) | /* Operation with crystal connected */
|
||||
(0 << 2) ; /* Low-frequency mode */
|
||||
|
||||
/* Wait ~250us @ 12MHz */
|
||||
for (i = 1500; i; i--);
|
||||
|
||||
#if (USE_SPIFI)
|
||||
/* configure SPIFI clk to IRC via IDIVA (later IDIVA is configured to PLL1/3) */
|
||||
LPC_CGU->IDIVA_CTRL = (0 << 0) | /* Disable Power-down */
|
||||
(0 << 2) | /* IDIV */
|
||||
(1 << 11) | /* Autoblock En */
|
||||
(CLK_SRC_IRC << 24) ; /* Clock source */
|
||||
|
||||
LPC_CGU->BASE_SPIFI_CLK = (0 << 0) | /* Disable Power-down */
|
||||
(0 << 2) | /* IDIV */
|
||||
(1 << 11) | /* Autoblock En */
|
||||
(CLK_SRC_IDIVA << 24) ; /* Clock source */
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
PLL1 Setup
|
||||
*----------------------------------------------------------------------------*/
|
||||
/* Power down PLL */
|
||||
LPC_CGU->PLL1_CTRL |= 1;
|
||||
|
||||
#if ((PLL1_FOUT > 110000000UL) && (CPU_CLK_SEL == CLK_SRC_PLL1))
|
||||
/* To run at full speed, CPU must first run at an intermediate speed */
|
||||
LPC_CGU->PLL1_CTRL = (0 << 0) | /* PLL1 Enabled */
|
||||
(PLL1_BYPASS << 1) | /* CCO out sent to post-dividers */
|
||||
(PLL1_FBSEL << 6) | /* PLL output used as feedback */
|
||||
(0 << 7) | /* Direct on/off */
|
||||
(PLL1_PSEL << 8) | /* PSEL */
|
||||
(0 << 11)| /* Autoblock Disabled */
|
||||
(PLL1_NSEL << 12)| /* NSEL */
|
||||
(PLL1_MSEL << 16)| /* MSEL */
|
||||
(PLL1_CLK_SEL << 24); /* Clock source */
|
||||
/* Wait for lock */
|
||||
while (!(LPC_CGU->PLL1_STAT & 1));
|
||||
|
||||
/* CPU base clock is in the mid frequency range before final clock set */
|
||||
LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */
|
||||
(0x09 << 24) ; /* Clock source: PLL1 */
|
||||
|
||||
/* Max. BASE_M4_CLK frequency here is 102MHz, wait at least 20us */
|
||||
for (i = 1050; i; i--); /* Wait minimum 2100 cycles */
|
||||
#endif
|
||||
/* Configure PLL1 */
|
||||
LPC_CGU->PLL1_CTRL = (0 << 0) | /* PLL1 Enabled */
|
||||
(PLL1_BYPASS << 1) | /* CCO out sent to post-dividers */
|
||||
(PLL1_FBSEL << 6) | /* PLL output used as feedback */
|
||||
(PLL1_DIRECT << 7) | /* Direct on/off */
|
||||
(PLL1_PSEL << 8) | /* PSEL */
|
||||
(1 << 11)| /* Autoblock En */
|
||||
(PLL1_NSEL << 12)| /* NSEL */
|
||||
(PLL1_MSEL << 16)| /* MSEL */
|
||||
(PLL1_CLK_SEL << 24); /* Clock source */
|
||||
|
||||
/* Wait for lock */
|
||||
while (!(LPC_CGU->PLL1_STAT & 1));
|
||||
|
||||
/* Set CPU base clock source */
|
||||
LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */
|
||||
(CPU_CLK_SEL << 24) ; /* Set clock source */
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
PLL0USB Setup
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/* Power down PLL0USB */
|
||||
LPC_CGU->PLL0USB_CTRL |= 1;
|
||||
|
||||
/* M divider */
|
||||
x = 0x00004000;
|
||||
switch (PLL0USB_M) {
|
||||
case 0: x = 0xFFFFFFFF;
|
||||
break;
|
||||
case 1: x = 0x00018003;
|
||||
break;
|
||||
case 2: x = 0x00010003;
|
||||
break;
|
||||
default:
|
||||
for (i = PLL0USB_M; i <= 0x8000; i++) {
|
||||
x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF);
|
||||
}
|
||||
}
|
||||
|
||||
if (PLL0USB_M < 60) selp = (PLL0USB_M >> 1) + 1;
|
||||
else selp = 31;
|
||||
|
||||
if (PLL0USB_M > 16384) seli = 1;
|
||||
else if (PLL0USB_M > 8192) seli = 2;
|
||||
else if (PLL0USB_M > 2048) seli = 4;
|
||||
else if (PLL0USB_M >= 501) seli = 8;
|
||||
else if (PLL0USB_M >= 60) seli = 4 * (1024 / (PLL0USB_M + 9));
|
||||
else seli = (PLL0USB_M & 0x3C) + 4;
|
||||
LPC_CGU->PLL0USB_MDIV = (selp << 17) |
|
||||
(seli << 22) |
|
||||
(x << 0);
|
||||
|
||||
/* N divider */
|
||||
x = 0x80;
|
||||
switch (PLL0USB_N) {
|
||||
case 0: x = 0xFFFFFFFF;
|
||||
break;
|
||||
case 1: x = 0x00000302;
|
||||
break;
|
||||
case 2: x = 0x00000202;
|
||||
break;
|
||||
default:
|
||||
for (i = PLL0USB_N; i <= 0x0100; i++) {
|
||||
x =(((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
|
||||
}
|
||||
}
|
||||
LPC_CGU->PLL0USB_NP_DIV = (x << 12);
|
||||
|
||||
/* P divider */
|
||||
x = 0x10;
|
||||
switch (PLL0USB_P) {
|
||||
case 0: x = 0xFFFFFFFF;
|
||||
break;
|
||||
case 1: x = 0x00000062;
|
||||
break;
|
||||
case 2: x = 0x00000042;
|
||||
break;
|
||||
default:
|
||||
for (i = PLL0USB_P; i <= 0x200; i++) {
|
||||
x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) &0x0F);
|
||||
}
|
||||
}
|
||||
LPC_CGU->PLL0USB_NP_DIV |= x;
|
||||
|
||||
LPC_CGU->PLL0USB_CTRL = (PLL0USB_CLK_SEL << 24) | /* Clock source sel */
|
||||
(1 << 11) | /* Autoblock En */
|
||||
(1 << 4 ) | /* PLL0USB clock en */
|
||||
(PLL0USB_DIRECTO << 3 ) | /* Direct output */
|
||||
(PLL0USB_DIRECTI << 2 ) | /* Direct input */
|
||||
(PLL0USB_BYPASS << 1 ) | /* PLL bypass */
|
||||
(0 << 0 ) ; /* PLL0USB Enabled */
|
||||
while (!(LPC_CGU->PLL0USB_STAT & 1));
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Integer divider Setup
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/* Configure integer dividers */
|
||||
LPC_CGU->IDIVA_CTRL = (0 << 0) | /* Disable Power-down */
|
||||
(IDIVA_IDIV << 2) | /* IDIV */
|
||||
(1 << 11) | /* Autoblock En */
|
||||
(IDIVA_CLK_SEL << 24) ; /* Clock source */
|
||||
|
||||
LPC_CGU->IDIVB_CTRL = (0 << 0) | /* Disable Power-down */
|
||||
(IDIVB_IDIV << 2) | /* IDIV */
|
||||
(1 << 11) | /* Autoblock En */
|
||||
(IDIVB_CLK_SEL << 24) ; /* Clock source */
|
||||
|
||||
LPC_CGU->IDIVC_CTRL = (0 << 0) | /* Disable Power-down */
|
||||
(IDIVC_IDIV << 2) | /* IDIV */
|
||||
(1 << 11) | /* Autoblock En */
|
||||
(IDIVC_CLK_SEL << 24) ; /* Clock source */
|
||||
|
||||
LPC_CGU->IDIVD_CTRL = (0 << 0) | /* Disable Power-down */
|
||||
(IDIVD_IDIV << 2) | /* IDIV */
|
||||
(1 << 11) | /* Autoblock En */
|
||||
(IDIVD_CLK_SEL << 24) ; /* Clock source */
|
||||
|
||||
LPC_CGU->IDIVE_CTRL = (0 << 0) | /* Disable Power-down */
|
||||
(IDIVE_IDIV << 2) | /* IDIV */
|
||||
(1 << 11) | /* Autoblock En */
|
||||
(IDIVE_CLK_SEL << 24) ; /* Clock source */
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Approximate delay function (must be used after SystemCoreClockUpdate() call)
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define CPU_NANOSEC(x) (((uint64_t)(x) * SystemCoreClock)/1000000000)
|
||||
|
||||
static void WaitUs (uint32_t us) {
|
||||
uint32_t cyc = us * CPU_NANOSEC(1000)/4;
|
||||
while(cyc--);
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
External Memory Controller Definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define SDRAM_ADDR_BASE 0x28000000 /* SDRAM base address */
|
||||
/* Write Mode register macro */
|
||||
#define WR_MODE(x) (*((volatile uint32_t *)(SDRAM_ADDR_BASE | (x))))
|
||||
|
||||
/* Pin Settings: Glith filter DIS, Input buffer EN, Fast Slew Rate, No Pullup */
|
||||
#define EMC_PIN_SET ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4))
|
||||
#define EMC_NANOSEC(ns, freq, div) (((uint64_t)(ns) * ((freq)/((div)+1)))/1000000000)
|
||||
|
||||
#define EMC_CLK_DLY_TIM_2 (0x7777) /* 3.5 ns delay for the EMC clock out */
|
||||
#define EMC_CLK_DLY_TIM_0 (0x0000) /* No delay for the EMC clock out */
|
||||
|
||||
typedef void (*emcdivby2) (volatile uint32_t *creg6, volatile uint32_t *emcdiv, uint32_t cfg);
|
||||
|
||||
const uint16_t emcdivby2_opc[] = {
|
||||
0x6803, /* LDR R3,[R0,#0] ; Load CREG6 */
|
||||
0xF443,0x3380, /* ORR R3,R3,#0x10000 ; Set Divided by 2 */
|
||||
0x6003, /* STR R3,[R0,#0] ; Store CREG6 */
|
||||
0x600A, /* STR R2,[R1,#0] ; EMCDIV_CFG = cfg */
|
||||
0x684B, /* loop LDR R3,[R1,#4] ; Load EMCDIV_STAT */
|
||||
0x07DB, /* LSLS R3,R3,#31 ; Check EMCDIV_STAT.0 */
|
||||
0xD0FC, /* BEQ loop ; Jump if 0 */
|
||||
0x4770, /* BX LR ; Exit */
|
||||
0,
|
||||
};
|
||||
|
||||
#define emcdivby2_szw ((sizeof(emcdivby2_opc)+3)/4)
|
||||
#define emcdivby2_ram 0x10000000
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Initialize external memory controller
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
void SystemInit_ExtMemCtl (void) {
|
||||
uint32_t emcdivby2_buf[emcdivby2_szw];
|
||||
uint32_t div, n;
|
||||
|
||||
/* Select and enable EMC branch clock */
|
||||
LPC_CCU1->CLK_M4_EMC_CFG = (1 << 2) | (1 << 1) | 1;
|
||||
while (!(LPC_CCU1->CLK_M4_EMC_STAT & 1));
|
||||
|
||||
/* Set EMC clock output delay */
|
||||
if (SystemCoreClock < 80000000UL) {
|
||||
LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_0; /* No EMC clock out delay */
|
||||
}
|
||||
else {
|
||||
LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_2; /* 2.0 ns EMC clock out delay */
|
||||
}
|
||||
|
||||
/* Configure EMC port pins */
|
||||
LPC_SCU->SFSP1_0 = EMC_PIN_SET | 2; /* P1_0: A5 */
|
||||
LPC_SCU->SFSP1_1 = EMC_PIN_SET | 2; /* P1_1: A6 */
|
||||
LPC_SCU->SFSP1_2 = EMC_PIN_SET | 2; /* P1_2: A7 */
|
||||
LPC_SCU->SFSP1_3 = EMC_PIN_SET | 3; /* P1_3: OE */
|
||||
LPC_SCU->SFSP1_4 = EMC_PIN_SET | 3; /* P1_4: BLS0 */
|
||||
LPC_SCU->SFSP1_5 = EMC_PIN_SET | 3; /* P1_5: CS0 */
|
||||
LPC_SCU->SFSP1_6 = EMC_PIN_SET | 3; /* P1_6: WE */
|
||||
LPC_SCU->SFSP1_7 = EMC_PIN_SET | 3; /* P1_7: D0 */
|
||||
LPC_SCU->SFSP1_8 = EMC_PIN_SET | 3; /* P1_8: D1 */
|
||||
LPC_SCU->SFSP1_9 = EMC_PIN_SET | 3; /* P1_9: D2 */
|
||||
LPC_SCU->SFSP1_10 = EMC_PIN_SET | 3; /* P1_10: D3 */
|
||||
LPC_SCU->SFSP1_11 = EMC_PIN_SET | 3; /* P1_11: D4 */
|
||||
LPC_SCU->SFSP1_12 = EMC_PIN_SET | 3; /* P1_12: D5 */
|
||||
LPC_SCU->SFSP1_13 = EMC_PIN_SET | 3; /* P1_13: D6 */
|
||||
LPC_SCU->SFSP1_14 = EMC_PIN_SET | 3; /* P1_14: D7 */
|
||||
|
||||
LPC_SCU->SFSP2_0 = EMC_PIN_SET | 2; /* P2_0: A13 */
|
||||
LPC_SCU->SFSP2_1 = EMC_PIN_SET | 2; /* P2_1: A12 */
|
||||
LPC_SCU->SFSP2_2 = EMC_PIN_SET | 2; /* P2_2: A11 */
|
||||
LPC_SCU->SFSP2_6 = EMC_PIN_SET | 2; /* P2_6: A10 */
|
||||
LPC_SCU->SFSP2_7 = EMC_PIN_SET | 3; /* P2_7: A9 */
|
||||
LPC_SCU->SFSP2_8 = EMC_PIN_SET | 3; /* P2_8: A8 */
|
||||
LPC_SCU->SFSP2_9 = EMC_PIN_SET | 3; /* P2_9: A0 */
|
||||
LPC_SCU->SFSP2_10 = EMC_PIN_SET | 3; /* P2_10: A1 */
|
||||
LPC_SCU->SFSP2_11 = EMC_PIN_SET | 3; /* P2_11: A2 */
|
||||
LPC_SCU->SFSP2_12 = EMC_PIN_SET | 3; /* P2_12: A3 */
|
||||
LPC_SCU->SFSP2_13 = EMC_PIN_SET | 3; /* P2_13: A4 */
|
||||
|
||||
LPC_SCU->SFSP5_0 = EMC_PIN_SET | 2; /* P5_0: D12 */
|
||||
LPC_SCU->SFSP5_1 = EMC_PIN_SET | 2; /* P5_1: D13 */
|
||||
LPC_SCU->SFSP5_2 = EMC_PIN_SET | 2; /* P5_2: D14 */
|
||||
LPC_SCU->SFSP5_3 = EMC_PIN_SET | 2; /* P5_3: D15 */
|
||||
LPC_SCU->SFSP5_4 = EMC_PIN_SET | 2; /* P5_4: D8 */
|
||||
LPC_SCU->SFSP5_5 = EMC_PIN_SET | 2; /* P5_5: D9 */
|
||||
LPC_SCU->SFSP5_6 = EMC_PIN_SET | 2; /* P5_6: D10 */
|
||||
LPC_SCU->SFSP5_7 = EMC_PIN_SET | 2; /* P5_7: D11 */
|
||||
|
||||
LPC_SCU->SFSP6_1 = EMC_PIN_SET | 1; /* P6_1: DYCS1 */
|
||||
LPC_SCU->SFSP6_2 = EMC_PIN_SET | 1; /* P6_3: CKEOUT1 */
|
||||
LPC_SCU->SFSP6_3 = EMC_PIN_SET | 3; /* P6_3: CS1 */
|
||||
LPC_SCU->SFSP6_4 = EMC_PIN_SET | 3; /* P6_4: CAS */
|
||||
LPC_SCU->SFSP6_5 = EMC_PIN_SET | 3; /* P6_5: RAS */
|
||||
LPC_SCU->SFSP6_6 = EMC_PIN_SET | 1; /* P6_6: BLS1 */
|
||||
LPC_SCU->SFSP6_7 = EMC_PIN_SET | 1; /* P6_7: A15 */
|
||||
LPC_SCU->SFSP6_8 = EMC_PIN_SET | 1; /* P6_8: A14 */
|
||||
LPC_SCU->SFSP6_9 = EMC_PIN_SET | 3; /* P6_9: DYCS0 */
|
||||
LPC_SCU->SFSP6_10 = EMC_PIN_SET | 3; /* P6_10: DQMOUT1 */
|
||||
LPC_SCU->SFSP6_11 = EMC_PIN_SET | 3; /* P6_11: CKEOUT0 */
|
||||
LPC_SCU->SFSP6_12 = EMC_PIN_SET | 3; /* P6_12: DQMOUT0 */
|
||||
|
||||
LPC_SCU->SFSPA_4 = EMC_PIN_SET | 3; /* PA_4: A23 */
|
||||
|
||||
LPC_SCU->SFSPD_0 = EMC_PIN_SET | 2; /* PD_0: DQMOUT2 */
|
||||
LPC_SCU->SFSPD_1 = EMC_PIN_SET | 2; /* PD_1: CKEOUT2 */
|
||||
LPC_SCU->SFSPD_2 = EMC_PIN_SET | 2; /* PD_2: D16 */
|
||||
LPC_SCU->SFSPD_3 = EMC_PIN_SET | 2; /* PD_3: D17 */
|
||||
LPC_SCU->SFSPD_4 = EMC_PIN_SET | 2; /* PD_4: D18 */
|
||||
LPC_SCU->SFSPD_5 = EMC_PIN_SET | 2; /* PD_5: D19 */
|
||||
LPC_SCU->SFSPD_6 = EMC_PIN_SET | 2; /* PD_6: D20 */
|
||||
LPC_SCU->SFSPD_7 = EMC_PIN_SET | 2; /* PD_7: D21 */
|
||||
LPC_SCU->SFSPD_8 = EMC_PIN_SET | 2; /* PD_8: D22 */
|
||||
LPC_SCU->SFSPD_9 = EMC_PIN_SET | 2; /* PD_9: D23 */
|
||||
LPC_SCU->SFSPD_10 = EMC_PIN_SET | 2; /* PD_10: BLS3 */
|
||||
LPC_SCU->SFSPD_11 = EMC_PIN_SET | 2; /* PD_11: CS3 */
|
||||
LPC_SCU->SFSPD_12 = EMC_PIN_SET | 2; /* PD_12: CS2 */
|
||||
LPC_SCU->SFSPD_13 = EMC_PIN_SET | 2; /* PD_13: BLS2 */
|
||||
LPC_SCU->SFSPD_14 = EMC_PIN_SET | 2; /* PD_14: DYCS2 */
|
||||
LPC_SCU->SFSPD_15 = EMC_PIN_SET | 2; /* PD_15: A17 */
|
||||
LPC_SCU->SFSPD_16 = EMC_PIN_SET | 2; /* PD_16: A16 */
|
||||
|
||||
LPC_SCU->SFSPE_0 = EMC_PIN_SET | 3; /* PE_0: A18 */
|
||||
LPC_SCU->SFSPE_1 = EMC_PIN_SET | 3; /* PE_1: A19 */
|
||||
LPC_SCU->SFSPE_2 = EMC_PIN_SET | 3; /* PE_2: A20 */
|
||||
LPC_SCU->SFSPE_3 = EMC_PIN_SET | 3; /* PE_3: A21 */
|
||||
LPC_SCU->SFSPE_4 = EMC_PIN_SET | 3; /* PE_4: A22 */
|
||||
LPC_SCU->SFSPE_5 = EMC_PIN_SET | 3; /* PE_5: D24 */
|
||||
LPC_SCU->SFSPE_6 = EMC_PIN_SET | 3; /* PE_6: D25 */
|
||||
LPC_SCU->SFSPE_7 = EMC_PIN_SET | 3; /* PE_7: D26 */
|
||||
LPC_SCU->SFSPE_8 = EMC_PIN_SET | 3; /* PE_8: D27 */
|
||||
LPC_SCU->SFSPE_9 = EMC_PIN_SET | 3; /* PE_9: D28 */
|
||||
LPC_SCU->SFSPE_10 = EMC_PIN_SET | 3; /* PE_10: D29 */
|
||||
LPC_SCU->SFSPE_11 = EMC_PIN_SET | 3; /* PE_11: D30 */
|
||||
LPC_SCU->SFSPE_12 = EMC_PIN_SET | 3; /* PE_12: D31 */
|
||||
LPC_SCU->SFSPE_13 = EMC_PIN_SET | 3; /* PE_13: DQMOUT3 */
|
||||
LPC_SCU->SFSPE_14 = EMC_PIN_SET | 3; /* PE_14: DYCS3 */
|
||||
LPC_SCU->SFSPE_15 = EMC_PIN_SET | 3; /* PE_15: CKEOUT3 */
|
||||
|
||||
LPC_EMC->CONTROL = 0x00000001; /* EMC Enable */
|
||||
LPC_EMC->CONFIG = 0x00000000; /* Little-endian, Clock Ratio 1:1 */
|
||||
|
||||
div = 0;
|
||||
if (SystemCoreClock > 120000000UL) {
|
||||
/* Use EMC clock divider and EMC clock output delay */
|
||||
div = 1;
|
||||
/* Following code must be executed in RAM to ensure stable operation */
|
||||
/* LPC_CCU1->CLK_M4_EMCDIV_CFG = (1 << 5) | (1 << 2) | (1 << 1) | 1; */
|
||||
/* LPC_CREG->CREG6 |= (1 << 16); // EMC_CLK_DIV divided by 2 */
|
||||
/* while (!(LPC_CCU1->CLK_M4_EMCDIV_STAT & 1)); */
|
||||
|
||||
/* This code configures EMC clock divider and is executed in RAM */
|
||||
for (n = 0; n < emcdivby2_szw; n++) {
|
||||
emcdivby2_buf[n] = *((uint32_t *)emcdivby2_ram + n);
|
||||
*((uint32_t *)emcdivby2_ram + n) = *((uint32_t *)emcdivby2_opc + n);
|
||||
}
|
||||
__ISB();
|
||||
((emcdivby2 )(emcdivby2_ram+1))(&LPC_CREG->CREG6, &LPC_CCU1->CLK_M4_EMCDIV_CFG, (1 << 5) | (1 << 2) | (1 << 1) | 1);
|
||||
for (n = 0; n < emcdivby2_szw; n++) {
|
||||
*((uint32_t *)emcdivby2_ram + n) = emcdivby2_buf[n];
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure EMC clock-out pins */
|
||||
LPC_SCU->SFSCLK_0 = EMC_PIN_SET | 0; /* CLK0 */
|
||||
LPC_SCU->SFSCLK_1 = EMC_PIN_SET | 0; /* CLK1 */
|
||||
LPC_SCU->SFSCLK_2 = EMC_PIN_SET | 0; /* CLK2 */
|
||||
LPC_SCU->SFSCLK_3 = EMC_PIN_SET | 0; /* CLK3 */
|
||||
|
||||
/* Static memory configuration (chip select 0) */
|
||||
#if (USE_EXT_STAT_MEM_CS0)
|
||||
LPC_EMC->STATICCONFIG0 = (1 << 7) | /* Byte lane state: use WE signal */
|
||||
(2 << 0) | /* Memory width 32-bit */
|
||||
(1 << 3); /* Async page mode enable */
|
||||
|
||||
LPC_EMC->STATICWAITOEN0 = (0 << 0) ; /* Wait output enable: No delay */
|
||||
|
||||
LPC_EMC->STATICWAITPAGE0 = 2;
|
||||
|
||||
/* Set Static Memory Read Delay for 90ns External NOR Flash */
|
||||
LPC_EMC->STATICWAITRD0 = 1 + EMC_NANOSEC(90, SystemCoreClock, div);
|
||||
LPC_EMC->STATICCONFIG0 |= (1 << 19) ; /* Enable buffer */
|
||||
#endif
|
||||
|
||||
/* Dynamic memory configuration (chip select 0) */
|
||||
#if (USE_EXT_DYN_MEM_CS0)
|
||||
|
||||
/* Set Address mapping: 128Mb(4Mx32), 4 banks, row len = 12, column len = 8 */
|
||||
LPC_EMC->DYNAMICCONFIG0 = (1 << 14) | /* AM[14] = 1 */
|
||||
(0 << 12) | /* AM[12] = 0 */
|
||||
(2 << 9) | /* AM[11:9] = 2 */
|
||||
(2 << 7) ; /* AM[8:7] = 2 */
|
||||
|
||||
LPC_EMC->DYNAMICRASCAS0 = 0x00000303; /* Latency: RAS 3, CAS 3 CCLK cyc.*/
|
||||
LPC_EMC->DYNAMICREADCONFIG = 0x00000001; /* Command delayed by 1/2 CCLK */
|
||||
|
||||
LPC_EMC->DYNAMICRP = EMC_NANOSEC (20, SystemCoreClock, div);
|
||||
LPC_EMC->DYNAMICRAS = EMC_NANOSEC (42, SystemCoreClock, div);
|
||||
LPC_EMC->DYNAMICSREX = EMC_NANOSEC (63, SystemCoreClock, div);
|
||||
LPC_EMC->DYNAMICAPR = EMC_NANOSEC (70, SystemCoreClock, div);
|
||||
LPC_EMC->DYNAMICDAL = EMC_NANOSEC (70, SystemCoreClock, div);
|
||||
LPC_EMC->DYNAMICWR = EMC_NANOSEC (30, SystemCoreClock, div);
|
||||
LPC_EMC->DYNAMICRC = EMC_NANOSEC (63, SystemCoreClock, div);
|
||||
LPC_EMC->DYNAMICRFC = EMC_NANOSEC (63, SystemCoreClock, div);
|
||||
LPC_EMC->DYNAMICXSR = EMC_NANOSEC (63, SystemCoreClock, div);
|
||||
LPC_EMC->DYNAMICRRD = EMC_NANOSEC (14, SystemCoreClock, div);
|
||||
LPC_EMC->DYNAMICMRD = EMC_NANOSEC (30, SystemCoreClock, div);
|
||||
|
||||
WaitUs (100);
|
||||
LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */
|
||||
WaitUs (10);
|
||||
LPC_EMC->DYNAMICCONTROL = 0x00000103; /* Issue PALL command */
|
||||
WaitUs (1);
|
||||
LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */
|
||||
WaitUs (1);
|
||||
LPC_EMC->DYNAMICREFRESH = EMC_NANOSEC( 200, SystemCoreClock, div) / 16 + 1;
|
||||
WaitUs (10);
|
||||
LPC_EMC->DYNAMICREFRESH = EMC_NANOSEC(15625, SystemCoreClock, div) / 16 + 1;
|
||||
WaitUs (10);
|
||||
LPC_EMC->DYNAMICCONTROL = 0x00000083; /* Issue MODE command */
|
||||
|
||||
/* Mode register: Burst Length: 4, Burst Type: Sequential, CAS Latency: 3 */
|
||||
WR_MODE(((3 << 4) | 2) << 12);
|
||||
|
||||
WaitUs (10);
|
||||
LPC_EMC->DYNAMICCONTROL = 0x00000002; /* Issue NORMAL command */
|
||||
LPC_EMC->DYNAMICCONFIG0 |= (1 << 19); /* Enable buffer */
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Measure frequency using frequency monitor
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t MeasureFreq (uint32_t clk_sel) {
|
||||
uint32_t fcnt, rcnt, fout;
|
||||
|
||||
/* Set register values */
|
||||
LPC_CGU->FREQ_MON &= ~(1 << 23); /* Stop frequency counters */
|
||||
LPC_CGU->FREQ_MON = (clk_sel << 24) | 511; /* RCNT == 511 */
|
||||
LPC_CGU->FREQ_MON |= (1 << 23); /* Start RCNT and FCNT */
|
||||
while (LPC_CGU->FREQ_MON & (1 << 23)) {
|
||||
fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
|
||||
rcnt = (LPC_CGU->FREQ_MON ) & 0x01FF;
|
||||
if (fcnt == 0 && rcnt == 0) {
|
||||
return (0); /* No input clock present */
|
||||
}
|
||||
}
|
||||
fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
|
||||
fout = fcnt * (12000000U/511U); /* FCNT * (IRC_CLK / RCNT) */
|
||||
|
||||
return (fout);
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Get PLL1 (divider and multiplier) parameters
|
||||
*----------------------------------------------------------------------------*/
|
||||
__inline uint32_t GetPLL1Param (void) {
|
||||
uint32_t ctrl;
|
||||
uint32_t p;
|
||||
uint32_t div, mul;
|
||||
|
||||
ctrl = LPC_CGU->PLL1_CTRL;
|
||||
div = ((ctrl >> 12) & 0x03) + 1;
|
||||
mul = ((ctrl >> 16) & 0xFF) + 1;
|
||||
p = 1 << ((ctrl >> 8) & 0x03);
|
||||
|
||||
if (ctrl & (1 << 1)) {
|
||||
/* Bypass = 1, PLL1 input clock sent to post-dividers */
|
||||
if (ctrl & (1 << 7)) {
|
||||
div *= (2*p);
|
||||
}
|
||||
}
|
||||
else {
|
||||
/* Direct and integer mode */
|
||||
if (((ctrl & (1 << 7)) == 0) && ((ctrl & (1 << 6)) == 0)) {
|
||||
/* Non-integer mode */
|
||||
div *= (2*p);
|
||||
}
|
||||
}
|
||||
return ((div << 8) | (mul));
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Get input clock source for specified clock generation block
|
||||
*----------------------------------------------------------------------------*/
|
||||
int32_t GetClkSel (uint32_t clk_src) {
|
||||
uint32_t reg;
|
||||
int32_t clk_sel = -1;
|
||||
|
||||
switch (clk_src) {
|
||||
case CLK_SRC_IRC:
|
||||
case CLK_SRC_ENET_RX:
|
||||
case CLK_SRC_ENET_TX:
|
||||
case CLK_SRC_GP_CLKIN:
|
||||
return (clk_src);
|
||||
|
||||
case CLK_SRC_32KHZ:
|
||||
return ((LPC_CREG->CREG0 & 0x0A) != 0x02) ? (-1) : (CLK_SRC_32KHZ);
|
||||
case CLK_SRC_XTAL:
|
||||
return (LPC_CGU->XTAL_OSC_CTRL & 1) ? (-1) : (CLK_SRC_XTAL);
|
||||
|
||||
case CLK_SRC_PLL0U: reg = LPC_CGU->PLL0USB_CTRL; break;
|
||||
case CLK_SRC_PLL0A: reg = LPC_CGU->PLL0AUDIO_CTRL; break;
|
||||
case CLK_SRC_PLL1: reg = (LPC_CGU->PLL1_STAT & 1) ? (LPC_CGU->PLL1_CTRL) : (0); break;
|
||||
|
||||
case CLK_SRC_IDIVA: reg = LPC_CGU->IDIVA_CTRL; break;
|
||||
case CLK_SRC_IDIVB: reg = LPC_CGU->IDIVB_CTRL; break;
|
||||
case CLK_SRC_IDIVC: reg = LPC_CGU->IDIVC_CTRL; break;
|
||||
case CLK_SRC_IDIVD: reg = LPC_CGU->IDIVD_CTRL; break;
|
||||
case CLK_SRC_IDIVE: reg = LPC_CGU->IDIVE_CTRL; break;
|
||||
|
||||
default:
|
||||
return (clk_sel);
|
||||
}
|
||||
if (!(reg & 1)) {
|
||||
clk_sel = (reg >> 24) & 0x1F;
|
||||
}
|
||||
return (clk_sel);
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Get clock frequency for specified clock source
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t GetClockFreq (uint32_t clk_src) {
|
||||
uint32_t tmp;
|
||||
uint32_t mul = 1;
|
||||
uint32_t div = 1;
|
||||
uint32_t main_freq = 0;
|
||||
int32_t clk_sel = clk_src;
|
||||
|
||||
do {
|
||||
switch (clk_sel) {
|
||||
case CLK_SRC_32KHZ: main_freq = CLK_32KHZ; break;
|
||||
case CLK_SRC_IRC: main_freq = CLK_IRC; break;
|
||||
case CLK_SRC_ENET_RX: main_freq = CLK_ENET_RX; break;
|
||||
case CLK_SRC_ENET_TX: main_freq = CLK_ENET_TX; break;
|
||||
case CLK_SRC_GP_CLKIN: main_freq = CLK_GP_CLKIN; break;
|
||||
case CLK_SRC_XTAL: main_freq = CLK_XTAL; break;
|
||||
|
||||
case CLK_SRC_IDIVA: div *= ((LPC_CGU->IDIVA_CTRL >> 2) & 0x03) + 1; break;
|
||||
case CLK_SRC_IDIVB: div *= ((LPC_CGU->IDIVB_CTRL >> 2) & 0x0F) + 1; break;
|
||||
case CLK_SRC_IDIVC: div *= ((LPC_CGU->IDIVC_CTRL >> 2) & 0x0F) + 1; break;
|
||||
case CLK_SRC_IDIVD: div *= ((LPC_CGU->IDIVD_CTRL >> 2) & 0x0F) + 1; break;
|
||||
case CLK_SRC_IDIVE: div *= ((LPC_CGU->IDIVE_CTRL >> 2) & 0xFF) + 1; break;
|
||||
|
||||
case CLK_SRC_PLL0U: /* Not implemented */ break;
|
||||
case CLK_SRC_PLL0A: /* Not implemented */ break;
|
||||
|
||||
case CLK_SRC_PLL1:
|
||||
tmp = GetPLL1Param ();
|
||||
mul *= (tmp ) & 0xFF; /* PLL input clock multiplier */
|
||||
div *= (tmp >> 8) & 0xFF; /* PLL input clock divider */
|
||||
break;
|
||||
|
||||
default:
|
||||
return (0); /* Clock not running or not supported */
|
||||
}
|
||||
if (main_freq == 0) {
|
||||
clk_sel = GetClkSel (clk_sel);
|
||||
}
|
||||
}
|
||||
while (main_freq == 0);
|
||||
|
||||
return ((main_freq * mul) / div);
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Core Clock update
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void) {
|
||||
/* Check BASE_M4_CLK connection */
|
||||
uint32_t base_src = (LPC_CGU->BASE_M4_CLK >> 24) & 0x1F;
|
||||
|
||||
/* Update core clock frequency */
|
||||
SystemCoreClock = GetClockFreq (base_src);
|
||||
}
|
||||
|
||||
|
||||
extern uint32_t __Vectors; /* see startup_LPC43xx.s */
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Initialize the system
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemInit (void) {
|
||||
|
||||
#if (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
|
||||
(3UL << 11*2) ); /* set CP11 Full Access */
|
||||
#endif
|
||||
|
||||
/* Stop CM0 core */
|
||||
LPC_RGU->RESET_CTRL1 = (1 << 24);
|
||||
|
||||
/* Disable SysTick timer */
|
||||
SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk);
|
||||
|
||||
/* Set vector table pointer */
|
||||
SCB->VTOR = ((uint32_t)(&__Vectors)) & 0xFFF00000UL;
|
||||
|
||||
/* Configure PLL0 and PLL1, connect CPU clock to selected clock source */
|
||||
SetClock();
|
||||
|
||||
/* Update SystemCoreClock variable */
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
/* Configure External Memory Controller */
|
||||
//SystemInit_ExtMemCtl ();
|
||||
}
|
||||
@ -0,0 +1,25 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Component Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'CMSIS_DAP'
|
||||
* Target: 'LPC4320 SPIFI'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
#define RTE_CMSIS_RTOS /* CMSIS-RTOS */
|
||||
#define RTE_CMSIS_RTOS_RTX /* CMSIS-RTOS Keil RTX */
|
||||
#define RTE_DEVICE_STARTUP_LPC43XX /* Device Startup for NXP43XX */
|
||||
#define RTE_Drivers_USART0 /* Driver USART0 */
|
||||
#define RTE_Drivers_USART1 /* Driver USART1 */
|
||||
#define RTE_Drivers_USART2 /* Driver USART2 */
|
||||
#define RTE_Drivers_USART3 /* Driver USART3 */
|
||||
#define RTE_Drivers_USBD0 /* Driver USBD0 */
|
||||
#define RTE_USB_Core /* USB Core */
|
||||
#define RTE_USB_Device_0 /* USB Device 0 */
|
||||
#define RTE_USB_Device_HID_0 /* USB Device HID instance 0 */
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@ -0,0 +1,171 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
* MDK Middleware - Component ::USB:Device
|
||||
* Copyright (c) 2004-2014 ARM Germany GmbH. All rights reserved.
|
||||
*------------------------------------------------------------------------------
|
||||
* Name: USBD_Config_0.c
|
||||
* Purpose: USB Device Configuration
|
||||
* Rev.: V5.00
|
||||
*------------------------------------------------------------------------------
|
||||
* Use the following configuration settings in the Device Class configuration
|
||||
* files to assign a Device Class to this USB Device 0.
|
||||
*
|
||||
* Configuration Setting Value
|
||||
* --------------------- -----
|
||||
* Assign Device Class to USB Device # = 0
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <h>USB Device 0
|
||||
// <o>Connect to hardware via Driver_USBD# <0-255>
|
||||
// <i>Select driver control block for hardware interface.
|
||||
#define USBD0_PORT 0
|
||||
|
||||
// <o.0>High-speed
|
||||
// <i>Enable High-speed functionality (if device supports it).
|
||||
#define USBD0_HS 1
|
||||
|
||||
// <h>Device Settings
|
||||
// <i>These settings are used to create the Device Descriptor
|
||||
// <o>Max Endpoint 0 Packet Size
|
||||
// <i>Maximum packet size for Endpoint 0 (bMaxPacketSize0).
|
||||
// <8=>8 Bytes <16=>16 Bytes <32=>32 Bytes <64=>64 Bytes
|
||||
#define USBD0_MAX_PACKET0 64
|
||||
|
||||
// <o.0..15>Vendor ID <0x0000-0xFFFF>
|
||||
// <i>Vendor ID assigned by USB-IF (idVendor).
|
||||
#define USBD0_DEV_DESC_IDVENDOR 0xC251
|
||||
|
||||
// <o.0..15>Product ID <0x0000-0xFFFF>
|
||||
// <i>Product ID assigned by manufacturer (idProduct).
|
||||
#define USBD0_DEV_DESC_IDPRODUCT 0xF001
|
||||
|
||||
// <o.0..15>Device Release Number <0x0000-0xFFFF>
|
||||
// <i>Device Release Number in binary-coded decimal (bcdDevice)
|
||||
#define USBD0_DEV_DESC_BCDDEVICE 0x0100
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Configuration Settings
|
||||
// <i>These settings are used to create the Configuration Descriptor.
|
||||
// <o.6>Power
|
||||
// <i>Default Power Setting (D6: of bmAttributes).
|
||||
// <0=>Bus-powered
|
||||
// <1=>Self-powered
|
||||
// <o.5>Remote Wakeup
|
||||
// <i>Configuration support for Remote Wakeup (D5: of bmAttributes).
|
||||
#define USBD0_CFG_DESC_BMATTRIBUTES 0x80
|
||||
|
||||
// <o.0..7>Maximum Power Consumption (in mA) <0-510><#/2>
|
||||
// <i>Maximum Power Consumption of USB Device from bus in this
|
||||
// <i>specific configuration when device is fully operational (bMaxPower).
|
||||
#define USBD0_CFG_DESC_BMAXPOWER 250
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>String Settings
|
||||
// <i>These settings are used to create the String Descriptor.
|
||||
// <o.0..15>Language ID <0x0000-0xFCFF>
|
||||
// <i>English (United States) = 0x0409.
|
||||
#define USBD0_STR_DESC_LANGID 0x0409
|
||||
|
||||
// <s.126>Manufacturer String
|
||||
// <i>String Descriptor describing Manufacturer.
|
||||
#define USBD0_STR_DESC_MAN L"KEIL - Tools By ARM"
|
||||
|
||||
// <s.126>Product String
|
||||
// <i>String Descriptor describing Product.
|
||||
#define USBD0_STR_DESC_PROD L"LPC-Link-II CMSIS-DAP"
|
||||
|
||||
// <e.0>Serial Number
|
||||
// <i>Enable Serial Number String.
|
||||
// <i>If disabled Serial Number String will not be assigned to USB Device.
|
||||
#define USBD0_STR_DESC_SER_EN 1
|
||||
|
||||
// <s.126>Serial Number String
|
||||
// <i>String Descriptor describing device's Serial Number.
|
||||
#define USBD0_STR_DESC_SER L"0001A0000000"
|
||||
|
||||
// </e>
|
||||
// </h>
|
||||
|
||||
// <h>OS Resources Settings
|
||||
// <i>These settings are used to optimize usage of OS resources.
|
||||
// <o>Core Thread Stack Size <64-65536>
|
||||
#define USBD0_CORE_THREAD_STACK_SIZE 512
|
||||
|
||||
// Core Thread Priority
|
||||
#define USBD0_CORE_THREAD_PRIORITY osPriorityAboveNormal
|
||||
|
||||
// </h>
|
||||
// </h>
|
||||
|
||||
|
||||
#include "..\RTE_Components.h"
|
||||
|
||||
#ifdef RTE_USB_Device_CustomClass_0
|
||||
#include "USBD_Config_CustomClass_0.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CustomClass_1
|
||||
#include "USBD_Config_CustomClass_1.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CustomClass_2
|
||||
#include "USBD_Config_CustomClass_2.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CustomClass_3
|
||||
#include "USBD_Config_CustomClass_3.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_USB_Device_HID_0
|
||||
#include "USBD_Config_HID_0.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_HID_1
|
||||
#include "USBD_Config_HID_1.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_HID_2
|
||||
#include "USBD_Config_HID_2.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_HID_3
|
||||
#include "USBD_Config_HID_3.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_USB_Device_MSC_0
|
||||
#include "USBD_Config_MSC_0.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_MSC_1
|
||||
#include "USBD_Config_MSC_1.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_MSC_2
|
||||
#include "USBD_Config_MSC_2.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_MSC_3
|
||||
#include "USBD_Config_MSC_3.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_USB_Device_CDC_0
|
||||
#include "USBD_Config_CDC_0.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CDC_1
|
||||
#include "USBD_Config_CDC_1.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CDC_2
|
||||
#include "USBD_Config_CDC_2.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CDC_3
|
||||
#include "USBD_Config_CDC_3.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_USB_Device_ADC_0
|
||||
#include "USBD_Config_ADC_0.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_ADC_1
|
||||
#include "USBD_Config_ADC_1.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_ADC_2
|
||||
#include "USBD_Config_ADC_2.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_ADC_3
|
||||
#include "USBD_Config_ADC_3.h"
|
||||
#endif
|
||||
|
||||
#include "usbd_config.h"
|
||||
@ -0,0 +1,171 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
* MDK Middleware - Component ::USB:Device
|
||||
* Copyright (c) 2004-2015 ARM Germany GmbH. All rights reserved.
|
||||
*------------------------------------------------------------------------------
|
||||
* Name: USBD_Config_HID_0.h
|
||||
* Purpose: USB Device Human Interface Device class (HID) Configuration
|
||||
* Rev.: V5.0.1
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <h>USB Device: Human Interface Device class (HID) 0
|
||||
// <o>Assign Device Class to USB Device # <0-3>
|
||||
// <i>Select USB Device that is used for this Device Class instance
|
||||
#define USBD_HID0_DEV 0
|
||||
|
||||
// <h>Interrupt Endpoint Settings
|
||||
// <i>By default, the settings match the first USB Class instance in a USB Device.
|
||||
// <i>Endpoint conflicts are flagged by compile-time error messages.
|
||||
//
|
||||
// <h>Interrupt IN Endpoint Settings
|
||||
// <o.0..3>Interrupt IN Endpoint Number
|
||||
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
|
||||
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
|
||||
#define USBD_HID0_EP_INT_IN 1
|
||||
|
||||
// <h>Endpoint Settings
|
||||
// <i>Parameters are used to create USB Descriptors, HID Device Descriptor
|
||||
// <i>and for memory allocation in the USB component.
|
||||
//
|
||||
// <h>Full/Low-speed (High-speed disabled)
|
||||
// <i>Parameters apply when High-speed is disabled in USBD_Config_n.c
|
||||
// <o.0..6>Maximum Endpoint Packet Size (in bytes) <0-64>
|
||||
// <i>Specifies the physical packet size used for information exchange.
|
||||
// <i>Maximum value is 64.
|
||||
#define USBD_HID0_EP_INT_IN_WMAXPACKETSIZE 64
|
||||
|
||||
// <o.0..7>Endpoint polling Interval (in ms) <1-255>
|
||||
// <i>Specifies the frequency of requests initiated by USB Host for
|
||||
// <i>function USBD_HIDn_GetReport.
|
||||
#define USBD_HID0_EP_INT_IN_BINTERVAL 1
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>High-speed
|
||||
// <i>Parameters apply when High-speed is enabled in USBD_Config_n.c
|
||||
//
|
||||
// <o.0..10>Maximum Endpoint Packet Size (in bytes) <0-1024>
|
||||
// <i>Specifies the physical packet size used for information exchange.
|
||||
// <i>Maximum value is 1024.
|
||||
// <o.11..12>Additional transactions per microframe
|
||||
// <i>Additional transactions improve communication performance.
|
||||
// <0=>None <1=>1 additional <2=>2 additional
|
||||
#define USBD_HID0_EP_INT_IN_HS_WMAXPACKETSIZE 64
|
||||
|
||||
// <o.0..4>Endpoint polling Interval (in 125 us intervals)
|
||||
// <i>Specifies the frequency of requests initiated by USB Host for
|
||||
// <i>function USBD_HIDn_GetReport.
|
||||
// <1=> 1 <2=> 2 <3=> 4 <4=> 8
|
||||
// <5=> 16 <6=> 32 <7=> 64 <8=> 128
|
||||
// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048
|
||||
// <13=>4096 <14=>8192 <15=>16384 <16=>32768
|
||||
#define USBD_HID0_EP_INT_IN_HS_BINTERVAL 1
|
||||
|
||||
// </h>
|
||||
// </h>
|
||||
// </h>
|
||||
|
||||
// <h>Interrupt OUT Endpoint Settings
|
||||
// <o.0..3>Interrupt OUT Endpoint Number
|
||||
// <i>When OUT Endpoint is set to "Not used" the USB Host uses
|
||||
// <i>the Control Endpoint 0 for Out Reports.
|
||||
// <0=>Not used
|
||||
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
|
||||
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
|
||||
#define USBD_HID0_EP_INT_OUT 1
|
||||
|
||||
// <h>Endpoint Settings
|
||||
// <i>Parameters are used to create USB Descriptors, HID Device Descriptor
|
||||
// <i>and for memory allocation in the USB component.
|
||||
//
|
||||
// <h>Full/Low-speed (High-speed disabled)
|
||||
// <i>Parameters apply when High-speed is disabled in USBD_Config_n.c
|
||||
// <o.0..6>Maximum Endpoint Packet Size (in bytes) <0-64>
|
||||
// <i>Specifies the physical packet size used for information exchange.
|
||||
// <i>Maximum value is 64.
|
||||
#define USBD_HID0_EP_INT_OUT_WMAXPACKETSIZE 64
|
||||
|
||||
// <o.0..7>Endpoint polling Interval (in ms) <1-255>
|
||||
// <i>Specifies the frequency of requests initiated by USB Host for
|
||||
// <i>function USBD_HIDn_GetReport.
|
||||
#define USBD_HID0_EP_INT_OUT_BINTERVAL 1
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>High-speed
|
||||
// <i>Parameters apply when High-speed is enabled in USBD_Config_n.c
|
||||
//
|
||||
// <o.0..10>Maximum Endpoint Packet Size (in bytes) <0-1024>
|
||||
// <i>Specifies the physical packet size used for information exchange.
|
||||
// <i>Maximum value is 1024.
|
||||
// <o.11..12>Additional transactions per microframe
|
||||
// <i>Additional transactions improve communication performance.
|
||||
// <0=>None <1=>1 additional <2=>2 additional
|
||||
#define USBD_HID0_EP_INT_OUT_HS_WMAXPACKETSIZE 64
|
||||
|
||||
// <o.0..4>Endpoint polling Interval (in 125 us intervals)
|
||||
// <i>Specifies the frequency of requests initiated by USB Host for
|
||||
// <i>function USBD_HIDn_GetReport.
|
||||
// <1=> 1 <2=> 2 <3=> 4 <4=> 8
|
||||
// <5=> 16 <6=> 32 <7=> 64 <8=> 128
|
||||
// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048
|
||||
// <13=>4096 <14=>8192 <15=>16384 <16=>32768
|
||||
#define USBD_HID0_EP_INT_OUT_HS_BINTERVAL 1
|
||||
|
||||
// </h>
|
||||
// </h>
|
||||
// </h>
|
||||
// </h>
|
||||
|
||||
// <h>Human Interface Device Class Settings
|
||||
// <i>Parameters are used to create USB Descriptors, USB HID Report Descriptor
|
||||
// <i>and for memory allocation in the USB component.
|
||||
//
|
||||
// <s.126>HID Interface String
|
||||
#define USBD_HID0_STR_DESC L"LPC-Link-II CMSIS-DAP"
|
||||
|
||||
// <o.0..4>Number of Input Reports <1-32>
|
||||
// <i>Configures max 'rid' value for USBD_HID0_GetReport and USBD_HID_GetReportTrigger
|
||||
#define USBD_HID0_IN_REPORT_NUM 1
|
||||
|
||||
// <o.0..4>Number of Output Reports <1-32>
|
||||
// <i>Configures max 'rid' value for USBD_HID0_SetReport
|
||||
#define USBD_HID0_OUT_REPORT_NUM 1
|
||||
|
||||
// <o.0..15>Maximum Input Report Size (in bytes) <1-65535>
|
||||
// <i>Allocates memory and configures 'len' value for USBD_HID0_GetReport
|
||||
// <i>and USBD_HID_GetReportTrigger
|
||||
#define USBD_HID0_IN_REPORT_MAX_SZ 1024
|
||||
|
||||
// <o.0..15>Maximum Output Report Size (in bytes) <1-65535>
|
||||
// <i>Allocates memory and configures 'len' value for USBD_HID0_SetReport
|
||||
// <i>when rtype=HID_REPORT_OUTPUT.
|
||||
#define USBD_HID0_OUT_REPORT_MAX_SZ 1024
|
||||
|
||||
// <o.0..15>Maximum Feature Report Size (in bytes) <1-65535>
|
||||
// <i>Allocates memory and configures 'len' value for USBD_HID0_SetReport
|
||||
// <i>when rtype=HID_REPORT_FEATURE
|
||||
#define USBD_HID0_FEAT_REPORT_MAX_SZ 1
|
||||
|
||||
// <e.0>Use User Provided HID Report Descriptor
|
||||
// <i>User needs to provide HID Report Descriptor in array
|
||||
// <i>const uint8_t usbd_hid0_report_descriptor[]
|
||||
#define USBD_HID0_USER_REPORT_DESCRIPTOR 0
|
||||
|
||||
// <o>User Provided HID Report Descriptor Size (in bytes) <1-65535>
|
||||
#define USBD_HID0_USER_REPORT_DESCRIPTOR_SIZE 33
|
||||
|
||||
// </e>
|
||||
// </h>
|
||||
|
||||
// <h>OS Resources Settings
|
||||
// <i>These settings are used to optimize usage of OS resources.
|
||||
// <o>Human Interface Device Class Thread Stack Size <64-65536>
|
||||
#define USBD_HID0_THREAD_STACK_SIZE 512
|
||||
|
||||
// Human Interface Device Class Thread Priority
|
||||
#define USBD_HID0_THREAD_PRIORITY osPriorityAboveNormal
|
||||
|
||||
// </h>
|
||||
// </h>
|
||||
@ -0,0 +1,237 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
* MDK Middleware - Component ::USB:Device
|
||||
* Copyright (c) 2004-2014 ARM Germany GmbH. All rights reserved.
|
||||
*------------------------------------------------------------------------------
|
||||
* Name: USBD_User_HID_0.c
|
||||
* Purpose: USB Device Human Interface Device class (HID) User module
|
||||
* Rev.: V6.2
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* \addtogroup usbd_hidFunctions
|
||||
*
|
||||
* USBD_User_HID_0.c implements the application specific functionality of the
|
||||
* HID class and is used to receive and send data reports to the USB Host.
|
||||
*
|
||||
* The implementation must match the configuration file USBD_Config_HID_0.h.
|
||||
* The following values in USBD_Config_HID_0.h affect the user code:
|
||||
*
|
||||
* - 'Endpoint polling Interval' specifies the frequency of requests
|
||||
* initiated by USB Host for \ref USBD_HIDn_GetReport.
|
||||
*
|
||||
* - 'Number of Output Reports' configures the values for \em rid of
|
||||
* \ref USBD_HIDn_SetReport.
|
||||
*
|
||||
* - 'Number of Input Reports' configures the values for \em rid of
|
||||
* \ref USBD_HIDn_GetReport and \ref USBD_HID_GetReportTrigger.
|
||||
*
|
||||
* - 'Maximum Input Report Size' specifies the maximum value for:
|
||||
* - return of \ref USBD_HIDn_GetReport
|
||||
* - len of \ref USBD_HID_GetReportTrigger.
|
||||
*
|
||||
* - 'Maximum Output Report Size' specifies the maximum value for \em len
|
||||
* in \ref USBD_HIDn_SetReport for rtype=HID_REPORT_OUTPUT
|
||||
*
|
||||
* - 'Maximum Feature Report Size' specifies the maximum value for \em len
|
||||
* in \ref USBD_HIDn_SetReport for rtype=HID_REPORT_FEATURE
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
//! [code_USBD_User_HID]
|
||||
|
||||
#include <string.h>
|
||||
#define osObjectsExternal
|
||||
#include "cmsis_os.h"
|
||||
#include "osObjects.h"
|
||||
#include "rl_usb.h"
|
||||
#include "USB\USBD_Config_HID_0.h"
|
||||
#include "DAP_config.h"
|
||||
#include "DAP.h"
|
||||
|
||||
|
||||
#if (USBD_HID0_OUT_REPORT_MAX_SZ != DAP_PACKET_SIZE)
|
||||
#error "USB HID0 Output Report Size must match DAP Packet Size"
|
||||
#endif
|
||||
#if (USBD_HID0_IN_REPORT_MAX_SZ != DAP_PACKET_SIZE)
|
||||
#error "USB HID Input Report Size must match DAP Packet Size"
|
||||
#endif
|
||||
|
||||
static uint16_t USB_RequestIndexI; // Request Index In
|
||||
static uint16_t USB_RequestIndexO; // Request Index Out
|
||||
static uint16_t USB_RequestCountI; // Request Count In
|
||||
static uint16_t USB_RequestCountO; // Request Count Out
|
||||
|
||||
static uint16_t USB_ResponseIndexI; // Response Index In
|
||||
static uint16_t USB_ResponseIndexO; // Response Index Out
|
||||
static uint16_t USB_ResponseCountI; // Response Count In
|
||||
static uint16_t USB_ResponseCountO; // Response Count Out
|
||||
static uint8_t USB_ResponseIdle; // Response Idle Flag
|
||||
|
||||
static uint8_t USB_Request [DAP_PACKET_COUNT][DAP_PACKET_SIZE]; // Request Buffer
|
||||
static uint8_t USB_Response[DAP_PACKET_COUNT][DAP_PACKET_SIZE]; // Response Buffer
|
||||
|
||||
|
||||
// Called during USBD_Initialize to initialize the USB Device class.
|
||||
void USBD_HID0_Initialize (void) {
|
||||
// Initialize variables
|
||||
USB_RequestIndexI = 0U;
|
||||
USB_RequestIndexO = 0U;
|
||||
USB_RequestCountI = 0U;
|
||||
USB_RequestCountO = 0U;
|
||||
USB_ResponseIndexI = 0U;
|
||||
USB_ResponseIndexO = 0U;
|
||||
USB_ResponseCountI = 0U;
|
||||
USB_ResponseCountO = 0U;
|
||||
USB_ResponseIdle = 1U;
|
||||
}
|
||||
|
||||
|
||||
// Called during USBD_Uninitialize to de-initialize the USB Device class.
|
||||
void USBD_HID0_Uninitialize (void) {
|
||||
}
|
||||
|
||||
|
||||
// \brief Prepare HID Report data to send.
|
||||
// \param[in] rtype report type:
|
||||
// - HID_REPORT_INPUT = input report requested
|
||||
// - HID_REPORT_FEATURE = feature report requested
|
||||
// \param[in] req request type:
|
||||
// - USBD_HID_REQ_EP_CTRL = control endpoint request
|
||||
// - USBD_HID_REQ_PERIOD_UPDATE = idle period expiration request
|
||||
// - USBD_HID_REQ_EP_INT = previously sent report on interrupt endpoint request
|
||||
// \param[in] rid report ID (0 if only one report exists).
|
||||
// \param[out] buf buffer containing report data to send.
|
||||
// \return number of report data bytes prepared to send or invalid report requested.
|
||||
// - value >= 0: number of report data bytes prepared to send
|
||||
// - value = -1: invalid report requested
|
||||
int32_t USBD_HID0_GetReport (uint8_t rtype, uint8_t req, uint8_t rid, uint8_t *buf) {
|
||||
|
||||
switch (rtype) {
|
||||
case HID_REPORT_INPUT:
|
||||
switch (req) {
|
||||
case USBD_HID_REQ_EP_CTRL: // Explicit USB Host request via Control OUT Endpoint
|
||||
case USBD_HID_REQ_PERIOD_UPDATE: // Periodic USB Host request via Interrupt OUT Endpoint
|
||||
break;
|
||||
case USBD_HID_REQ_EP_INT: // Called after USBD_HID_GetReportTrigger to signal data obtained.
|
||||
if (USB_ResponseCountI != USB_ResponseCountO) {
|
||||
// Load data from response buffer to be sent back
|
||||
memcpy(buf, USB_Response[USB_ResponseIndexO], DAP_PACKET_SIZE);
|
||||
USB_ResponseIndexO++;
|
||||
if (USB_ResponseIndexO == DAP_PACKET_COUNT) {
|
||||
USB_ResponseIndexO = 0U;
|
||||
}
|
||||
USB_ResponseCountO++;
|
||||
return ((int32_t)DAP_PACKET_SIZE);
|
||||
} else {
|
||||
USB_ResponseIdle = 1U;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case HID_REPORT_FEATURE:
|
||||
break;
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
// \brief Process received HID Report data.
|
||||
// \param[in] rtype report type:
|
||||
// - HID_REPORT_OUTPUT = output report received
|
||||
// - HID_REPORT_FEATURE = feature report received
|
||||
// \param[in] req request type:
|
||||
// - USBD_HID_REQ_EP_CTRL = report received on control endpoint
|
||||
// - USBD_HID_REQ_EP_INT = report received on interrupt endpoint
|
||||
// \param[in] rid report ID (0 if only one report exists).
|
||||
// \param[in] buf buffer that receives report data.
|
||||
// \param[in] len length of received report data.
|
||||
// \return true received report data processed.
|
||||
// \return false received report data not processed or request not supported.
|
||||
bool USBD_HID0_SetReport (uint8_t rtype, uint8_t req, uint8_t rid, const uint8_t *buf, int32_t len) {
|
||||
|
||||
switch (rtype) {
|
||||
case HID_REPORT_OUTPUT:
|
||||
if (len == 0) { break; }
|
||||
if (buf[0] == ID_DAP_TransferAbort) {
|
||||
DAP_TransferAbort = 1U;
|
||||
break;
|
||||
}
|
||||
if ((uint16_t)(USB_RequestCountI - USB_RequestCountO) == DAP_PACKET_COUNT) {
|
||||
osSignalSet(HID0_ThreadId, 0x80);
|
||||
break; // Discard packet when buffer is full
|
||||
}
|
||||
// Store received data into request buffer
|
||||
memcpy(USB_Request[USB_RequestIndexI], buf, len);
|
||||
USB_RequestIndexI++;
|
||||
if (USB_RequestIndexI == DAP_PACKET_COUNT) {
|
||||
USB_RequestIndexI = 0U;
|
||||
}
|
||||
USB_RequestCountI++;
|
||||
osSignalSet(HID0_ThreadId, 0x01);
|
||||
break;
|
||||
case HID_REPORT_FEATURE:
|
||||
break;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
// HID0 Thread.
|
||||
void HID0_Thread (void const *arg) {
|
||||
osEvent evt;
|
||||
uint32_t n;
|
||||
|
||||
for (;;) {
|
||||
osSignalWait(0, osWaitForever);
|
||||
|
||||
// Process pending requests
|
||||
while (USB_RequestCountI != USB_RequestCountO) {
|
||||
|
||||
// Handle Queue Commands
|
||||
n = USB_RequestIndexO;
|
||||
while (USB_Request[n][0] == ID_DAP_QueueCommands) {
|
||||
USB_Request[n][0] = ID_DAP_ExecuteCommands;
|
||||
n++;
|
||||
if (n == DAP_PACKET_COUNT) {
|
||||
n = 0U;
|
||||
}
|
||||
if (n == USB_RequestIndexI) {
|
||||
evt = osSignalWait(0, osWaitForever);
|
||||
if (evt.value.signals & 0x80) { break; }
|
||||
}
|
||||
}
|
||||
|
||||
// Execute DAP Command (process request and prepare response)
|
||||
DAP_ExecuteCommand(USB_Request[USB_RequestIndexO], USB_Response[USB_ResponseIndexI]);
|
||||
|
||||
// Update Request Index and Count
|
||||
USB_RequestIndexO++;
|
||||
if (USB_RequestIndexO == DAP_PACKET_COUNT) {
|
||||
USB_RequestIndexO = 0U;
|
||||
}
|
||||
USB_RequestCountO++;
|
||||
|
||||
// Update Response Index and Count
|
||||
USB_ResponseIndexI++;
|
||||
if (USB_ResponseIndexI == DAP_PACKET_COUNT) {
|
||||
USB_ResponseIndexI = 0U;
|
||||
}
|
||||
USB_ResponseCountI++;
|
||||
|
||||
if (USB_ResponseIdle) {
|
||||
if (USB_ResponseCountI != USB_ResponseCountO) {
|
||||
// Load data from response buffer to be sent back
|
||||
n = USB_ResponseIndexO++;
|
||||
if (USB_ResponseIndexO == DAP_PACKET_COUNT) {
|
||||
USB_ResponseIndexO = 0U;
|
||||
}
|
||||
USB_ResponseCountO++;
|
||||
USB_ResponseIdle = 0U;
|
||||
USBD_HID_GetReportTrigger(0U, 0U, USB_Response[n], DAP_PACKET_SIZE);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//! [code_USBD_User_HID]
|
||||
@ -0,0 +1,50 @@
|
||||
/******************************************************************************
|
||||
* @file main.c
|
||||
* @brief CMSIS-DAP Main module
|
||||
* @version V1.10
|
||||
* @date 20. Jan 2015
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2012-2015 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "cmsis_os.h"
|
||||
#include "osObjects.h"
|
||||
#include "rl_usb.h"
|
||||
#include "DAP_config.h"
|
||||
#include "DAP.h"
|
||||
|
||||
// Main program
|
||||
int main (void) {
|
||||
|
||||
DAP_Setup(); // DAP Setup
|
||||
|
||||
USBD_Initialize(0U); // USB Device Initialization
|
||||
USBD_Connect(0U); // USB Device Connect
|
||||
|
||||
while (!USBD_Configured(0U)); // Wait for USB Device to configure
|
||||
|
||||
LED_CONNECTED_OUT(1U); // Turn on Debugger Connected LED
|
||||
LED_RUNNING_OUT(1U); // Turn on Target Running LED
|
||||
Delayms(500U); // Wait for 500ms
|
||||
LED_RUNNING_OUT(0U); // Turn off Target Running LED
|
||||
LED_CONNECTED_OUT(0U); // Turn off Debugger Connected LED
|
||||
|
||||
// Create HID Thread
|
||||
HID0_ThreadId = osThreadCreate(osThread(HID0_Thread), NULL);
|
||||
|
||||
osThreadSetPriority(osThreadGetId(), osPriorityIdle);
|
||||
for (;;); // Endless Loop
|
||||
}
|
||||
@ -0,0 +1,37 @@
|
||||
/******************************************************************************
|
||||
* @file osObjects.h
|
||||
* @brief CMSIS-DAP RTOS Objects
|
||||
* @version V1.10
|
||||
* @date 20. Jan 2015
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2012-2015 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __osObjects_h__
|
||||
#define __osObjects_h__
|
||||
|
||||
#include "cmsis_os.h"
|
||||
|
||||
#ifdef osObjectsExternal
|
||||
extern osThreadId HID0_ThreadId;
|
||||
#else
|
||||
osThreadId HID0_ThreadId;
|
||||
#endif
|
||||
|
||||
extern void HID0_Thread (void const *arg);
|
||||
osThreadDef(HID0_Thread, osPriorityNormal, 1U, 512U);
|
||||
|
||||
#endif /* __osObjects_h__ */
|
||||
@ -0,0 +1 @@
|
||||
CMSIS-DAP USB HID Firmware for Infineon XMC4200 board.
|
||||
File diff suppressed because one or more lines are too long
@ -0,0 +1,519 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>XMC4200</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>9</CpuCode>
|
||||
<Books>
|
||||
<Book>
|
||||
<Number>0</Number>
|
||||
<Title>User Manual (XMC4200 CPU Board - Actuator (CPU_42A))</Title>
|
||||
<Path>C:\Keil_v5\ARM\PACK\Infineon\XMC4000_DFP\2.3.0\Documents\Board_Users_Manual_CPU_Board_XMC4400_General_Purpose_R1 0.pdf</Path>
|
||||
</Book>
|
||||
<Book>
|
||||
<Number>1</Number>
|
||||
<Title>Schematics (XMC4200 CPU Board - Actuator (CPU_42A))</Title>
|
||||
<Path>C:\Keil_v5\ARM\PACK\Infineon\XMC4000_DFP\2.3.0\Documents\PCB_Sources_Eagle_CPU_42A-V1-4.zip</Path>
|
||||
</Book>
|
||||
<Book>
|
||||
<Number>2</Number>
|
||||
<Title>XMC4200 CPU Board - Actuator (CPU_42A) (XMC4200 CPU Board - Actuator (CPU_42A))</Title>
|
||||
<Path>http://www.infineon.com/cms/en/product/microcontroller/32-bit-industrial-microcontroller-based-on-arm-registered-cortex-tm-m/32-bit-xmc4000-industrial-microcontroller-arm-registered-cortex-tm-m4/channel.html?channel=db3a30433580b3710135a03abaf9385e</Path>
|
||||
</Book>
|
||||
</Books>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<nTsel>7</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\ULP2CM3.DLL</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMRTXEVENTFLAGS</Key>
|
||||
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGTARM</Key>
|
||||
<Name>(1010=75,103,485,649,0)(1007=105,136,282,400,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMDBGFLAGS</Key>
|
||||
<Name></Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGUARM</Key>
|
||||
<Name></Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ULP2CM3</Key>
|
||||
<Name>-UP1445219 -O198 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC80000000 -TP11 -TDX0 -TDD0 -TDS1 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN2 -FF0XMC4200_4100_256.FLM -FS0C000000 -FL040000 -FP0($$Device:XMC4200-Q48x256$Flash\XMC4200_4100_256.FLM) -FF1XMC4200_4100c_256.FLM -FS18000000 -FL140000 -FP1($$Device:XMC4200-Q48x256$Flash\XMC4200_4100c_256.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>-UV0001BDE -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC180000000 -TP21 -TDS802F -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FN2 -FC1000 -FD20000000 -FF0XMC4200_4100_256 -FF1XMC4200_4100c_256 -FL040000 -FL140000 -FS0C000000 -FS18000000 -FP0($$Device:XMC4200-Q48x256$Flash\XMC4200_4100_256.FLM) -FP1($$Device:XMC4200-Q48x256$Flash\XMC4200_4100c_256.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint>
|
||||
<Bp>
|
||||
<Number>0</Number>
|
||||
<Type>0</Type>
|
||||
<LineNumber>107</LineNumber>
|
||||
<EnabledFlag>0</EnabledFlag>
|
||||
<Address>134228026</Address>
|
||||
<ByteObject>0</ByteObject>
|
||||
<HtxType>0</HtxType>
|
||||
<ManyObjects>0</ManyObjects>
|
||||
<SizeOfObject>0</SizeOfObject>
|
||||
<BreakByAccess>0</BreakByAccess>
|
||||
<BreakIfRCount>1</BreakIfRCount>
|
||||
<Filename>..\..\Source\SWO.c</Filename>
|
||||
<ExecCommand></ExecCommand>
|
||||
<Expression>\\CMSIS_DAP\../../Source/SWO.c\107</Expression>
|
||||
</Bp>
|
||||
</Breakpoint>
|
||||
<WatchWindow1>
|
||||
<Ww>
|
||||
<count>0</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>usbd0_string_descriptor</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>1</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>data</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>2</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>gintmsk</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>3</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>TraceIn</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>4</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>TraceOut</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>5</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>TracePending</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>6</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>\\CMSIS_DAP\../../Source/SWO.c\TraceIn</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>7</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>\\CMSIS_DAP\../../Source/SWO.c\TraceOut</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>8</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>\\CMSIS_DAP\../../Source/SWO.c\TracePending</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>9</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>\\CMSIS_DAP\../../Source/SWO.c\TraceStatus</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>10</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>\\CMSIS_DAP\../../Source/SWO.c\TraceMode</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>11</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>usbd0_string_descriptor</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>12</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>baudrate,0x0A</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>13</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>peripheral_clock,0x0A</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>14</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>pdiv_frac_min</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>15</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>clock_divider_min,0x0A</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>16</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>pdiv_int_min</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>17</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>rate,0x0A</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>18</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>oversampling</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>19</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>config->baudrate</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>20</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>uart_default_config</ItemText>
|
||||
</Ww>
|
||||
</WatchWindow1>
|
||||
<MemoryWindow1>
|
||||
<Mm>
|
||||
<WinNumber>1</WinNumber>
|
||||
<SubType>0</SubType>
|
||||
<ItemText>0x20003120</ItemText>
|
||||
<AccSizeX>0</AccSizeX>
|
||||
</Mm>
|
||||
</MemoryWindow1>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>1</periodic>
|
||||
<aLwin>1</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>1</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<SystemViewers>
|
||||
<Entry>
|
||||
<Name>System Viewer\PORT0</Name>
|
||||
<WinId>35902</WinId>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Name>System Viewer\USIC1</Name>
|
||||
<WinId>35904</WinId>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Name>System Viewer\USIC1_CH0</Name>
|
||||
<WinId>35905</WinId>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Name>System Viewer\USIC1_CH1</Name>
|
||||
<WinId>35903</WinId>
|
||||
</Entry>
|
||||
</SystemViewers>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>Source</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>1</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\main.c</PathWithFileName>
|
||||
<FilenameWithoutPath>main.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>2</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\USBD_User_HID_0.c</PathWithFileName>
|
||||
<FilenameWithoutPath>USBD_User_HID_0.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>Documentation</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>2</GroupNumber>
|
||||
<FileNumber>3</FileNumber>
|
||||
<FileType>5</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\Abstract.txt</PathWithFileName>
|
||||
<FilenameWithoutPath>Abstract.txt</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>CMSIS DAP</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>4</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>1</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\Source\DAP.c</PathWithFileName>
|
||||
<FilenameWithoutPath>DAP.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>5</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\Source\JTAG_DP.c</PathWithFileName>
|
||||
<FilenameWithoutPath>JTAG_DP.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>6</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\Source\SW_DP.c</PathWithFileName>
|
||||
<FilenameWithoutPath>SW_DP.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>7</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\Source\SWO.c</PathWithFileName>
|
||||
<FilenameWithoutPath>SWO.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>CMSIS Driver Workaround</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>4</GroupNumber>
|
||||
<FileNumber>8</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\UART.c</PathWithFileName>
|
||||
<FilenameWithoutPath>UART.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::CMSIS Driver</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::Device</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::USB</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
@ -0,0 +1,681 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>XMC4200</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>5060020::V5.06 (build 20)::ARMCC</pCCUsed>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>XMC4200-Q48x256</Device>
|
||||
<Vendor>Infineon</Vendor>
|
||||
<PackID>Infineon.XMC4000_DFP.2.3.0</PackID>
|
||||
<PackURL>http://media.infineon.com/mdk/</PackURL>
|
||||
<Cpu>IROM(0x08000000,0x40000) IROM2(0x0C000000,0x40000) IRAM(0x20000000,0x5FC0) IRAM2(0x1FFFC000,0x4000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0XMC4200_4100_256 -FS0C000000 -FL040000 -FF1XMC4200_4100c_256 -FS18000000 -FL140000 -FP0($$Device:XMC4200-Q48x256$Flash\XMC4200_4100_256.FLM) -FP1($$Device:XMC4200-Q48x256$Flash\XMC4200_4100c_256.FLM))</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:XMC4200-Q48x256$Device\XMC4200_series\Include\XMC4200.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:XMC4200-Q48x256$SVD\XMC4200.svd</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\Objects\</OutputDirectory>
|
||||
<OutputName>CMSIS_DAP</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments> -REMAP -MPU</SimDllArguments>
|
||||
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments> -MPU</TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
<Simulator>
|
||||
<UseSimulator>0</UseSimulator>
|
||||
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||
<RunToMain>1</RunToMain>
|
||||
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||
<RestoreFunctions>1</RestoreFunctions>
|
||||
<RestoreToolbox>1</RestoreToolbox>
|
||||
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
|
||||
<RestoreSysVw>1</RestoreSysVw>
|
||||
</Simulator>
|
||||
<Target>
|
||||
<UseTarget>1</UseTarget>
|
||||
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||
<RunToMain>1</RunToMain>
|
||||
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||
<RestoreFunctions>0</RestoreFunctions>
|
||||
<RestoreToolbox>1</RestoreToolbox>
|
||||
<RestoreTracepoints>1</RestoreTracepoints>
|
||||
<RestoreSysVw>1</RestoreSysVw>
|
||||
</Target>
|
||||
<RunDebugAfterBuild>0</RunDebugAfterBuild>
|
||||
<TargetSelection>7</TargetSelection>
|
||||
<SimDlls>
|
||||
<CpuDll></CpuDll>
|
||||
<CpuDllArguments></CpuDllArguments>
|
||||
<PeripheralDll></PeripheralDll>
|
||||
<PeripheralDllArguments></PeripheralDllArguments>
|
||||
<InitializationFile></InitializationFile>
|
||||
</SimDlls>
|
||||
<TargetDlls>
|
||||
<CpuDll></CpuDll>
|
||||
<CpuDllArguments></CpuDllArguments>
|
||||
<PeripheralDll></PeripheralDll>
|
||||
<PeripheralDllArguments></PeripheralDllArguments>
|
||||
<InitializationFile></InitializationFile>
|
||||
<Driver>BIN\ULP2CM3.DLL</Driver>
|
||||
</TargetDlls>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4096</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3>"" ()</Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M4"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>1</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>2</RvdsVP>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>1</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>1</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x5fc0</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x8000000</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x8000000</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0xc000000</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x5fc0</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x1fffc000</StartAddress>
|
||||
<Size>0x4000</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>1</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>0</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>0</uC99>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>0</v6Lang>
|
||||
<v6LangP>0</v6LangP>
|
||||
<vShortEn>0</vShortEn>
|
||||
<vShortWch>0</vShortWch>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath>.;..\..\Include</IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>1</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x10000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile></ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>Source</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>main.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\main.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>USBD_User_HID_0.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\USBD_User_HID_0.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Documentation</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>Abstract.txt</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Abstract.txt</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>CMSIS DAP</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>DAP.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Source\DAP.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>JTAG_DP.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Source\JTAG_DP.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>SW_DP.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Source\SW_DP.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>SWO.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Source\SWO.c</FilePath>
|
||||
<FileOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>2</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>2</IncludeInBuild>
|
||||
<AlwaysBuild>2</AlwaysBuild>
|
||||
<GenerateAssemblyFile>2</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>2</AssembleAssemblyFile>
|
||||
<PublicsOnly>2</PublicsOnly>
|
||||
<StopOnExitCode>11</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<FileArmAds>
|
||||
<Cads>
|
||||
<interw>2</interw>
|
||||
<Optim>0</Optim>
|
||||
<oTime>2</oTime>
|
||||
<SplitLS>2</SplitLS>
|
||||
<OneElfS>2</OneElfS>
|
||||
<Strict>2</Strict>
|
||||
<EnumInt>2</EnumInt>
|
||||
<PlainCh>2</PlainCh>
|
||||
<Ropi>2</Ropi>
|
||||
<Rwpi>2</Rwpi>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>2</uThumb>
|
||||
<uSurpInc>2</uSurpInc>
|
||||
<uC99>2</uC99>
|
||||
<useXO>2</useXO>
|
||||
<v6Lang>0</v6Lang>
|
||||
<v6LangP>0</v6LangP>
|
||||
<vShortEn>0</vShortEn>
|
||||
<vShortWch>0</vShortWch>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define>USART_PORT=2</Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
</FileArmAds>
|
||||
</FileOption>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>CMSIS Driver Workaround</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>UART.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\UART.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::CMSIS Driver</GroupName>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::Device</GroupName>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::USB</GroupName>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis>
|
||||
<api Capiversion="2.01" Cclass="CMSIS Driver" Cgroup="USB Device" exclusive="0">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="XMC4200"/>
|
||||
</targetInfos>
|
||||
</api>
|
||||
<api Capiversion="1.0" Cclass="CMSIS" Cgroup="RTOS" exclusive="1">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="XMC4200"/>
|
||||
</targetInfos>
|
||||
</api>
|
||||
</apis>
|
||||
<components>
|
||||
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="4.1.0" condition="CMSIS Core">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="XMC4200"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cvendor="ARM" Cversion="4.78.0" condition="Cortex-M Device Startup">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="XMC4200"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Capiversion="2.01" Cclass="CMSIS Driver" Cgroup="USB Device" Csub="USB" Cvendor="Infineon" Cversion="2.03" condition="XMC4 CMSIS Driver USBD">
|
||||
<package license="License\CMSIS_END_USER_LICENSE_AGREEMENT.txt" name="XMC4000_DFP" schemaVersion="1.2" supportContact="http://www.infineon.com/cms/en/corporate/company/contact/support/index.html" url="http://media.infineon.com/mdk/" vendor="Infineon" version="2.3.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="XMC4200"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="RTE_Device" Cvendor="Infineon" Cversion="1.0.1" condition="XMC4 CMSIS">
|
||||
<package license="License\CMSIS_END_USER_LICENSE_AGREEMENT.txt" name="XMC4000_DFP" schemaVersion="1.2" supportContact="http://www.infineon.com/cms/en/corporate/company/contact/support/index.html" url="http://media.infineon.com/mdk/" vendor="Infineon" version="2.3.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="XMC4200"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Infineon" Cversion="1.0.0" condition="XMC4 CMSIS">
|
||||
<package license="License\CMSIS_END_USER_LICENSE_AGREEMENT.txt" name="XMC4000_DFP" schemaVersion="1.2" supportContact="http://www.infineon.com/cms/en/corporate/company/contact/support/index.html" url="http://media.infineon.com/mdk/" vendor="Infineon" version="2.2.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="XMC4200">
|
||||
<c>
|
||||
<Define>USE_SPIFI=1</Define>
|
||||
</c>
|
||||
<asm>
|
||||
<Define>NO_CRP</Define>
|
||||
</asm>
|
||||
</targetInfo>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="XMClib" Csub="GPIO" Cvendor="Infineon" Cversion="2.0.0" condition="XMC4 CMSIS">
|
||||
<package license="License\CMSIS_END_USER_LICENSE_AGREEMENT.txt" name="XMC4000_DFP" schemaVersion="1.2" supportContact="http://www.infineon.com/cms/en/corporate/company/contact/support/index.html" url="http://media.infineon.com/mdk/" vendor="Infineon" version="2.3.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="XMC4200"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="XMClib" Csub="SCU" Cvendor="Infineon" Cversion="2.0.0" condition="XMC4 CMSIS">
|
||||
<package license="License\CMSIS_END_USER_LICENSE_AGREEMENT.txt" name="XMC4000_DFP" schemaVersion="1.2" supportContact="http://www.infineon.com/cms/en/corporate/company/contact/support/index.html" url="http://media.infineon.com/mdk/" vendor="Infineon" version="2.3.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="XMC4200"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="XMClib" Csub="UART" Cvendor="Infineon" Cversion="2.0.0" condition="XMC4 CMSIS SCU">
|
||||
<package license="License\CMSIS_END_USER_LICENSE_AGREEMENT.txt" name="XMC4000_DFP" schemaVersion="1.2" supportContact="http://www.infineon.com/cms/en/corporate/company/contact/support/index.html" url="http://media.infineon.com/mdk/" vendor="Infineon" version="2.3.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="XMC4200"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="CORE" Cvendor="Keil" Cversion="6.5.0" condition="USB Core">
|
||||
<package name="MDK-Middleware" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="6.5.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="XMC4200"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Device" Cvendor="Keil" Cversion="6.5.0" condition="USB Core and Device Driver" maxInstances="4">
|
||||
<package name="MDK-Middleware" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="6.5.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="XMC4200"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Device" Csub="HID" Cvendor="Keil" Cversion="6.5.0" condition="USB Device" maxInstances="4">
|
||||
<package name="MDK-Middleware" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="6.5.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="XMC4200"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
</components>
|
||||
<files>
|
||||
<file attr="config" category="source" name="CMSIS\RTOS\RTX\Templates\RTX_Conf_CM.c" version="4.70.1">
|
||||
<instance index="0">RTE\CMSIS\RTX_Conf_CM.c</instance>
|
||||
<component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cvendor="ARM" Cversion="4.78.0" condition="Cortex-M Device Startup"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="XMC4200"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="header" condition="XMC4200_Q48" name="RTE_Driver\Config\XMC4200_Q48\RTE_Device.h" version="1.0.1">
|
||||
<instance index="0">RTE\Device\XMC4200-Q48x256\RTE_Device.h</instance>
|
||||
<component Cclass="Device" Cgroup="RTE_Device" Cvendor="Infineon" Cversion="1.0.1" condition="XMC4 CMSIS"/>
|
||||
<package license="License\CMSIS_END_USER_LICENSE_AGREEMENT.txt" name="XMC4000_DFP" schemaVersion="1.2" supportContact="http://www.infineon.com/cms/en/corporate/company/contact/support/index.html" url="http://media.infineon.com/mdk/" vendor="Infineon" version="2.3.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="XMC4200"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="source" condition="XMC42xx" name="Device\XMC4200_series\Source\ARM\startup_XMC4200.s" version="1.5.0">
|
||||
<instance index="0">RTE\Device\XMC4200-Q48x256\startup_XMC4200.s</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Infineon" Cversion="1.0.0" condition="XMC4 CMSIS"/>
|
||||
<package license="License\CMSIS_END_USER_LICENSE_AGREEMENT.txt" name="XMC4000_DFP" schemaVersion="1.2" supportContact="http://www.infineon.com/cms/en/corporate/company/contact/support/index.html" url="http://media.infineon.com/mdk/" vendor="Infineon" version="2.2.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="XMC4200"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="source" condition="XMC42xx" name="Device\XMC4200_series\Source\system_XMC4200.c" version="3.1.0">
|
||||
<instance index="0">RTE\Device\XMC4200-Q48x256\system_XMC4200.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Infineon" Cversion="1.0.0" condition="XMC4 CMSIS"/>
|
||||
<package license="License\CMSIS_END_USER_LICENSE_AGREEMENT.txt" name="XMC4000_DFP" schemaVersion="1.2" supportContact="http://www.infineon.com/cms/en/corporate/company/contact/support/index.html" url="http://media.infineon.com/mdk/" vendor="Infineon" version="2.2.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="XMC4200"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="source" name="USB\Config\USBD_Config.c" version="5.00">
|
||||
<instance index="0">RTE\USB\USBD_Config_0.c</instance>
|
||||
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Device" Cvendor="Keil" Cversion="6.4.0" condition="USB Core and Device Driver" maxInstances="4"/>
|
||||
<package name="MDK-Middleware" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="6.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="XMC4200"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="source" name="USB\Config\USBD_Config_HID.h" version="5.0.1">
|
||||
<instance index="0">RTE\USB\USBD_Config_HID_0.h</instance>
|
||||
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Device" Csub="HID" Cvendor="Keil" Cversion="6.4.0" condition="USB Device" maxInstances="4"/>
|
||||
<package name="MDK-Middleware" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="6.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="XMC4200"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
</files>
|
||||
</RTE>
|
||||
|
||||
</Project>
|
||||
@ -0,0 +1,607 @@
|
||||
/**************************************************************************//**
|
||||
* @file DAP_config.h
|
||||
* @brief CMSIS-DAP Configuration File for LPC-Link-II
|
||||
* @version V1.10
|
||||
* @date 20. May 2015
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2012-2015 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __DAP_CONFIG_H__
|
||||
#define __DAP_CONFIG_H__
|
||||
|
||||
|
||||
//**************************************************************************************************
|
||||
/**
|
||||
\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
|
||||
\ingroup DAP_ConfigIO_gr
|
||||
@{
|
||||
Provides definitions about the hardware and configuration of the Debug Unit.
|
||||
|
||||
This information includes:
|
||||
- Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
|
||||
- Debug Unit communication packet size.
|
||||
- Debug Access Port communication mode (JTAG or SWD).
|
||||
- Optional information about a connected Target Device (for Evaluation Boards).
|
||||
*/
|
||||
|
||||
#include "XMC4200.h" // Debug Unit Cortex-M Processor Header File
|
||||
#include "xmc_gpio.h"
|
||||
#include "xmc4_gpio.h"
|
||||
|
||||
/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
|
||||
/// This value is used to calculate the SWD/JTAG clock speed.
|
||||
#define CPU_CLOCK 80000000U ///< Specifies the CPU Clock in Hz
|
||||
|
||||
/// Number of processor cycles for I/O Port write operations.
|
||||
/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
|
||||
/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
|
||||
/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
|
||||
/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
|
||||
/// required.
|
||||
#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
|
||||
|
||||
/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
|
||||
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
|
||||
#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available
|
||||
|
||||
/// Indicate that JTAG communication mode is available at the Debug Port.
|
||||
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
|
||||
#define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available.
|
||||
|
||||
/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
|
||||
/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
|
||||
#define DAP_JTAG_DEV_CNT 8U ///< Maximum number of JTAG devices on scan chain
|
||||
|
||||
/// Default communication mode on the Debug Access Port.
|
||||
/// Used for the command \ref DAP_Connect when Port Default mode is selected.
|
||||
#define DAP_DEFAULT_PORT 1U ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
|
||||
|
||||
/// Default communication speed on the Debug Access Port for SWD and JTAG mode.
|
||||
/// Used to initialize the default SWD/JTAG clock frequency.
|
||||
/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
|
||||
#define DAP_DEFAULT_SWJ_CLOCK 1000000U ///< Default SWD/JTAG clock frequency in Hz.
|
||||
|
||||
/// Maximum Package Size for Command and Response data.
|
||||
/// This configuration settings is used to optimized the communication performance with the
|
||||
/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
|
||||
#define DAP_PACKET_SIZE 64U ///< USB: 64 = Full-Speed, 1024 = High-Speed.
|
||||
|
||||
/// Maximum Package Buffers for Command and Response data.
|
||||
/// This configuration settings is used to optimized the communication performance with the
|
||||
/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
|
||||
/// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
|
||||
#define DAP_PACKET_COUNT 64U ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
|
||||
|
||||
/// Indicate that UART Serial Wire Output (SWO) trace is available.
|
||||
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
|
||||
#define SWO_UART 1 ///< SWO UART: 1 = available, 0 = not available
|
||||
|
||||
/// Maximum SWO UART Baudrate
|
||||
#define SWO_UART_MAX_BAUDRATE 1000000U ///< SWO UART Maximum Baudrate in Hz
|
||||
|
||||
/// Indicate that Manchester Serial Wire Output (SWO) trace is available.
|
||||
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
|
||||
#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available
|
||||
|
||||
/// SWO Trace Buffer Size.
|
||||
#define SWO_BUFFER_SIZE 8192U ///< SWO Trace Buffer Size in bytes (must be 2^n)
|
||||
|
||||
|
||||
/// Debug Unit is connected to fixed Target Device.
|
||||
/// The Debug Unit may be part of an evaluation board and always connected to a fixed
|
||||
/// known device. In this case a Device Vendor and Device Name string is stored which
|
||||
/// may be used by the debugger or IDE to configure device parameters.
|
||||
#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
|
||||
|
||||
#if TARGET_DEVICE_FIXED
|
||||
#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor
|
||||
#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device
|
||||
#endif
|
||||
|
||||
///@}
|
||||
|
||||
|
||||
// Debug Port I/O Pins
|
||||
|
||||
// SWCLK Pin P1.1
|
||||
#define PIN_SWCLK_TCK_PORT XMC_GPIO_PORT1
|
||||
#define PIN_SWCLK_TCK_BIT 1
|
||||
|
||||
// SWCLK_IN Pin P2.4
|
||||
#define PIN_SWCLK_TCK_IN_PORT XMC_GPIO_PORT2
|
||||
#define PIN_SWCLK_TCK_IN_BIT 4
|
||||
|
||||
// SWDIO out P1.5
|
||||
#define PIN_SWDIO_OUT_PORT XMC_GPIO_PORT1
|
||||
#define PIN_SWDIO_OUT_BIT 5
|
||||
|
||||
// SWDIO in P1.4
|
||||
#define PIN_SWDIO_IN_PORT XMC_GPIO_PORT1
|
||||
#define PIN_SWDIO_IN_BIT 4
|
||||
|
||||
// SWDIO Output Enable Pin P1.3
|
||||
#define PIN_SWDIO_OE_PORT XMC_GPIO_PORT1
|
||||
#define PIN_SWDIO_OE_BIT 3
|
||||
|
||||
// TDI Pin Not available
|
||||
//#define PIN_TDI_PORT
|
||||
//#define PIN_TDI_BIT
|
||||
|
||||
// TDO Pin Not available
|
||||
//#define PIN_TDO_PORT
|
||||
//#define PIN_TDO_BIT
|
||||
|
||||
// nTRST Pin Not available
|
||||
//#define PIN_nTRST_PORT
|
||||
//#define PIN_nTRST_BIT
|
||||
|
||||
// nRESET Pin P0.5
|
||||
#define PIN_nRESET_PORT XMC_GPIO_PORT0
|
||||
#define PIN_nRESET_BIT 5
|
||||
|
||||
|
||||
// Debug Unit LEDs
|
||||
|
||||
// Connected LED P0.2
|
||||
#define LED_CONNECTED_PORT XMC_GPIO_PORT0
|
||||
#define LED_CONNECTED_BIT 2
|
||||
|
||||
// Target Running LED P0.1
|
||||
#define LED_RUNNING_PORT XMC_GPIO_PORT0
|
||||
#define LED_RUNNING_BIT 1
|
||||
|
||||
|
||||
//**************************************************************************************************
|
||||
/**
|
||||
\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
|
||||
\ingroup DAP_ConfigIO_gr
|
||||
@{
|
||||
|
||||
Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
|
||||
and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
|
||||
interface of a device. The following I/O Pins are provided:
|
||||
|
||||
JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
|
||||
---------------------------- | -------------------- | ---------------------------------------------
|
||||
TCK: Test Clock | SWCLK: Clock | Output Push/Pull
|
||||
TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
|
||||
TDI: Test Data Input | | Output Push/Pull
|
||||
TDO: Test Data Output | | Input
|
||||
nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
|
||||
nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
|
||||
|
||||
|
||||
DAP Hardware I/O Pin Access Functions
|
||||
-------------------------------------
|
||||
The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
|
||||
these I/O Pins.
|
||||
|
||||
For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
|
||||
This functions are provided to achieve faster I/O that is possible with some advanced GPIO
|
||||
peripherals that can independently write/read a single I/O pin without affecting any other pins
|
||||
of the same I/O port. The following SWDIO I/O Pin functions are provided:
|
||||
- \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
|
||||
- \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
|
||||
- \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
|
||||
- \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
|
||||
*/
|
||||
|
||||
|
||||
// Configure DAP I/O pins ------------------------------
|
||||
|
||||
// LPC-Link-II HW uses buffers for debug port pins. Therefore it is not
|
||||
// possible to disable outputs SWCLK/TCK, TDI and they are left active.
|
||||
// Only SWDIO/TMS output can be disabled but it is also left active.
|
||||
// nRESET is configured for open drain mode.
|
||||
|
||||
/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
|
||||
Configures the DAP Hardware I/O pins for JTAG mode:
|
||||
- TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
|
||||
- TDO to input mode.
|
||||
*/
|
||||
static __inline void PORT_JTAG_SETUP (void) {
|
||||
// Not available
|
||||
}
|
||||
|
||||
/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
|
||||
Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
|
||||
- SWCLK, SWDIO, nRESET to output mode and set to default high level.
|
||||
- TDI, nTRST to HighZ mode (pins are unused in SWD mode).
|
||||
*/
|
||||
static __inline void PORT_SWD_SETUP (void) {
|
||||
XMC_GPIO_CONFIG_t config;
|
||||
|
||||
/* SWCLK: Enable Output */
|
||||
config.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL; /**< Defines the direction and characteristics of a pin */
|
||||
config.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH; /**< Defines output level of a pin */
|
||||
config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SHARP_EDGE; /**< Defines pad driver mode of a pin */
|
||||
XMC_GPIO_Init(PIN_SWCLK_TCK_PORT, PIN_SWCLK_TCK_BIT, &config);
|
||||
|
||||
/* SWCLK_IN: Disable Output */
|
||||
config.mode = XMC_GPIO_MODE_INPUT_TRISTATE; /**< Defines the direction and characteristics of a pin */
|
||||
XMC_GPIO_Init(PIN_SWCLK_TCK_IN_PORT, PIN_SWCLK_TCK_IN_BIT, &config);
|
||||
|
||||
/* SWDIO out: Enable Output */
|
||||
config.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL; /**< Defines the direction and characteristics of a pin */
|
||||
config.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH; /**< Defines output level of a pin */
|
||||
config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SHARP_EDGE; /**< Defines pad driver mode of a pin */
|
||||
XMC_GPIO_Init(PIN_SWDIO_OUT_PORT, PIN_SWDIO_OUT_BIT, &config);
|
||||
|
||||
/* SWDIO Output Enable: Enable Output */
|
||||
config.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL; /**< Defines the direction and characteristics of a pin */
|
||||
config.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH; /**< Defines output level of a pin */
|
||||
config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SHARP_EDGE; /**< Defines pad driver mode of a pin */
|
||||
XMC_GPIO_Init(PIN_SWDIO_OE_PORT, PIN_SWDIO_OE_BIT, &config);
|
||||
|
||||
/* SWDIO in: Enable Input */
|
||||
config.mode = XMC_GPIO_MODE_INPUT_TRISTATE; /**< Defines the direction and characteristics of a pin */
|
||||
XMC_GPIO_Init(PIN_SWDIO_IN_PORT, PIN_SWDIO_IN_BIT, &config);
|
||||
|
||||
/* nRESET: Enable I/O, open-drain, pull-up */
|
||||
/* HS: open-drain is not possible with this hardware. I reused the PC_RXD_DEV/TX signal to create the reset */
|
||||
config.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL; /**< Defines the direction and characteristics of a pin */
|
||||
config.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH; /**< Defines output level of a pin */
|
||||
config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SHARP_EDGE; /**< Defines pad driver mode of a pin */
|
||||
XMC_GPIO_Init(PIN_nRESET_PORT, PIN_nRESET_BIT, &config);
|
||||
}
|
||||
|
||||
/** Disable JTAG/SWD I/O Pins.
|
||||
Disables the DAP Hardware I/O pins which configures:
|
||||
- TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
|
||||
*/
|
||||
static __inline void PORT_OFF (void) {
|
||||
XMC_GPIO_CONFIG_t config;
|
||||
|
||||
/* SWCLK: Disable Output */
|
||||
//config.mode = XMC_GPIO_MODE_INPUT_TRISTATE; /**< Defines the direction and characteristics of a pin */
|
||||
//configuring SWCLK to tri-state mode does not make sense because the isolation device then has an undefined input
|
||||
config.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL; /**< Defines the direction and characteristics of a pin */
|
||||
config.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH; /**< Defines output level of a pin */
|
||||
config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SHARP_EDGE; /**< Defines pad driver mode of a pin */
|
||||
XMC_GPIO_Init(PIN_SWCLK_TCK_PORT, PIN_SWCLK_TCK_BIT, &config);
|
||||
|
||||
/* SWCLK_IN: Disable Output */
|
||||
config.mode = XMC_GPIO_MODE_INPUT_TRISTATE; /**< Defines the direction and characteristics of a pin */
|
||||
XMC_GPIO_Init(PIN_SWCLK_TCK_IN_PORT, PIN_SWCLK_TCK_IN_BIT, &config);
|
||||
|
||||
/* SWDIO out: Disable Output */
|
||||
//config.mode = XMC_GPIO_MODE_INPUT_TRISTATE; /**< Defines the direction and characteristics of a pin */
|
||||
//configuring SWDIO out to tri-state mode does not make sense because the isolation device then has an undefined input
|
||||
config.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL; /**< Defines the direction and characteristics of a pin */
|
||||
config.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH; /**< Defines output level of a pin */
|
||||
config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_WEAK; /**< Defines pad driver mode of a pin */
|
||||
XMC_GPIO_Init(PIN_SWDIO_OUT_PORT, PIN_SWDIO_OUT_BIT, &config);
|
||||
|
||||
/* SWDIO Output Enable: Disable Output */
|
||||
config.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL; /**< Defines the direction and characteristics of a pin */
|
||||
config.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW; /**< Defines output level of a pin */
|
||||
config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SHARP_EDGE; /**< Defines pad driver mode of a pin */
|
||||
XMC_GPIO_Init(PIN_SWDIO_OE_PORT, PIN_SWDIO_OE_BIT, &config);
|
||||
|
||||
/* SWDIO in: Enable Input */
|
||||
config.mode = XMC_GPIO_MODE_INPUT_TRISTATE; /**< Defines the direction and characteristics of a pin */
|
||||
XMC_GPIO_Init(PIN_SWDIO_IN_PORT, PIN_SWDIO_IN_BIT, &config);
|
||||
|
||||
/* nRESET: Enable I/O, open-drain, pull-up */
|
||||
/* HS: open-drain is not possible with this hardware. I reused the PC_RXD_DEV/TX signal to create the reset */
|
||||
config.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL; /**< Defines the direction and characteristics of a pin */
|
||||
config.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH; /**< Defines output level of a pin */
|
||||
config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_WEAK; /**< Defines pad driver mode of a pin */
|
||||
XMC_GPIO_Init(PIN_nRESET_PORT, PIN_nRESET_BIT, &config);
|
||||
}
|
||||
|
||||
|
||||
// SWCLK/TCK I/O pin -------------------------------------
|
||||
|
||||
/** SWCLK/TCK I/O pin: Get Input.
|
||||
\return Current status of the SWCLK/TCK DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_SWCLK_TCK_IN (void) {
|
||||
return (XMC_GPIO_GetInput(PIN_SWCLK_TCK_IN_PORT, PIN_SWCLK_TCK_IN_BIT));
|
||||
}
|
||||
|
||||
/** SWCLK/TCK I/O pin: Set Output to High.
|
||||
Set the SWCLK/TCK DAP hardware I/O pin to high level.
|
||||
*/
|
||||
static __forceinline void PIN_SWCLK_TCK_SET (void) {
|
||||
XMC_GPIO_SetOutputHigh(PIN_SWCLK_TCK_PORT, PIN_SWCLK_TCK_BIT);
|
||||
}
|
||||
|
||||
/** SWCLK/TCK I/O pin: Set Output to Low.
|
||||
Set the SWCLK/TCK DAP hardware I/O pin to low level.
|
||||
*/
|
||||
static __forceinline void PIN_SWCLK_TCK_CLR (void) {
|
||||
XMC_GPIO_SetOutputLow(PIN_SWCLK_TCK_PORT, PIN_SWCLK_TCK_BIT);
|
||||
}
|
||||
|
||||
|
||||
// SWDIO/TMS Pin I/O --------------------------------------
|
||||
|
||||
/** SWDIO/TMS I/O pin: Get Input.
|
||||
\return Current status of the SWDIO/TMS DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_SWDIO_TMS_IN (void) {
|
||||
return (XMC_GPIO_GetInput(PIN_SWDIO_IN_PORT, PIN_SWDIO_IN_BIT));
|
||||
}
|
||||
|
||||
/** SWDIO/TMS I/O pin: Set Output to High.
|
||||
Set the SWDIO/TMS DAP hardware I/O pin to high level.
|
||||
*/
|
||||
static __forceinline void PIN_SWDIO_TMS_SET (void) {
|
||||
XMC_GPIO_SetOutputHigh(PIN_SWDIO_OUT_PORT, PIN_SWDIO_OUT_BIT);
|
||||
}
|
||||
|
||||
/** SWDIO/TMS I/O pin: Set Output to Low.
|
||||
Set the SWDIO/TMS DAP hardware I/O pin to low level.
|
||||
*/
|
||||
static __forceinline void PIN_SWDIO_TMS_CLR (void) {
|
||||
XMC_GPIO_SetOutputLow(PIN_SWDIO_OUT_PORT, PIN_SWDIO_OUT_BIT);
|
||||
}
|
||||
|
||||
/** SWDIO I/O pin: Get Input (used in SWD mode only).
|
||||
\return Current status of the SWDIO DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_SWDIO_IN (void) {
|
||||
return (XMC_GPIO_GetInput(PIN_SWDIO_IN_PORT, PIN_SWDIO_IN_BIT));
|
||||
}
|
||||
|
||||
/** SWDIO I/O pin: Set Output (used in SWD mode only).
|
||||
\param bit Output value for the SWDIO DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline void PIN_SWDIO_OUT (uint32_t bit) {
|
||||
if (bit & 0x0001) {
|
||||
XMC_GPIO_SetOutputHigh(PIN_SWDIO_OUT_PORT, PIN_SWDIO_OUT_BIT);
|
||||
} else {
|
||||
XMC_GPIO_SetOutputLow(PIN_SWDIO_OUT_PORT, PIN_SWDIO_OUT_BIT);
|
||||
}
|
||||
}
|
||||
|
||||
/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
|
||||
Configure the SWDIO DAP hardware I/O pin to output mode. This function is
|
||||
called prior \ref PIN_SWDIO_OUT function calls.
|
||||
*/
|
||||
static __forceinline void PIN_SWDIO_OUT_ENABLE (void) {
|
||||
XMC_GPIO_SetOutputHigh(PIN_SWDIO_OE_PORT, PIN_SWDIO_OE_BIT);
|
||||
}
|
||||
|
||||
/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
|
||||
Configure the SWDIO DAP hardware I/O pin to input mode. This function is
|
||||
called prior \ref PIN_SWDIO_IN function calls.
|
||||
*/
|
||||
static __forceinline void PIN_SWDIO_OUT_DISABLE (void) {
|
||||
XMC_GPIO_SetOutputLow(PIN_SWDIO_OE_PORT, PIN_SWDIO_OE_BIT);
|
||||
}
|
||||
|
||||
|
||||
// TDI Pin I/O ---------------------------------------------
|
||||
|
||||
/** TDI I/O pin: Get Input.
|
||||
\return Current status of the TDI DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_TDI_IN (void) {
|
||||
return (0U); // Not available
|
||||
}
|
||||
|
||||
/** TDI I/O pin: Set Output.
|
||||
\param bit Output value for the TDI DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline void PIN_TDI_OUT (uint32_t bit) {
|
||||
// Not available
|
||||
}
|
||||
|
||||
|
||||
// TDO Pin I/O ---------------------------------------------
|
||||
|
||||
/** TDO I/O pin: Get Input.
|
||||
\return Current status of the TDO DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_TDO_IN (void) {
|
||||
return (0U); // Not available
|
||||
}
|
||||
|
||||
|
||||
// nTRST Pin I/O -------------------------------------------
|
||||
|
||||
/** nTRST I/O pin: Get Input.
|
||||
\return Current status of the nTRST DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_nTRST_IN (void) {
|
||||
return (0U); // Not available
|
||||
}
|
||||
|
||||
/** nTRST I/O pin: Set Output.
|
||||
\param bit JTAG TRST Test Reset pin status:
|
||||
- 0: issue a JTAG TRST Test Reset.
|
||||
- 1: release JTAG TRST Test Reset.
|
||||
*/
|
||||
static __forceinline void PIN_nTRST_OUT (uint32_t bit) {
|
||||
; // Not available
|
||||
}
|
||||
|
||||
// nRESET Pin I/O------------------------------------------
|
||||
|
||||
/** nRESET I/O pin: Get Input.
|
||||
\return Current status of the nRESET DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_nRESET_IN (void) {
|
||||
//return (XMC_GPIO_GetInput(PIN_nRESET_PORT, PIN_nRESET_BIT));
|
||||
return (0); // Not available
|
||||
}
|
||||
|
||||
/** nRESET I/O pin: Set Output.
|
||||
\param bit target device hardware reset pin status:
|
||||
- 0: issue a device hardware reset.
|
||||
- 1: release device hardware reset.
|
||||
*/
|
||||
static __forceinline void PIN_nRESET_OUT (uint32_t bit) {
|
||||
if (bit) {
|
||||
XMC_GPIO_SetOutputHigh(PIN_nRESET_PORT, PIN_nRESET_BIT);
|
||||
} else {
|
||||
XMC_GPIO_SetOutputLow(PIN_nRESET_PORT, PIN_nRESET_BIT);
|
||||
}
|
||||
}
|
||||
|
||||
///@}
|
||||
|
||||
|
||||
//**************************************************************************************************
|
||||
/**
|
||||
\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
|
||||
\ingroup DAP_ConfigIO_gr
|
||||
@{
|
||||
|
||||
CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
|
||||
|
||||
It is recommended to provide the following LEDs for status indication:
|
||||
- Connect LED: is active when the DAP hardware is connected to a debugger.
|
||||
- Running LED: is active when the debugger has put the target device into running state.
|
||||
*/
|
||||
|
||||
/** Debug Unit: Set status of Connected LED.
|
||||
\param bit status of the Connect LED.
|
||||
- 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
|
||||
- 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
|
||||
*/
|
||||
static __inline void LED_CONNECTED_OUT (uint32_t bit) {
|
||||
|
||||
if (bit) {
|
||||
XMC_GPIO_SetOutputLow(LED_CONNECTED_PORT, LED_CONNECTED_BIT);
|
||||
} else {
|
||||
XMC_GPIO_SetOutputHigh(LED_CONNECTED_PORT, LED_CONNECTED_BIT);
|
||||
}
|
||||
}
|
||||
|
||||
/** Debug Unit: Set status Target Running LED.
|
||||
\param bit status of the Target Running LED.
|
||||
- 1: Target Running LED ON: program execution in target started.
|
||||
- 0: Target Running LED OFF: program execution in target stopped.
|
||||
*/
|
||||
static __inline void LED_RUNNING_OUT (uint32_t bit) {
|
||||
|
||||
if (bit) {
|
||||
XMC_GPIO_SetOutputLow(LED_RUNNING_PORT, LED_RUNNING_BIT);
|
||||
} else {
|
||||
XMC_GPIO_SetOutputHigh(LED_RUNNING_PORT, LED_RUNNING_BIT);
|
||||
}
|
||||
}
|
||||
|
||||
///@}
|
||||
|
||||
|
||||
//**************************************************************************************************
|
||||
/**
|
||||
\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
|
||||
\ingroup DAP_ConfigIO_gr
|
||||
@{
|
||||
|
||||
CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
|
||||
*/
|
||||
|
||||
/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
|
||||
This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
|
||||
Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
|
||||
- I/O clock system enabled.
|
||||
- all I/O pins: input buffer enabled, output pins are set to HighZ mode.
|
||||
- for nTRST, nRESET a weak pull-up (if available) is enabled.
|
||||
- LED output pins are enabled and LEDs are turned off.
|
||||
*/
|
||||
static __inline void DAP_SETUP (void) {
|
||||
XMC_GPIO_CONFIG_t config;
|
||||
|
||||
/* Enable clock and init GPIO outputs */
|
||||
//LPC_CCU1->CLK_M4_GPIO_CFG = CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN;
|
||||
//while (!(LPC_CCU1->CLK_M4_GPIO_STAT & CCU_CLK_STAT_RUN));
|
||||
|
||||
/* Configure I/O pins: function number, input buffer enabled, */
|
||||
/* no pull-up/down except nRESET (pull-up) */
|
||||
/* SWCLK: Disable Output */
|
||||
//config.mode = XMC_GPIO_MODE_INPUT_TRISTATE; /**< Defines the direction and characteristics of a pin */
|
||||
//configuring SWCLK to tri-state mode does not make sense because the isolation device then has an undefined input
|
||||
config.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL; /**< Defines the direction and characteristics of a pin */
|
||||
config.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH; /**< Defines output level of a pin */
|
||||
config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SHARP_EDGE; /**< Defines pad driver mode of a pin */
|
||||
XMC_GPIO_Init(PIN_SWCLK_TCK_PORT, PIN_SWCLK_TCK_BIT, &config);
|
||||
|
||||
/* SWCLK_IN: Disable Output */
|
||||
config.mode = XMC_GPIO_MODE_INPUT_TRISTATE; /**< Defines the direction and characteristics of a pin */
|
||||
XMC_GPIO_Init(PIN_SWCLK_TCK_IN_PORT, PIN_SWCLK_TCK_IN_BIT, &config);
|
||||
|
||||
/* SWDIO out: Disable Output */
|
||||
//config.mode = XMC_GPIO_MODE_INPUT_TRISTATE; /**< Defines the direction and characteristics of a pin */
|
||||
// onfiguring SWDIO out to tri-state mode does not make sense because the isolation device then has an undefined input
|
||||
config.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL; /**< Defines the direction and characteristics of a pin */
|
||||
config.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH; /**< Defines output level of a pin */
|
||||
config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_WEAK; /**< Defines pad driver mode of a pin */
|
||||
XMC_GPIO_Init(PIN_SWDIO_OUT_PORT, PIN_SWDIO_OUT_BIT, &config);
|
||||
|
||||
/* SWDIO Output Enable: Disable Output */
|
||||
config.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL; /**< Defines the direction and characteristics of a pin */
|
||||
config.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW; /**< Defines output level of a pin */
|
||||
config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_WEAK; /**< Defines pad driver mode of a pin */
|
||||
XMC_GPIO_Init(PIN_SWDIO_OE_PORT, PIN_SWDIO_OE_BIT, &config);
|
||||
|
||||
/* SWDIO in: Enable Input */
|
||||
config.mode = XMC_GPIO_MODE_INPUT_TRISTATE; /**< Defines the direction and characteristics of a pin */
|
||||
XMC_GPIO_Init(PIN_SWDIO_IN_PORT, PIN_SWDIO_IN_BIT, &config);
|
||||
|
||||
/* TDI: Enable I/O */
|
||||
// not available
|
||||
|
||||
/* TDO: Enable I/O */
|
||||
// not available
|
||||
|
||||
/* nTRST: Enable I/O, open-drain, pull-up */
|
||||
// not available
|
||||
|
||||
/* nRESET: Enable I/O, open-drain, pull-up */
|
||||
/* HS: open-drain is not possible with this hardware. I reused the PC_RXD_DEV/TX signal to create the reset */
|
||||
config.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL; /**< Defines the direction and characteristics of a pin */
|
||||
config.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH; /**< Defines output level of a pin */
|
||||
config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_WEAK; /**< Defines pad driver mode of a pin */
|
||||
XMC_GPIO_Init(PIN_nRESET_PORT, PIN_nRESET_BIT, &config);
|
||||
|
||||
/* Configure: Connect LED as output (turned off) */
|
||||
config.mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN; /**< Defines the direction and characteristics of a pin */
|
||||
config.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH; /**< Defines output level of a pin */
|
||||
config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SLOW_EDGE; /**< Defines pad driver mode of a pin */
|
||||
XMC_GPIO_Init(LED_CONNECTED_PORT, LED_CONNECTED_BIT, &config);
|
||||
|
||||
/* Configure: Running LED as output (turned off) */
|
||||
config.mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN; /**< Defines the direction and characteristics of a pin */
|
||||
config.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH; /**< Defines output level of a pin */
|
||||
config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SLOW_EDGE; /**< Defines pad driver mode of a pin */
|
||||
XMC_GPIO_Init(LED_RUNNING_PORT, LED_RUNNING_BIT, &config);
|
||||
|
||||
/* Configure Peripheral Interrupt Priorities */
|
||||
//NVIC_SetPriority(USB0_IRQn, 1U);
|
||||
}
|
||||
|
||||
/** Reset Target Device with custom specific I/O pin or command sequence.
|
||||
This function allows the optional implementation of a device specific reset sequence.
|
||||
It is called when the command \ref DAP_ResetTarget and is for example required
|
||||
when a device needs a time-critical unlock sequence that enables the debug port.
|
||||
\return 0 = no device specific reset sequence is implemented.\n
|
||||
1 = a device specific reset sequence is implemented.
|
||||
*/
|
||||
static __inline uint32_t RESET_TARGET (void) {
|
||||
return (0); // change to '1' when a device reset sequence is implemented
|
||||
}
|
||||
|
||||
///@}
|
||||
|
||||
|
||||
#endif /* __DAP_CONFIG_H__ */
|
||||
@ -0,0 +1,311 @@
|
||||
/*----------------------------------------------------------------------------
|
||||
* CMSIS-RTOS - RTX
|
||||
*----------------------------------------------------------------------------
|
||||
* Name: RTX_Conf_CM.C
|
||||
* Purpose: Configuration of CMSIS RTX Kernel for Cortex-M
|
||||
* Rev.: V4.70.1
|
||||
*----------------------------------------------------------------------------
|
||||
*
|
||||
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
|
||||
* All rights reserved.
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* - Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without
|
||||
* specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#include "cmsis_os.h"
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* RTX User configuration part BEGIN
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
|
||||
//
|
||||
// <h>Thread Configuration
|
||||
// =======================
|
||||
//
|
||||
// <o>Number of concurrent running user threads <1-250>
|
||||
// <i> Defines max. number of user threads that will run at the same time.
|
||||
// <i> Default: 6
|
||||
#ifndef OS_TASKCNT
|
||||
#define OS_TASKCNT 4
|
||||
#endif
|
||||
|
||||
// <o>Default Thread stack size [bytes] <64-4096:8><#/4>
|
||||
// <i> Defines default stack size for threads with osThreadDef stacksz = 0
|
||||
// <i> Default: 200
|
||||
#ifndef OS_STKSIZE
|
||||
#define OS_STKSIZE 64 // this stack size value is in words
|
||||
#endif
|
||||
|
||||
// <o>Main Thread stack size [bytes] <64-32768:8><#/4>
|
||||
// <i> Defines stack size for main thread.
|
||||
// <i> Default: 200
|
||||
#ifndef OS_MAINSTKSIZE
|
||||
#define OS_MAINSTKSIZE 128 // this stack size value is in words
|
||||
#endif
|
||||
|
||||
// <o>Number of threads with user-provided stack size <0-250>
|
||||
// <i> Defines the number of threads with user-provided stack size.
|
||||
// <i> Default: 0
|
||||
#ifndef OS_PRIVCNT
|
||||
#define OS_PRIVCNT 3
|
||||
#endif
|
||||
|
||||
// <o>Total stack size [bytes] for threads with user-provided stack size <0-1048576:8><#/4>
|
||||
// <i> Defines the combined stack size for threads with user-provided stack size.
|
||||
// <i> Default: 0
|
||||
#ifndef OS_PRIVSTKSIZE
|
||||
#define OS_PRIVSTKSIZE 384 // this stack size value is in words
|
||||
#endif
|
||||
|
||||
// <q>Stack overflow checking
|
||||
// <i> Enable stack overflow checks at thread switch.
|
||||
// <i> Enabling this option increases slightly the execution time of a thread switch.
|
||||
#ifndef OS_STKCHECK
|
||||
#define OS_STKCHECK 1
|
||||
#endif
|
||||
|
||||
// <q>Stack usage watermark
|
||||
// <i> Initialize thread stack with watermark pattern for analyzing stack usage (current/maximum) in System and Thread Viewer.
|
||||
// <i> Enabling this option increases significantly the execution time of osThreadCreate.
|
||||
#ifndef OS_STKINIT
|
||||
#define OS_STKINIT 1
|
||||
#endif
|
||||
|
||||
// <o>Processor mode for thread execution
|
||||
// <0=> Unprivileged mode
|
||||
// <1=> Privileged mode
|
||||
// <i> Default: Privileged mode
|
||||
#ifndef OS_RUNPRIV
|
||||
#define OS_RUNPRIV 1
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>RTX Kernel Timer Tick Configuration
|
||||
// ======================================
|
||||
// <q> Use Cortex-M SysTick timer as RTX Kernel Timer
|
||||
// <i> Cortex-M processors provide in most cases a SysTick timer that can be used as
|
||||
// <i> as time-base for RTX.
|
||||
#ifndef OS_SYSTICK
|
||||
#define OS_SYSTICK 1
|
||||
#endif
|
||||
//
|
||||
// <o>RTOS Kernel Timer input clock frequency [Hz] <1-1000000000>
|
||||
// <i> Defines the input frequency of the RTOS Kernel Timer.
|
||||
// <i> When the Cortex-M SysTick timer is used, the input clock
|
||||
// <i> is on most systems identical with the core clock.
|
||||
#ifndef OS_CLOCK
|
||||
#define OS_CLOCK 80000000
|
||||
#endif
|
||||
|
||||
// <o>RTX Timer tick interval value [us] <1-1000000>
|
||||
// <i> The RTX Timer tick interval value is used to calculate timeout values.
|
||||
// <i> When the Cortex-M SysTick timer is enabled, the value also configures the SysTick timer.
|
||||
// <i> Default: 1000 (1ms)
|
||||
#ifndef OS_TICK
|
||||
#define OS_TICK 1000
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>System Configuration
|
||||
// =======================
|
||||
//
|
||||
// <e>Round-Robin Thread switching
|
||||
// ===============================
|
||||
//
|
||||
// <i> Enables Round-Robin Thread switching.
|
||||
#ifndef OS_ROBIN
|
||||
#define OS_ROBIN 1
|
||||
#endif
|
||||
|
||||
// <o>Round-Robin Timeout [ticks] <1-1000>
|
||||
// <i> Defines how long a thread will execute before a thread switch.
|
||||
// <i> Default: 5
|
||||
#ifndef OS_ROBINTOUT
|
||||
#define OS_ROBINTOUT 5
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e>User Timers
|
||||
// ==============
|
||||
// <i> Enables user Timers
|
||||
#ifndef OS_TIMERS
|
||||
#define OS_TIMERS 1
|
||||
#endif
|
||||
|
||||
// <o>Timer Thread Priority
|
||||
// <1=> Low
|
||||
// <2=> Below Normal <3=> Normal <4=> Above Normal
|
||||
// <5=> High
|
||||
// <6=> Realtime (highest)
|
||||
// <i> Defines priority for Timer Thread
|
||||
// <i> Default: High
|
||||
#ifndef OS_TIMERPRIO
|
||||
#define OS_TIMERPRIO 5
|
||||
#endif
|
||||
|
||||
// <o>Timer Thread stack size [bytes] <64-4096:8><#/4>
|
||||
// <i> Defines stack size for Timer thread.
|
||||
// <i> Default: 200
|
||||
#ifndef OS_TIMERSTKSZ
|
||||
#define OS_TIMERSTKSZ 128 // this stack size value is in words
|
||||
#endif
|
||||
|
||||
// <o>Timer Callback Queue size <1-32>
|
||||
// <i> Number of concurrent active timer callback functions.
|
||||
// <i> Default: 4
|
||||
#ifndef OS_TIMERCBQS
|
||||
#define OS_TIMERCBQS 4
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <o>ISR FIFO Queue size<4=> 4 entries <8=> 8 entries
|
||||
// <12=> 12 entries <16=> 16 entries
|
||||
// <24=> 24 entries <32=> 32 entries
|
||||
// <48=> 48 entries <64=> 64 entries
|
||||
// <96=> 96 entries
|
||||
// <i> ISR functions store requests to this buffer,
|
||||
// <i> when they are called from the interrupt handler.
|
||||
// <i> Default: 16 entries
|
||||
#ifndef OS_FIFOSZ
|
||||
#define OS_FIFOSZ 16
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
//------------- <<< end of configuration section >>> -----------------------
|
||||
|
||||
// Standard library system mutexes
|
||||
// ===============================
|
||||
// Define max. number system mutexes that are used to protect
|
||||
// the arm standard runtime library. For microlib they are not used.
|
||||
#ifndef OS_MUTEXCNT
|
||||
#define OS_MUTEXCNT 8
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* RTX User configuration part END
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Global Functions
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
/*--------------------------- os_idle_demon ---------------------------------*/
|
||||
|
||||
/// \brief The idle demon is running when no other thread is ready to run
|
||||
void os_idle_demon (void) {
|
||||
|
||||
for (;;) {
|
||||
/* HERE: include optional user code to be executed when no thread runs.*/
|
||||
}
|
||||
}
|
||||
|
||||
#if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer
|
||||
|
||||
/*--------------------------- os_tick_init ----------------------------------*/
|
||||
|
||||
/// \brief Initializes an alternative hardware timer as RTX kernel timer
|
||||
/// \return IRQ number of the alternative hardware timer
|
||||
int os_tick_init (void) {
|
||||
return (-1); /* Return IRQ number of timer (0..239) */
|
||||
}
|
||||
|
||||
/*--------------------------- os_tick_val -----------------------------------*/
|
||||
|
||||
/// \brief Get alternative hardware timer's current value (0 .. OS_TRV)
|
||||
/// \return Current value of the alternative hardware timer
|
||||
uint32_t os_tick_val (void) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*--------------------------- os_tick_ovf -----------------------------------*/
|
||||
|
||||
/// \brief Get alternative hardware timer's overflow flag
|
||||
/// \return Overflow flag\n
|
||||
/// - 1 : overflow
|
||||
/// - 0 : no overflow
|
||||
uint32_t os_tick_ovf (void) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*--------------------------- os_tick_irqack --------------------------------*/
|
||||
|
||||
/// \brief Acknowledge alternative hardware timer interrupt
|
||||
void os_tick_irqack (void) {
|
||||
/* ... */
|
||||
}
|
||||
|
||||
#endif // (OS_SYSTICK == 0)
|
||||
|
||||
/*--------------------------- os_error --------------------------------------*/
|
||||
|
||||
/* OS Error Codes */
|
||||
#define OS_ERROR_STACK_OVF 1
|
||||
#define OS_ERROR_FIFO_OVF 2
|
||||
#define OS_ERROR_MBX_OVF 3
|
||||
#define OS_ERROR_TIMER_OVF 4
|
||||
|
||||
extern osThreadId svcThreadGetId (void);
|
||||
|
||||
/// \brief Called when a runtime error is detected
|
||||
/// \param[in] error_code actual error code that has been detected
|
||||
void os_error (uint32_t error_code) {
|
||||
|
||||
/* HERE: include optional code to be executed on runtime error. */
|
||||
switch (error_code) {
|
||||
case OS_ERROR_STACK_OVF:
|
||||
/* Stack overflow detected for the currently running task. */
|
||||
/* Thread can be identified by calling svcThreadGetId(). */
|
||||
break;
|
||||
case OS_ERROR_FIFO_OVF:
|
||||
/* ISR FIFO Queue buffer overflow detected. */
|
||||
break;
|
||||
case OS_ERROR_MBX_OVF:
|
||||
/* Mailbox overflow detected. */
|
||||
break;
|
||||
case OS_ERROR_TIMER_OVF:
|
||||
/* User Timer Callback Queue overflow detected. */
|
||||
break;
|
||||
}
|
||||
for (;;);
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* RTX Configuration Functions
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#include "RTX_CM_lib.h"
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* end of file
|
||||
*---------------------------------------------------------------------------*/
|
||||
@ -0,0 +1,897 @@
|
||||
/*
|
||||
*
|
||||
* Copyright (c) 2015, Infineon Technologies AG
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
|
||||
* following conditions are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
|
||||
* disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
|
||||
* disclaimer in the documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
|
||||
* products derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
|
||||
* Infineon Technologies AG dave@infineon.com).
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file RTE_Device.h
|
||||
* @date 24 July, 2015
|
||||
* @version 1.0.1
|
||||
*
|
||||
* @brief RTE Device Configuration for Infineon XMC4200_Q48
|
||||
*
|
||||
* History
|
||||
*
|
||||
* Version 1.0.1
|
||||
* Fix pin assignment
|
||||
* Version 1.0.0
|
||||
* Initial version
|
||||
*/
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
#ifndef __RTE_DEVICE_H
|
||||
#define __RTE_DEVICE_H
|
||||
|
||||
#include "xmc_device.h"
|
||||
#include "xmc4_gpio_map.h"
|
||||
#include "xmc4_usic_map.h"
|
||||
|
||||
#define NO_FIFO 0
|
||||
#define FIFO_SIZE_2 1
|
||||
#define FIFO_SIZE_4 2
|
||||
#define FIFO_SIZE_8 3
|
||||
#define FIFO_SIZE_16 4
|
||||
#define FIFO_SIZE_32 5
|
||||
#define FIFO_SIZE_64 6
|
||||
|
||||
// <e> UART0 (Universal asynchronous receiver transmitter) [Driver_USART0]
|
||||
// <i> Configuration settings for Driver_USART0 in component ::Drivers:UART
|
||||
#define RTE_UART0 0
|
||||
|
||||
// <o> UART0_TX Pin <0=>P1_5
|
||||
#define RTE_UART0_TX_ID 0
|
||||
#if (RTE_UART0_TX_ID == 0)
|
||||
#define RTE_UART0_TX_PORT P1_5
|
||||
#define RTE_UART0_TX_AF P1_5_AF_U0C0_DOUT0
|
||||
#else
|
||||
#error "Invalid UART0_TX Pin Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> UART0_RX Pin <0=>P1_5 <1=>P1_4
|
||||
#define RTE_UART0_RX_ID 1
|
||||
#if (RTE_UART0_RX_ID == 0)
|
||||
#define RTE_UART0_RX_PORT P1_5
|
||||
#define RTE_UART0_RX_INPUT USIC0_C0_DX0_P1_5
|
||||
#elif (RTE_UART0_RX_ID == 1)
|
||||
#define RTE_UART0_RX_PORT P1_4
|
||||
#define RTE_UART0_RX_INPUT USIC0_C0_DX0_P1_4
|
||||
#else
|
||||
#error "Invalid UART0_RX Pin Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> UART0_RX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
|
||||
#define RTE_UART0_RX_FIFO_SIZE_ID 5
|
||||
#if (RTE_UART0_RX_FIFO_SIZE_ID == 0)
|
||||
#define RTE_UART0_RX_FIFO_SIZE NO_FIFO
|
||||
#define RTE_UART0_RX_FIFO_SIZE_NUM 0
|
||||
#elif (RTE_UART0_RX_FIFO_SIZE_ID == 1)
|
||||
#define RTE_UART0_RX_FIFO_SIZE FIFO_SIZE_2
|
||||
#define RTE_UART0_RX_FIFO_SIZE_NUM 2
|
||||
#elif (RTE_UART0_RX_FIFO_SIZE_ID == 2)
|
||||
#define RTE_UART0_RX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_UART0_RX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_UART0_RX_FIFO_SIZE_ID == 3)
|
||||
#define RTE_UART0_RX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_UART0_RX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_UART0_RX_FIFO_SIZE_ID == 4)
|
||||
#define RTE_UART0_RX_FIFO_SIZE FIFO_SIZE_16
|
||||
#define RTE_UART0_RX_FIFO_SIZE_NUM 16
|
||||
#elif (RTE_UART0_RX_FIFO_SIZE_ID == 5)
|
||||
#define RTE_UART0_RX_FIFO_SIZE FIFO_SIZE_32
|
||||
#define RTE_UART0_RX_FIFO_SIZE_NUM 32
|
||||
#elif (RTE_UART0_RX_FIFO_SIZE_ID == 6)
|
||||
#define RTE_UART0_RX_FIFO_SIZE FIFO_SIZE_64
|
||||
#define RTE_UART0_RX_FIFO_SIZE_NUM 64
|
||||
#else
|
||||
#error "Invalid UART0_RX FIFO SIZE Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> UART0_TX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
|
||||
#define RTE_UART0_TX_FIFO_SIZE_ID 5
|
||||
#if (RTE_UART0_TX_FIFO_SIZE_ID == 0)
|
||||
#define RTE_UART0_TX_FIFO_SIZE NO_FIFO
|
||||
#define RTE_UART0_TX_FIFO_SIZE_NUM 0
|
||||
#elif (RTE_UART0_TX_FIFO_SIZE_ID == 1)
|
||||
#define RTE_UART0_TX_FIFO_SIZE FIFO_SIZE_2
|
||||
#define RTE_UART0_TX_FIFO_SIZE_NUM 2
|
||||
#elif (RTE_UART0_TX_FIFO_SIZE_ID == 2)
|
||||
#define RTE_UART0_TX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_UART0_TX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_UART0_TX_FIFO_SIZE_ID == 3)
|
||||
#define RTE_UART0_TX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_UART0_TX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_UART0_TX_FIFO_SIZE_ID == 4)
|
||||
#define RTE_UART0_TX_FIFO_SIZE FIFO_SIZE_16
|
||||
#define RTE_UART0_TX_FIFO_SIZE_NUM 16
|
||||
#elif (RTE_UART0_TX_FIFO_SIZE_ID == 5)
|
||||
#define RTE_UART0_TX_FIFO_SIZE FIFO_SIZE_32
|
||||
#define RTE_UART0_TX_FIFO_SIZE_NUM 32
|
||||
#elif (RTE_UART0_TX_FIFO_SIZE_ID == 6)
|
||||
#define RTE_UART0_TX_FIFO_SIZE FIFO_SIZE_64
|
||||
#define RTE_UART0_TX_FIFO_SIZE_NUM 64
|
||||
#else
|
||||
#error "Invalid UART0_TX FIFO SIZE Configuration!"
|
||||
#endif
|
||||
//</e>
|
||||
|
||||
// <e> UART1 (Universal asynchronous receiver transmitter) [Driver_USART1]
|
||||
// <i> Configuration settings for Driver_USART1 in component ::Drivers:UART
|
||||
#define RTE_UART1 0
|
||||
|
||||
// <o> UART1_TX Pin <0=>P2_5
|
||||
#define RTE_UART1_TX_ID 0
|
||||
#if (RTE_UART1_TX_ID == 0)
|
||||
#define RTE_UART1_TX_PORT P2_5
|
||||
#define RTE_UART1_TX_AF P2_5_AF_U0C1_DOUT0
|
||||
#else
|
||||
#error "Invalid UART1_TX Pin Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> UART1_RX Pin <0=>P2_2 <1=>P2_5
|
||||
#define RTE_UART1_RX_ID 1
|
||||
#if (RTE_UART1_RX_ID == 0)
|
||||
#define RTE_UART1_RX_PORT P2_2
|
||||
#define RTE_UART1_RX_INPUT USIC0_C1_DX0_P2_2
|
||||
#elif (RTE_UART1_RX_ID == 1)
|
||||
#define RTE_UART1_RX_PORT P2_5
|
||||
#define RTE_UART1_RX_INPUT USIC0_C1_DX0_P2_5
|
||||
#else
|
||||
#error "Invalid UART1_RX Pin Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> UART1_RX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
|
||||
#define RTE_UART1_RX_FIFO_SIZE_ID 2
|
||||
#if (RTE_UART1_RX_FIFO_SIZE_ID == 0)
|
||||
#define RTE_UART1_RX_FIFO_SIZE NO_FIFO
|
||||
#define RTE_UART1_RX_FIFO_SIZE_NUM 0
|
||||
#elif (RTE_UART1_RX_FIFO_SIZE_ID == 1)
|
||||
#define RTE_UART1_RX_FIFO_SIZE FIFO_SIZE_2
|
||||
#define RTE_UART1_RX_FIFO_SIZE_NUM 2
|
||||
#elif (RTE_UART1_RX_FIFO_SIZE_ID == 2)
|
||||
#define RTE_UART1_RX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_UART1_RX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_UART1_RX_FIFO_SIZE_ID == 3)
|
||||
#define RTE_UART1_RX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_UART1_RX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_UART1_RX_FIFO_SIZE_ID == 4)
|
||||
#define RTE_UART1_RX_FIFO_SIZE FIFO_SIZE_16
|
||||
#define RTE_UART1_RX_FIFO_SIZE_NUM 16
|
||||
#elif (RTE_UART1_RX_FIFO_SIZE_ID == 5)
|
||||
#define RTE_UART1_RX_FIFO_SIZE FIFO_SIZE_32
|
||||
#define RTE_UART1_RX_FIFO_SIZE_NUM 32
|
||||
#elif (RTE_UART1_RX_FIFO_SIZE_ID == 6)
|
||||
#define RTE_UART1_RX_FIFO_SIZE FIFO_SIZE_64
|
||||
#define RTE_UART1_RX_FIFO_SIZE_NUM 64
|
||||
#else
|
||||
#error "Invalid UART1_RX FIFO SIZE Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> UART1_TX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
|
||||
#define RTE_UART1_TX_FIFO_SIZE_ID 2
|
||||
#if (RTE_UART1_TX_FIFO_SIZE_ID == 0)
|
||||
#define RTE_UART1_TX_FIFO_SIZE NO_FIFO
|
||||
#define RTE_UART1_TX_FIFO_SIZE_NUM 0
|
||||
#elif (RTE_UART1_TX_FIFO_SIZE_ID == 1)
|
||||
#define RTE_UART1_TX_FIFO_SIZE FIFO_SIZE_2
|
||||
#define RTE_UART1_TX_FIFO_SIZE_NUM 2
|
||||
#elif (RTE_UART1_TX_FIFO_SIZE_ID == 2)
|
||||
#define RTE_UART1_TX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_UART1_TX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_UART1_TX_FIFO_SIZE_ID == 3)
|
||||
#define RTE_UART1_TX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_UART1_TX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_UART1_TX_FIFO_SIZE_ID == 4)
|
||||
#define RTE_UART1_TX_FIFO_SIZE FIFO_SIZE_16
|
||||
#define RTE_UART1_TX_FIFO_SIZE_NUM 16
|
||||
#elif (RTE_UART1_TX_FIFO_SIZE_ID == 5)
|
||||
#define RTE_UART1_TX_FIFO_SIZE FIFO_SIZE_32
|
||||
#define RTE_UART1_TX_FIFO_SIZE_NUM 32
|
||||
#elif (RTE_UART1_TX_FIFO_SIZE_ID == 6)
|
||||
#define RTE_UART1_TX_FIFO_SIZE FIFO_SIZE_64
|
||||
#define RTE_UART1_TX_FIFO_SIZE_NUM 64
|
||||
#else
|
||||
#error "Invalid UART1_TX FIFO SIZE Configuration!"
|
||||
#endif
|
||||
//</e>
|
||||
// <e> UART2 (Universal asynchronous receiver transmitter) [Driver_USART2]
|
||||
// <i> Configuration settings for Driver_USART2 in component ::Drivers:UART
|
||||
#define RTE_UART2 1
|
||||
|
||||
// <o> UART2_TX Pin <0=>P0_5
|
||||
#define RTE_UART2_TX_ID 0
|
||||
#if (RTE_UART2_TX_ID == 0)
|
||||
#define RTE_UART2_TX_PORT P0_5
|
||||
#define RTE_UART2_TX_AF P0_5_AF_U1C0_DOUT0
|
||||
#else
|
||||
#error "Invalid UART2_TX Pin Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> UART2_RX Pin <0=> P0_4 <1=> P0_5
|
||||
#define RTE_UART2_RX_ID 0
|
||||
#if (RTE_UART2_RX_ID == 0)
|
||||
#define RTE_UART2_RX_PORT P0_4
|
||||
#define RTE_UART2_RX_INPUT USIC1_C0_DX0_P0_4
|
||||
#elif (RTE_UART2_RX_ID == 1)
|
||||
#define RTE_UART2_RX_PORT P0_5
|
||||
#define RTE_UART2_RX_INPUT USIC1_C0_DX0_P0_5
|
||||
#else
|
||||
#error "Invalid UART2_RX Pin Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> UART2_RX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
|
||||
#define RTE_UART2_RX_FIFO_SIZE_ID 0
|
||||
#if (RTE_UART2_RX_FIFO_SIZE_ID == 0)
|
||||
#define RTE_UART2_RX_FIFO_SIZE NO_FIFO
|
||||
#define RTE_UART2_RX_FIFO_SIZE_NUM 0
|
||||
#elif (RTE_UART2_RX_FIFO_SIZE_ID == 1)
|
||||
#define RTE_UART2_RX_FIFO_SIZE FIFO_SIZE_2
|
||||
#define RTE_UART2_RX_FIFO_SIZE_NUM 2
|
||||
#elif (RTE_UART2_RX_FIFO_SIZE_ID == 2)
|
||||
#define RTE_UART2_RX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_UART2_RX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_UART2_RX_FIFO_SIZE_ID == 3)
|
||||
#define RTE_UART2_RX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_UART2_RX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_UART2_RX_FIFO_SIZE_ID == 4)
|
||||
#define RTE_UART2_RX_FIFO_SIZE FIFO_SIZE_16
|
||||
#define RTE_UART2_RX_FIFO_SIZE_NUM 16
|
||||
#elif (RTE_UART2_RX_FIFO_SIZE_ID == 5)
|
||||
#define RTE_UART2_RX_FIFO_SIZE FIFO_SIZE_32
|
||||
#define RTE_UART2_RX_FIFO_SIZE_NUM 32
|
||||
#elif (RTE_UART2_RX_FIFO_SIZE_ID == 6)
|
||||
#define RTE_UART2_RX_FIFO_SIZE FIFO_SIZE_64
|
||||
#define RTE_UART2_RX_FIFO_SIZE_NUM 64
|
||||
#else
|
||||
#error "Invalid UART2_RX FIFO SIZE Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> UART2_TX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
|
||||
#define RTE_UART2_TX_FIFO_SIZE_ID 0
|
||||
#if (RTE_UART2_TX_FIFO_SIZE_ID == 0)
|
||||
#define RTE_UART2_TX_FIFO_SIZE NO_FIFO
|
||||
#define RTE_UART2_TX_FIFO_SIZE_NUM 0
|
||||
#elif (RTE_UART2_TX_FIFO_SIZE_ID == 1)
|
||||
#define RTE_UART2_TX_FIFO_SIZE FIFO_SIZE_2
|
||||
#define RTE_UART2_TX_FIFO_SIZE_NUM 2
|
||||
#elif (RTE_UART2_TX_FIFO_SIZE_ID == 2)
|
||||
#define RTE_UART2_TX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_UART2_TX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_UART2_TX_FIFO_SIZE_ID == 3)
|
||||
#define RTE_UART2_TX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_UART2_TX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_UART2_TX_FIFO_SIZE_ID == 4)
|
||||
#define RTE_UART2_TX_FIFO_SIZE FIFO_SIZE_16
|
||||
#define RTE_UART2_TX_FIFO_SIZE_NUM 16
|
||||
#elif (RTE_UART2_TX_FIFO_SIZE_ID == 5)
|
||||
#define RTE_UART2_TX_FIFO_SIZE FIFO_SIZE_32
|
||||
#define RTE_UART2_TX_FIFO_SIZE_NUM 32
|
||||
#elif (RTE_UART2_TX_FIFO_SIZE_ID == 6)
|
||||
#define RTE_UART2_TX_FIFO_SIZE FIFO_SIZE_64
|
||||
#define RTE_UART2_TX_FIFO_SIZE_NUM 64
|
||||
#else
|
||||
#error "Invalid UART2_TX FIFO SIZE Configuration!"
|
||||
#endif
|
||||
//</e>
|
||||
// <e> UART3 (Universal asynchronous receiver transmitter) [Driver_USART3]
|
||||
// <i> Configuration settings for Driver_USART3 in component ::Drivers:UART
|
||||
#define RTE_UART3 0
|
||||
|
||||
// <o> UART3_TX Pin <0=>P0_1
|
||||
#define RTE_UART3_TX_ID 0
|
||||
#if (RTE_UART3_TX_ID == 0)
|
||||
#define RTE_UART3_TX_PORT P0_1
|
||||
#define RTE_UART3_TX_AF P0_1_AF_U1C1_DOUT0
|
||||
#else
|
||||
#error "Invalid UART3_TX Pin Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> UART3_RX Pin <0=>P0_1
|
||||
#define RTE_UART3_RX_ID 0
|
||||
#if (RTE_UART3_RX_ID == 0)
|
||||
#define RTE_UART3_RX_PORT P0_0
|
||||
#define RTE_UART3_RX_INPUT USIC1_C1_DX0_P0_0
|
||||
#else
|
||||
#error "Invalid UART3_RX Pin Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> UART3_RX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
|
||||
#define RTE_UART3_RX_FIFO_SIZE_ID 2
|
||||
#if (RTE_UART3_RX_FIFO_SIZE_ID == 0)
|
||||
#define RTE_UART3_RX_FIFO_SIZE NO_FIFO
|
||||
#define RTE_UART3_RX_FIFO_SIZE_NUM 0
|
||||
#elif (RTE_UART3_RX_FIFO_SIZE_ID == 1)
|
||||
#define RTE_UART3_RX_FIFO_SIZE FIFO_SIZE_2
|
||||
#define RTE_UART3_RX_FIFO_SIZE_NUM 2
|
||||
#elif (RTE_UART3_RX_FIFO_SIZE_ID == 2)
|
||||
#define RTE_UART3_RX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_UART3_RX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_UART3_RX_FIFO_SIZE_ID == 3)
|
||||
#define RTE_UART3_RX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_UART3_RX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_UART3_RX_FIFO_SIZE_ID == 4)
|
||||
#define RTE_UART3_RX_FIFO_SIZE FIFO_SIZE_16
|
||||
#define RTE_UART3_RX_FIFO_SIZE_NUM 16
|
||||
#elif (RTE_UART3_RX_FIFO_SIZE_ID == 5)
|
||||
#define RTE_UART3_RX_FIFO_SIZE FIFO_SIZE_32
|
||||
#define RTE_UART3_RX_FIFO_SIZE_NUM 32
|
||||
#elif (RTE_UART3_RX_FIFO_SIZE_ID == 6)
|
||||
#define RTE_UART3_RX_FIFO_SIZE FIFO_SIZE_64
|
||||
#define RTE_UART3_RX_FIFO_SIZE_NUM 64
|
||||
#else
|
||||
#error "Invalid UART3_RX FIFO SIZE Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> UART3_TX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
|
||||
#define RTE_UART3_TX_FIFO_SIZE_ID 2
|
||||
#if (RTE_UART3_TX_FIFO_SIZE_ID == 0)
|
||||
#define RTE_UART3_TX_FIFO_SIZE NO_FIFO
|
||||
#define RTE_UART3_TX_FIFO_SIZE_NUM 0
|
||||
#elif (RTE_UART3_TX_FIFO_SIZE_ID == 1)
|
||||
#define RTE_UART3_TX_FIFO_SIZE FIFO_SIZE_2
|
||||
#define RTE_UART3_TX_FIFO_SIZE_NUM 2
|
||||
#elif (RTE_UART3_TX_FIFO_SIZE_ID == 2)
|
||||
#define RTE_UART3_TX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_UART3_TX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_UART3_TX_FIFO_SIZE_ID == 3)
|
||||
#define RTE_UART3_TX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_UART3_TX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_UART3_TX_FIFO_SIZE_ID == 4)
|
||||
#define RTE_UART3_TX_FIFO_SIZE FIFO_SIZE_16
|
||||
#define RTE_UART3_TX_FIFO_SIZE_NUM 16
|
||||
#elif (RTE_UART3_TX_FIFO_SIZE_ID == 5)
|
||||
#define RTE_UART3_TX_FIFO_SIZE FIFO_SIZE_32
|
||||
#define RTE_UART3_TX_FIFO_SIZE_NUM 32
|
||||
#elif (RTE_UART3_TX_FIFO_SIZE_ID == 6)
|
||||
#define RTE_UART3_TX_FIFO_SIZE FIFO_SIZE_64
|
||||
#define RTE_UART3_TX_FIFO_SIZE_NUM 64
|
||||
#else
|
||||
#error "Invalid UART3_TX FIFO SIZE Configuration!"
|
||||
#endif
|
||||
|
||||
|
||||
// </e>
|
||||
// <e> SPI0 (Serial peripheral interface) [Driver_SPI0]
|
||||
// <i> Configuration settings for Driver_SPI0 in component ::Drivers:SPI
|
||||
#define RTE_SPI0 0
|
||||
|
||||
// <o> SPI0 TX: MOSI(master) MISO(slave) Pin <0=>P1_5
|
||||
#define RTE_SPI0_TX_ID 0
|
||||
#if (RTE_SPI0_TX_ID == 0)
|
||||
#define RTE_SPI0_TX_PORT P1_5
|
||||
#define RTE_SPI0_TX_AF P1_5_AF_U0C0_DOUT0
|
||||
#else
|
||||
#error "Invalid SPI0_TX Pin Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> SPI0 RX MISO(master) MOSI(slave) Pin <0=>P1_5
|
||||
#define RTE_SPI0_RX_ID 0
|
||||
#if (RTE_SPI0_RX_ID == 0)
|
||||
#define RTE_SPI0_RX_PORT P1_5
|
||||
#define RTE_SPI0_RX_INPUT USIC0_C0_DX0_P1_5
|
||||
#else
|
||||
#error "Invalid SPI0_RX Pin Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> SPI0_CLK OUTPUT Pin <0=>P0_8 <1=>P1_1
|
||||
#define RTE_SPI0_CLK_OUTPUT_ID 0
|
||||
#if (RTE_SPI0_CLK_OUTPUT_ID == 0)
|
||||
#define RTE_SPI0_CLK_OUTPUT_PORT P0_8
|
||||
#define RTE_SPI0_CLK_AF P0_8_AF_U0C0_SCLKOUT
|
||||
#elif (RTE_SPI0_CLK_OUTPUT_ID == 1)
|
||||
#define RTE_SPI0_CLK_OUTPUT_PORT P1_1
|
||||
#define RTE_SPI0_CLK_AF P1_1_AF_U0C0_SCLKOUT
|
||||
#else
|
||||
#error "Invalid SPI0 CLOCK OUTPUT Pin Configuration!"
|
||||
#endif
|
||||
// <h> SPI0_SLAVE SELECT Pins
|
||||
// <e> SLAVE SELECT LINE 0
|
||||
// <i> Enable slave select line 0
|
||||
#define RTE_SPI0_SLAVE_SELECT_LINE0 1
|
||||
// <o> SPI0_SLAVE SELECT LINE 0 Pin <0=>P0_7 <1=>P1_0
|
||||
#define RTE_SPI0_SLAVE_SELECT_LINE_0_ID 1
|
||||
#if (RTE_SPI0_SLAVE_SELECT_LINE_0_ID == 0)
|
||||
#define RTE_SPI0_SLAVE_SELECT_LINE_0_PORT P0_7
|
||||
#define RTE_SPI0_SLAVE_SELECT_LINE_0_AF P0_7_AF_U0C0_SELO0
|
||||
#elif (RTE_SPI0_SLAVE_SELECT_LINE_0_ID == 1)
|
||||
#define RTE_SPI0_SLAVE_SELECT_LINE_0_PORT P1_0
|
||||
#define RTE_SPI0_SLAVE_SELECT_LINE_0_AF P1_0_AF_U0C0_SELO0
|
||||
#else
|
||||
#error "Invalid SPI0 SLAVE SELECT LINE 0 Pin Configuration!"
|
||||
#endif
|
||||
// </e>
|
||||
// <e> SLAVE SELECT LINE 1
|
||||
// <i> Enable slave select line 1
|
||||
#define RTE_SPI0_SLAVE_SELECT_LINE1 1
|
||||
// <o> SPI0_SLAVE SELECT LINE 1 Pin <0=>P1_8
|
||||
#define RTE_SPI0_SLAVE_SELECT_LINE_1_ID 0
|
||||
#if (RTE_SPI0_SLAVE_SELECT_LINE_1_ID == 0)
|
||||
#define RTE_SPI0_SLAVE_SELECT_LINE_1_PORT P1_8
|
||||
#define RTE_SPI0_SLAVE_SELECT_LINE_1_AF P1_8_AF_U0C0_SELO1
|
||||
#else
|
||||
#error "Invalid SPI0 SLAVE SELECT LINE 1 Pin Configuration!"
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
// <e> SLAVE SELECT LINE 2
|
||||
// <i> Enable slave select line 2
|
||||
#define RTE_SPI0_SLAVE_SELECT_LINE2 0
|
||||
#if (RTE_SPI0_SLAVE_SELECT_LINE2 == 1)
|
||||
#error "Invalid SPI0 SLAVE SELECT LINE 2 Pin Configuration!"
|
||||
#endif
|
||||
//</e>
|
||||
// <e> SLAVE SELECT LINE 3
|
||||
// <i> Enable slave select line 3
|
||||
#define RTE_SPI0_SLAVE_SELECT_LINE3 0
|
||||
#if (RTE_SPI0_SLAVE_SELECT_LINE3 == 1)
|
||||
#error "Invalid SPI0 SLAVE SELECT LINE 3 Pin Configuration!"
|
||||
#endif
|
||||
//</e>
|
||||
// <e> SLAVE SELECT LINE 4
|
||||
// <i> Enable slave select line 4
|
||||
#define RTE_SPI0_SLAVE_SELECT_LINE4 0
|
||||
#if (RTE_SPI0_SLAVE_SELECT_LINE4 == 1)
|
||||
#error "Invalid SPI0 SLAVE SELECT LINE 4 Pin Configuration!"
|
||||
#endif
|
||||
//</e>
|
||||
// <e> SLAVE SELECT LINE 5
|
||||
// <i> Enable slave select line 5
|
||||
#define RTE_SPI0_SLAVE_SELECT_LINE5 0
|
||||
#if (RTE_SPI0_SLAVE_SELECT_LINE5 == 1)
|
||||
#error "Invalid SPI0 SLAVE SELECT LINE 5 Pin Configuration!"
|
||||
#endif
|
||||
//</e>
|
||||
// </h>
|
||||
// <o> SPI0_CLK INPUT Pin <0=>P1_1 <1=>P0_8
|
||||
#define RTE_SPI0_CLK_INPUT_ID 0
|
||||
#if (RTE_SPI0_CLK_INPUT_ID == 0)
|
||||
#define RTE_SPI0_CLK_INPUT_PORT P1_1
|
||||
#define RTE_SPI0_CLK_INPUT USIC0_C0_DX1_P1_1
|
||||
#elif (RTE_SPI0_CLK_INPUT_ID == 1)
|
||||
#define RTE_SPI0_CLK_INPUT_PORT P0_8
|
||||
#define RTE_SPI0_CLK_INPUT USIC0_C0_DX1_P0_8
|
||||
#else
|
||||
#error "Invalid SPI0 CLOCK INPUT Pin Configuration!"
|
||||
#endif
|
||||
// <o> RTE_SPI0_SLAVE_SELECT INPUT Pin <0=>P1_0
|
||||
#define RTE_SPI0_SLAVE_SELECT_INPUT_ID 0
|
||||
#if (RTE_SPI0_SLAVE_SELECT_INPUT_ID == 0)
|
||||
#define RTE_SPI0_SLAVE_SELECT_INPUT_PORT P1_0
|
||||
#define RTE_SPI0_SLAVE_SELECT_INPUT USIC0_C0_DX2_P1_0
|
||||
#else
|
||||
#error "Invalid SPI0 SLAVE SELECT INPUT Pin Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> SPI0_RX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
|
||||
#define RTE_SPI0_RX_FIFO_SIZE_ID 2
|
||||
#if (RTE_SPI0_RX_FIFO_SIZE_ID == 0)
|
||||
#define RTE_SPI0_RX_FIFO_SIZE NO_FIFO
|
||||
#define RTE_SPI0_RX_FIFO_SIZE_NUM 0
|
||||
#elif (RTE_SPI0_RX_FIFO_SIZE_ID == 1)
|
||||
#define RTE_SPI0_RX_FIFO_SIZE FIFO_SIZE_2
|
||||
#define RTE_SPI0_RX_FIFO_SIZE_NUM 2
|
||||
#elif (RTE_SPI0_RX_FIFO_SIZE_ID == 2)
|
||||
#define RTE_SPI0_RX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_SPI0_RX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_SPI0_RX_FIFO_SIZE_ID == 3)
|
||||
#define RTE_SPI0_RX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_SPI0_RX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_SPI0_RX_FIFO_SIZE_ID == 4)
|
||||
#define RTE_SPI0_RX_FIFO_SIZE FIFO_SIZE_16
|
||||
#define RTE_SPI0_RX_FIFO_SIZE_NUM 16
|
||||
#elif (RTE_SPI0_RX_FIFO_SIZE_ID == 5)
|
||||
#define RTE_SPI0_RX_FIFO_SIZE FIFO_SIZE_32
|
||||
#define RTE_SPI0_RX_FIFO_SIZE_NUM 32
|
||||
#elif (RTE_SPI0_RX_FIFO_SIZE_ID == 6)
|
||||
#define RTE_SPI0_RX_FIFO_SIZE FIFO_SIZE_64
|
||||
#define RTE_SPI0_RX_FIFO_SIZE_NUM 64
|
||||
#else
|
||||
#error "Invalid SPI0_RX FIFO SIZE Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> SPI0_TX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
|
||||
#define RTE_SPI0_TX_FIFO_SIZE_ID 4
|
||||
#if (RTE_SPI0_TX_FIFO_SIZE_ID == 0)
|
||||
#define RTE_SPI0_TX_FIFO_SIZE NO_FIFO
|
||||
#define RTE_SPI0_TX_FIFO_SIZE_NUM 0
|
||||
#elif (RTE_SPI0_TX_FIFO_SIZE_ID == 1)
|
||||
#define RTE_SPI0_TX_FIFO_SIZE FIFO_SIZE_2
|
||||
#define RTE_SPI0_TX_FIFO_SIZE_NUM 2
|
||||
#elif (RTE_SPI0_TX_FIFO_SIZE_ID == 2)
|
||||
#define RTE_SPI0_TX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_SPI0_TX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_SPI0_TX_FIFO_SIZE_ID == 3)
|
||||
#define RTE_SPI0_TX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_SPI0_TX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_SPI0_TX_FIFO_SIZE_ID == 4)
|
||||
#define RTE_SPI0_TX_FIFO_SIZE FIFO_SIZE_16
|
||||
#define RTE_SPI0_TX_FIFO_SIZE_NUM 16
|
||||
#elif (RTE_SPI0_TX_FIFO_SIZE_ID == 5)
|
||||
#define RTE_SPI0_TX_FIFO_SIZE FIFO_SIZE_32
|
||||
#define RTE_SPI0_TX_FIFO_SIZE_NUM 32
|
||||
#elif (RTE_SPI0_TX_FIFO_SIZE_ID == 6)
|
||||
#define RTE_SPI0_TX_FIFO_SIZE FIFO_SIZE_64
|
||||
#define RTE_SPI0_TX_FIFO_SIZE_NUM 64
|
||||
#else
|
||||
#error "Invalid SPI0_TX FIFO SIZE Configuration!"
|
||||
#endif
|
||||
//</e>
|
||||
|
||||
// <e> SPI1 (Serial peripheral interface) [Driver_SPI1]
|
||||
// <i> Configuration settings for Driver_SPI1 in component ::Drivers:SPI
|
||||
#define RTE_SPI1 0
|
||||
|
||||
// <o> SPI1 TX MOSI(master) MISO(slave) Pin <0=>P2_5
|
||||
#define RTE_SPI1_TX_ID 0
|
||||
#if (RTE_SPI1_TX_ID == 0)
|
||||
#define RTE_SPI1_TX_PORT P2_5
|
||||
#define RTE_SPI1_TX_AF P2_5_AF_U0C1_DOUT0
|
||||
#else
|
||||
#error "Invalid SPI1_TX Pin Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> SPI1 RX MISO(master) MOSI(slave) Pin <0=>P2_2 <1=>P2_5
|
||||
#define RTE_SPI1_RX_ID 1
|
||||
#if (RTE_SPI1_RX_ID == 0)
|
||||
#define RTE_SPI1_RX_PORT P2_2
|
||||
#define RTE_SPI1_RX_INPUT USIC0_C1_DX0_P2_2
|
||||
#elif (RTE_SPI1_RX_ID == 1)
|
||||
#define RTE_SPI1_RX_PORT P2_5
|
||||
#define RTE_SPI1_RX_INPUT USIC0_C1_DX0_P2_5
|
||||
#else
|
||||
#error "Invalid SPI1_RX Pin Configuration!"
|
||||
#endif
|
||||
|
||||
|
||||
// <o> SPI1_CLK OUTPUT Pin <0=>P2_4
|
||||
#define RTE_SPI1_CLK_OUTPUT_ID 0
|
||||
#if (RTE_SPI1_CLK_OUTPUT_ID == 0)
|
||||
#define RTE_SPI1_CLK_OUTPUT_PORT P2_4
|
||||
#define RTE_SPI1_CLK_AF P2_4_AF_U0C1_SCLKOUT
|
||||
#else
|
||||
#error "Invalid SPI1 CLOCK OUTPUT Pin Configuration!"
|
||||
#endif
|
||||
|
||||
// <h> SPI1_SLAVE SELECT Pins
|
||||
// <e> SLAVE SELECT LINE 0
|
||||
// <i> Enable slave select line 0
|
||||
#define RTE_SPI1_SLAVE_SELECT_LINE0 1
|
||||
// <o> SPI1_SLAVE SELECT LINE 0 Pin <0=>P2_3
|
||||
#define RTE_SPI1_SLAVE_SELECT_LINE_0_ID 0
|
||||
#if (RTE_SPI1_SLAVE_SELECT_LINE_0_ID == 0)
|
||||
#define RTE_SPI1_SLAVE_SELECT_LINE_0_PORT P2_3
|
||||
#define RTE_SPI1_SLAVE_SELECT_LINE_0_AF P2_3_AF_U0C1_SELO0
|
||||
#else
|
||||
#error "Invalid SPI1 SLAVE SELECT LINE 0 Pin Configuration!"
|
||||
#endif
|
||||
// </e>
|
||||
// <e> SLAVE SELECT LINE 1
|
||||
// <i> Enable slave select line 1
|
||||
#define RTE_SPI1_SLAVE_SELECT_LINE1 0
|
||||
#if (RTE_SPI1_SLAVE_SELECT_LINE1 == 1)
|
||||
#error "Invalid SPI1 SLAVE SELECT LINE 1 Pin Configuration!"
|
||||
#endif
|
||||
//</e>
|
||||
// <e> SLAVE SELECT LINE 2
|
||||
// <i> Enable slave select line 2
|
||||
#define RTE_SPI1_SLAVE_SELECT_LINE2 0
|
||||
#if (RTE_SPI1_SLAVE_SELECT_LINE2 == 1)
|
||||
#error "Invalid SPI1 SLAVE SELECT LINE 2 Pin Configuration!"
|
||||
#endif
|
||||
//</e>
|
||||
// <e> SLAVE SELECT LINE 3
|
||||
// <i> Enable slave select line 3
|
||||
#define RTE_SPI1_SLAVE_SELECT_LINE3 0
|
||||
#if (RTE_SPI1_SLAVE_SELECT_LINE3 == 1)
|
||||
#error "Invalid SPI1 SLAVE SELECT LINE 3 Pin Configuration!"
|
||||
#endif
|
||||
//</e>
|
||||
// </h>
|
||||
|
||||
// <o> SPI1_CLK INPUT Pin <0=>P2_4
|
||||
#define RTE_SPI1_CLK_INPUT_ID 0
|
||||
#if (RTE_SPI1_CLK_INPUT_ID == 0)
|
||||
#define RTE_SPI1_CLK_INPUT_PORT P2_4
|
||||
#define RTE_SPI1_CLK_INPUT USIC0_C1_DX1_P2_4
|
||||
#else
|
||||
#error "Invalid SPI1 CLOCK INPUT Pin Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> RTE_SPI1_SLAVE_SELECT INPUT Pin <0=>P2_3
|
||||
#define RTE_SPI1_SLAVE_SELECT_INPUT_ID 0
|
||||
#if (RTE_SPI1_SLAVE_SELECT_INPUT_ID == 0)
|
||||
#define RTE_SPI1_SLAVE_SELECT_INPUT_PORT P2_3
|
||||
#define RTE_SPI1_SLAVE_SELECT_INPUT USIC0_C1_DX2_P2_3
|
||||
#else
|
||||
#error "Invalid SPI1 SLAVE SELECT INPUT Pin Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> SPI1_RX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
|
||||
#define RTE_SPI1_RX_FIFO_SIZE_ID 2
|
||||
#if (RTE_SPI1_RX_FIFO_SIZE_ID == 0)
|
||||
#define RTE_SPI1_RX_FIFO_SIZE NO_FIFO
|
||||
#define RTE_SPI1_RX_FIFO_SIZE_NUM 0
|
||||
#elif (RTE_SPI1_RX_FIFO_SIZE_ID == 1)
|
||||
#define RTE_SPI1_RX_FIFO_SIZE FIFO_SIZE_2
|
||||
#define RTE_SPI1_RX_FIFO_SIZE_NUM 2
|
||||
#elif (RTE_SPI1_RX_FIFO_SIZE_ID == 2)
|
||||
#define RTE_SPI1_RX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_SPI1_RX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_SPI1_RX_FIFO_SIZE_ID == 3)
|
||||
#define RTE_SPI1_RX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_SPI1_RX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_SPI1_RX_FIFO_SIZE_ID == 4)
|
||||
#define RTE_SPI1_RX_FIFO_SIZE FIFO_SIZE_16
|
||||
#define RTE_SPI1_RX_FIFO_SIZE_NUM 16
|
||||
#elif (RTE_SPI1_RX_FIFO_SIZE_ID == 5)
|
||||
#define RTE_SPI1_RX_FIFO_SIZE FIFO_SIZE_32
|
||||
#define RTE_SPI1_RX_FIFO_SIZE_NUM 32
|
||||
#elif (RTE_SPI1_RX_FIFO_SIZE_ID == 6)
|
||||
#define RTE_SPI1_RX_FIFO_SIZE FIFO_SIZE_64
|
||||
#define RTE_SPI1_RX_FIFO_SIZE_NUM 64
|
||||
#else
|
||||
#error "Invalid SPI1_RX FIFO SIZE Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> SPI1_TX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
|
||||
#define RTE_SPI1_TX_FIFO_SIZE_ID 2
|
||||
#if (RTE_SPI1_TX_FIFO_SIZE_ID == 0)
|
||||
#define RTE_SPI1_TX_FIFO_SIZE NO_FIFO
|
||||
#define RTE_SPI1_TX_FIFO_SIZE_NUM 0
|
||||
#elif (RTE_SPI1_TX_FIFO_SIZE_ID == 1)
|
||||
#define RTE_SPI1_TX_FIFO_SIZE FIFO_SIZE_2
|
||||
#define RTE_SPI1_TX_FIFO_SIZE_NUM 2
|
||||
#elif (RTE_SPI1_TX_FIFO_SIZE_ID == 2)
|
||||
#define RTE_SPI1_TX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_SPI1_TX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_SPI1_TX_FIFO_SIZE_ID == 3)
|
||||
#define RTE_SPI1_TX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_SPI1_TX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_SPI1_TX_FIFO_SIZE_ID == 4)
|
||||
#define RTE_SPI1_TX_FIFO_SIZE FIFO_SIZE_16
|
||||
#define RTE_SPI1_TX_FIFO_SIZE_NUM 16
|
||||
#elif (RTE_SPI1_TX_FIFO_SIZE_ID == 5)
|
||||
#define RTE_SPI1_TX_FIFO_SIZE FIFO_SIZE_32
|
||||
#define RTE_SPI1_TX_FIFO_SIZE_NUM 32
|
||||
#elif (RTE_SPI1_TX_FIFO_SIZE_ID == 6)
|
||||
#define RTE_SPI1_TX_FIFO_SIZE FIFO_SIZE_64
|
||||
#define RTE_SPI1_TX_FIFO_SIZE_NUM 64
|
||||
#else
|
||||
#error "Invalid SPI1_TX FIFO SIZE Configuration!"
|
||||
#endif
|
||||
//</e>
|
||||
// <e> I2C0 (Inter-Integrated circuit) [Driver_I2C0]
|
||||
// <i> Configuration settings for Driver_I2C0 in component ::Drivers:I2C
|
||||
#define RTE_I2C0 0
|
||||
|
||||
// <o> I2C0_TX Pin <0=>P1_5
|
||||
#define RTE_I2C0_TX_ID 0
|
||||
#if (RTE_I2C0_TX_ID == 0)
|
||||
#define RTE_I2C0_TX_PORT P1_5
|
||||
#define RTE_I2C0_TX_AF P1_5_AF_U0C0_DOUT0
|
||||
#else
|
||||
#error "Invalid I2C0_TX Pin Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> I2C0_RX Pin <0=>P1_5
|
||||
#define RTE_I2C0_RX_ID 0
|
||||
#if (RTE_I2C0_RX_ID == 0)
|
||||
#define RTE_I2C0_RX_PORT P1_5
|
||||
#define RTE_I2C0_RX_INPUT USIC0_C0_DX0_P1_5
|
||||
#else
|
||||
#error "Invalid I2C0_RX Pin Configuration!"
|
||||
#endif
|
||||
// <o> I2C0_CLK OUTPUT Pin <0=>P0_8 <1=>P1_1
|
||||
#define RTE_I2C0_CLK_OUTPUT_ID 1
|
||||
#if (RTE_I2C0_CLK_OUTPUT_ID == 0)
|
||||
#define RTE_I2C0_CLK_OUTPUT_PORT P0_8
|
||||
#define RTE_I2C0_CLK_AF P0_8_AF_U0C0_SCLKOUT
|
||||
#elif (RTE_I2C0_CLK_OUTPUT_ID == 1)
|
||||
#define RTE_I2C0_CLK_OUTPUT_PORT P1_1
|
||||
#define RTE_I2C0_CLK_AF P1_1_AF_U0C0_SCLKOUT
|
||||
#else
|
||||
#error "Invalid I2C0 CLOCK OUTPUT Pin Configuration!"
|
||||
#endif
|
||||
// <o> I2C0_CLK INPUT Pin <0=>P1_1 <1=>P0_8
|
||||
#define RTE_I2C0_CLK_INPUT_ID 1
|
||||
#if (RTE_I2C0_CLK_INPUT_ID == 0)
|
||||
#define RTE_I2C0_CLK_INPUT_PORT P1_1
|
||||
#define RTE_I2C0_CLK_INPUT USIC0_C0_DX1_P1_1
|
||||
#elif (RTE_I2C0_CLK_INPUT_ID == 1)
|
||||
#define RTE_I2C0_CLK_INPUT_PORT P0_8
|
||||
#define RTE_I2C0_CLK_INPUT USIC0_C0_DX1_P0_8
|
||||
#else
|
||||
#error "Invalid I2C0 CLOCK INPUT Pin Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> I2C0_RX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
|
||||
#define RTE_I2C0_RX_FIFO_SIZE_ID 2
|
||||
#if (RTE_I2C0_RX_FIFO_SIZE_ID == 0)
|
||||
#define RTE_I2C0_RX_FIFO_SIZE NO_FIFO
|
||||
#define RTE_I2C0_RX_FIFO_SIZE_NUM 0
|
||||
#elif (RTE_I2C0_RX_FIFO_SIZE_ID == 1)
|
||||
#define RTE_I2C0_RX_FIFO_SIZE FIFO_SIZE_2
|
||||
#define RTE_I2C0_RX_FIFO_SIZE_NUM 2
|
||||
#elif (RTE_I2C0_RX_FIFO_SIZE_ID == 2)
|
||||
#define RTE_I2C0_RX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_I2C0_RX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_I2C0_RX_FIFO_SIZE_ID == 3)
|
||||
#define RTE_I2C0_RX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_I2C0_RX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_I2C0_RX_FIFO_SIZE_ID == 4)
|
||||
#define RTE_I2C0_RX_FIFO_SIZE FIFO_SIZE_16
|
||||
#define RTE_I2C0_RX_FIFO_SIZE_NUM 16
|
||||
#elif (RTE_I2C0_RX_FIFO_SIZE_ID == 5)
|
||||
#define RTE_I2C0_RX_FIFO_SIZE FIFO_SIZE_32
|
||||
#define RTE_I2C0_RX_FIFO_SIZE_NUM 32
|
||||
#elif (RTE_I2C0_RX_FIFO_SIZE_ID == 6)
|
||||
#define RTE_I2C0_RX_FIFO_SIZE FIFO_SIZE_64
|
||||
#define RTE_I2C0_RX_FIFO_SIZE_NUM 64
|
||||
#else
|
||||
#error "Invalid I2C0_RX FIFO SIZE Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> I2C0_TX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
|
||||
#define RTE_I2C0_TX_FIFO_SIZE_ID 2
|
||||
#if (RTE_I2C0_TX_FIFO_SIZE_ID == 0)
|
||||
#define RTE_I2C0_TX_FIFO_SIZE NO_FIFO
|
||||
#define RTE_I2C0_TX_FIFO_SIZE_NUM 0
|
||||
#elif (RTE_I2C0_TX_FIFO_SIZE_ID == 1)
|
||||
#define RTE_I2C0_TX_FIFO_SIZE FIFO_SIZE_2
|
||||
#define RTE_I2C0_TX_FIFO_SIZE_NUM 2
|
||||
#elif (RTE_I2C0_TX_FIFO_SIZE_ID == 2)
|
||||
#define RTE_I2C0_TX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_I2C0_TX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_I2C0_TX_FIFO_SIZE_ID == 3)
|
||||
#define RTE_I2C0_TX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_I2C0_TX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_I2C0_TX_FIFO_SIZE_ID == 4)
|
||||
#define RTE_I2C0_TX_FIFO_SIZE FIFO_SIZE_16
|
||||
#define RTE_I2C0_TX_FIFO_SIZE_NUM 16
|
||||
#elif (RTE_I2C0_TX_FIFO_SIZE_ID == 5)
|
||||
#define RTE_I2C0_TX_FIFO_SIZE FIFO_SIZE_32
|
||||
#define RTE_I2C0_TX_FIFO_SIZE_NUM 32
|
||||
#elif (RTE_I2C0_TX_FIFO_SIZE_ID == 6)
|
||||
#define RTE_I2C0_TX_FIFO_SIZE FIFO_SIZE_64
|
||||
#define RTE_I2C0_TX_FIFO_SIZE_NUM 64
|
||||
#else
|
||||
#error "Invalid I2C0_TX FIFO SIZE Configuration!"
|
||||
#endif
|
||||
|
||||
//</e>
|
||||
|
||||
// <e> I2C1 (Inter-Integrated circuit) [Driver_I2C1]
|
||||
// <i> Configuration settings for Driver_I2C1 in component ::Drivers:I2C
|
||||
#define RTE_I2C1 0
|
||||
|
||||
// <o> I2C1_TX Pin <0=>P2_5
|
||||
#define RTE_I2C1_TX_ID 0
|
||||
#if (RTE_I2C1_TX_ID == 0)
|
||||
#define RTE_I2C1_TX_PORT P2_5
|
||||
#define RTE_I2C1_TX_AF P2_5_AF_U0C1_DOUT0
|
||||
#else
|
||||
#error "Invalid I2C1_TX Pin Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> I2C1_RX Pin <0=>P2_2 <1=>P2_5
|
||||
#define RTE_I2C1_RX_ID 1
|
||||
#if (RTE_I2C1_RX_ID == 0)
|
||||
#define RTE_I2C1_RX_PORT P2_2
|
||||
#define RTE_I2C1_RX_INPUT USIC0_C1_DX0_P2_2
|
||||
#elif (RTE_I2C1_RX_ID == 1)
|
||||
#define RTE_I2C1_RX_PORT P2_5
|
||||
#define RTE_I2C1_RX_INPUT USIC0_C1_DX0_P2_5
|
||||
#else
|
||||
#error "Invalid I2C1_RX Pin Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> I2C1_CLK OUTPUT Pin <0=>P2_4
|
||||
#define RTE_I2C1_CLK_OUTPUT_ID 0
|
||||
#if (RTE_I2C1_CLK_OUTPUT_ID == 0)
|
||||
#define RTE_I2C1_CLK_OUTPUT_PORT P2_4
|
||||
#define RTE_I2C1_CLK_AF P2_4_AF_U0C1_SCLKOUT
|
||||
#else
|
||||
#error "Invalid I2C1 CLOCK OUTPUT Pin Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> I2C1_CLK INPUT Pin <0=>P2_4
|
||||
#define RTE_I2C1_CLK_INPUT_ID 0
|
||||
#if (RTE_I2C1_CLK_INPUT_ID == 0)
|
||||
#define RTE_I2C1_CLK_INPUT_PORT P2_4
|
||||
#define RTE_I2C1_CLK_INPUT USIC0_C1_DX1_P2_4
|
||||
#else
|
||||
#error "Invalid I2C1 CLOCK INPUT Pin Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> I2C1_RX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
|
||||
#define RTE_I2C1_RX_FIFO_SIZE_ID 2
|
||||
#if (RTE_I2C1_RX_FIFO_SIZE_ID == 0)
|
||||
#define RTE_I2C1_RX_FIFO_SIZE NO_FIFO
|
||||
#define RTE_I2C1_RX_FIFO_SIZE_NUM 0
|
||||
#elif (RTE_I2C1_RX_FIFO_SIZE_ID == 1)
|
||||
#define RTE_I2C1_RX_FIFO_SIZE FIFO_SIZE_2
|
||||
#define RTE_I2C1_RX_FIFO_SIZE_NUM 2
|
||||
#elif (RTE_I2C1_RX_FIFO_SIZE_ID == 2)
|
||||
#define RTE_I2C1_RX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_I2C1_RX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_I2C1_RX_FIFO_SIZE_ID == 3)
|
||||
#define RTE_I2C1_RX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_I2C1_RX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_I2C1_RX_FIFO_SIZE_ID == 4)
|
||||
#define RTE_I2C1_RX_FIFO_SIZE FIFO_SIZE_16
|
||||
#define RTE_I2C1_RX_FIFO_SIZE_NUM 16
|
||||
#elif (RTE_I2C1_RX_FIFO_SIZE_ID == 5)
|
||||
#define RTE_I2C1_RX_FIFO_SIZE FIFO_SIZE_32
|
||||
#define RTE_I2C1_RX_FIFO_SIZE_NUM 32
|
||||
#elif (RTE_I2C1_RX_FIFO_SIZE_ID == 6)
|
||||
#define RTE_I2C1_RX_FIFO_SIZE FIFO_SIZE_64
|
||||
#define RTE_I2C1_RX_FIFO_SIZE_NUM 64
|
||||
#else
|
||||
#error "Invalid I2C1_RX FIFO SIZE Configuration!"
|
||||
#endif
|
||||
|
||||
// <o> I2C1_TX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
|
||||
#define RTE_I2C1_TX_FIFO_SIZE_ID 2
|
||||
#if (RTE_I2C1_TX_FIFO_SIZE_ID == 0)
|
||||
#define RTE_I2C1_TX_FIFO_SIZE NO_FIFO
|
||||
#define RTE_I2C1_TX_FIFO_SIZE_NUM 0
|
||||
#elif (RTE_I2C1_TX_FIFO_SIZE_ID == 1)
|
||||
#define RTE_I2C1_TX_FIFO_SIZE FIFO_SIZE_2
|
||||
#define RTE_I2C1_TX_FIFO_SIZE_NUM 2
|
||||
#elif (RTE_I2C1_TX_FIFO_SIZE_ID == 2)
|
||||
#define RTE_I2C1_TX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_I2C1_TX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_I2C1_TX_FIFO_SIZE_ID == 3)
|
||||
#define RTE_I2C1_TX_FIFO_SIZE FIFO_SIZE_4
|
||||
#define RTE_I2C1_TX_FIFO_SIZE_NUM 4
|
||||
#elif (RTE_I2C1_TX_FIFO_SIZE_ID == 4)
|
||||
#define RTE_I2C1_TX_FIFO_SIZE FIFO_SIZE_16
|
||||
#define RTE_I2C1_TX_FIFO_SIZE_NUM 16
|
||||
#elif (RTE_I2C1_TX_FIFO_SIZE_ID == 5)
|
||||
#define RTE_I2C1_TX_FIFO_SIZE FIFO_SIZE_32
|
||||
#define RTE_I2C1_TX_FIFO_SIZE_NUM 32
|
||||
#elif (RTE_I2C1_TX_FIFO_SIZE_ID == 6)
|
||||
#define RTE_I2C1_TX_FIFO_SIZE FIFO_SIZE_64
|
||||
#define RTE_I2C1_TX_FIFO_SIZE_NUM 64
|
||||
#else
|
||||
#error "Invalid I2C1_TX FIFO SIZE Configuration!"
|
||||
#endif
|
||||
//</e>
|
||||
|
||||
#if ((RTE_UART0+RTE_I2C0+RTE_SPI0)>1)
|
||||
#error "Choose just one Driver_I2C/SPI/UART0 driver !"
|
||||
#elif ((RTE_UART1+RTE_I2C1+RTE_SPI1)>1)
|
||||
#error "Choose just one Driver_I2C/SPI/UART1 driver !"
|
||||
#elif ((RTE_UART2+RTE_I2C2+RTE_SPI2)>1)
|
||||
#error "Choose just one Driver_I2C/SPI/UART2 driver !"
|
||||
#elif ((RTE_UART3+RTE_I2C3+RTE_SPI3)>1)
|
||||
#error "Choose just one Driver_I2C/SPI/UART3 driver !"
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __RTE_DEVICE_H */
|
||||
@ -0,0 +1,535 @@
|
||||
;*******************************************************************************
|
||||
;* @file startup_XMC4200.s
|
||||
;* @brief CMSIS Core Device Startup File for
|
||||
;* Infineon XMC4200 Device Series
|
||||
;* @version V1.2
|
||||
;* @date November 2014
|
||||
;*
|
||||
;* Copyright (C) 2014 Infineon Technologies AG. All rights reserved.
|
||||
;*
|
||||
;*
|
||||
;* @par
|
||||
;* Infineon Technologies AG (Infineon) is supplying this software for use with
|
||||
;* Infineon's microcontrollers. This file can be freely distributed
|
||||
;* within development tools that are supporting such microcontrollers.
|
||||
;*
|
||||
;* @par
|
||||
;* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
;* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
;* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
;* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
;* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
;*
|
||||
;******************************************************************************
|
||||
|
||||
;************************** Version History ************************************
|
||||
; V0.1, September 2012, First version
|
||||
; V1.0, February 2013, FIX for CPU prefetch bug implemented
|
||||
; V1.1, August 2013, Fix the bug of stack pointer alignment to a 8 byte boundary
|
||||
; V1.2, November 2014, Disable CPU workaround. Increased stack size.
|
||||
; Removed DAVE3 dependency
|
||||
;*******************************************************************************
|
||||
|
||||
; ------------------ <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000800
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
IF :DEF:ENABLE_CPU_CM_001_WORKAROUND
|
||||
MACRO
|
||||
Entry $Handler
|
||||
DCD $Handler._Veneer
|
||||
MEND
|
||||
ELSE
|
||||
MACRO
|
||||
Entry $Handler
|
||||
DCD $Handler
|
||||
MEND
|
||||
ENDIF
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; 0 Top of Stack
|
||||
DCD Reset_Handler ; 1 Reset Handler
|
||||
Entry NMI_Handler ; 2 NMI Handler
|
||||
Entry HardFault_Handler ; 3 Hard Fault Handler
|
||||
Entry MemManage_Handler ; 4 MPU Fault Handler
|
||||
Entry BusFault_Handler ; 5 Bus Fault Handler
|
||||
Entry UsageFault_Handler ; 6 Usage Fault Handler
|
||||
DCD 0 ; 7 Reserved
|
||||
DCD 0 ; 8 Reserved
|
||||
DCD 0 ; 9 Reserved
|
||||
DCD 0 ; 10 Reserved
|
||||
Entry SVC_Handler ; 11 SVCall Handler
|
||||
Entry DebugMon_Handler ; 12 Debug Monitor Handler
|
||||
DCD 0 ; 13 Reserved
|
||||
Entry PendSV_Handler ; 14 PendSV Handler
|
||||
Entry SysTick_Handler ; 15 SysTick Handler
|
||||
|
||||
; Interrupt Handlers for Service Requests (SR) from XMC4200 Peripherals */
|
||||
Entry SCU_0_IRQHandler ; Handler name for SR SCU_0
|
||||
Entry ERU0_0_IRQHandler ; Handler name for SR ERU0_0
|
||||
Entry ERU0_1_IRQHandler ; Handler name for SR ERU0_1
|
||||
Entry ERU0_2_IRQHandler ; Handler name for SR ERU0_2
|
||||
Entry ERU0_3_IRQHandler ; Handler name for SR ERU0_3
|
||||
Entry ERU1_0_IRQHandler ; Handler name for SR ERU1_0
|
||||
Entry ERU1_1_IRQHandler ; Handler name for SR ERU1_1
|
||||
Entry ERU1_2_IRQHandler ; Handler name for SR ERU1_2
|
||||
Entry ERU1_3_IRQHandler ; Handler name for SR ERU1_3
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
Entry PMU0_0_IRQHandler ; Handler name for SR PMU0_0
|
||||
DCD 0 ; Not Available
|
||||
Entry VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0
|
||||
Entry VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1
|
||||
Entry VADC0_C0_2_IRQHandler ; Handler name for SR VADC0_C0_1
|
||||
Entry VADC0_C0_3_IRQHandler ; Handler name for SR VADC0_C0_3
|
||||
Entry VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0
|
||||
Entry VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1
|
||||
Entry VADC0_G0_2_IRQHandler ; Handler name for SR VADC0_G0_2
|
||||
Entry VADC0_G0_3_IRQHandler ; Handler name for SR VADC0_G0_3
|
||||
Entry VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0
|
||||
Entry VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1
|
||||
Entry VADC0_G1_2_IRQHandler ; Handler name for SR VADC0_G1_2
|
||||
Entry VADC0_G1_3_IRQHandler ; Handler name for SR VADC0_G1_3
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
Entry DAC0_0_IRQHandler ; Handler name for SR DAC0_0
|
||||
Entry DAC0_1_IRQHandler ; Handler name for SR DAC0_1
|
||||
Entry CCU40_0_IRQHandler ; Handler name for SR CCU40_0
|
||||
Entry CCU40_1_IRQHandler ; Handler name for SR CCU40_1
|
||||
Entry CCU40_2_IRQHandler ; Handler name for SR CCU40_2
|
||||
Entry CCU40_3_IRQHandler ; Handler name for SR CCU40_3
|
||||
Entry CCU41_0_IRQHandler ; Handler name for SR CCU41_0
|
||||
Entry CCU41_1_IRQHandler ; Handler name for SR CCU41_1
|
||||
Entry CCU41_2_IRQHandler ; Handler name for SR CCU41_2
|
||||
Entry CCU41_3_IRQHandler ; Handler name for SR CCU41_3
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
Entry CCU80_0_IRQHandler ; Handler name for SR CCU80_0
|
||||
Entry CCU80_1_IRQHandler ; Handler name for SR CCU80_1
|
||||
Entry CCU80_2_IRQHandler ; Handler name for SR CCU80_2
|
||||
Entry CCU80_3_IRQHandler ; Handler name for SR CCU80_3
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
Entry POSIF0_0_IRQHandler ; Handler name for SR POSIF0_0
|
||||
Entry POSIF0_1_IRQHandler ; Handler name for SR POSIF0_1
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
Entry HRPWM_0_IRQHandler ; Handler name for SR HRPWM_0
|
||||
Entry HRPWM_1_IRQHandler ; Handler name for SR HRPWM_1
|
||||
Entry HRPWM_2_IRQHandler ; Handler name for SR HRPWM_2
|
||||
Entry HRPWM_3_IRQHandler ; Handler name for SR HRPWM_3
|
||||
Entry CAN0_0_IRQHandler ; Handler name for SR CAN0_0
|
||||
Entry CAN0_1_IRQHandler ; Handler name for SR CAN0_1
|
||||
Entry CAN0_2_IRQHandler ; Handler name for SR CAN0_2
|
||||
Entry CAN0_3_IRQHandler ; Handler name for SR CAN0_3
|
||||
Entry CAN0_4_IRQHandler ; Handler name for SR CAN0_4
|
||||
Entry CAN0_5_IRQHandler ; Handler name for SR CAN0_5
|
||||
Entry CAN0_6_IRQHandler ; Handler name for SR CAN0_6
|
||||
Entry CAN0_7_IRQHandler ; Handler name for SR CAN0_7
|
||||
Entry USIC0_0_IRQHandler ; Handler name for SR USIC0_0
|
||||
Entry USIC0_1_IRQHandler ; Handler name for SR USIC0_1
|
||||
Entry USIC0_2_IRQHandler ; Handler name for SR USIC0_2
|
||||
Entry USIC0_3_IRQHandler ; Handler name for SR USIC0_3
|
||||
Entry USIC0_4_IRQHandler ; Handler name for SR USIC0_4
|
||||
Entry USIC0_5_IRQHandler ; Handler name for SR USIC0_5
|
||||
Entry USIC1_0_IRQHandler ; Handler name for SR USIC1_0
|
||||
Entry USIC1_1_IRQHandler ; Handler name for SR USIC1_1
|
||||
Entry USIC1_2_IRQHandler ; Handler name for SR USIC1_2
|
||||
Entry USIC1_3_IRQHandler ; Handler name for SR USIC1_3
|
||||
Entry USIC1_4_IRQHandler ; Handler name for SR USIC1_4
|
||||
Entry USIC1_5_IRQHandler ; Handler name for SR USIC1_5
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
Entry LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0
|
||||
DCD 0 ; Not Available
|
||||
Entry FCE0_0_IRQHandler ; Handler name for SR FCE0_0
|
||||
Entry GPDMA0_0_IRQHandler ; Handler name for SR GPDMA0_0
|
||||
DCD 0 ; Not Available
|
||||
Entry USB0_0_IRQHandler ; Handler name for SR USB0_0
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR SP, =__initial_sp
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
|
||||
EXPORT SCU_0_IRQHandler [WEAK]
|
||||
EXPORT ERU0_0_IRQHandler [WEAK]
|
||||
EXPORT ERU0_1_IRQHandler [WEAK]
|
||||
EXPORT ERU0_2_IRQHandler [WEAK]
|
||||
EXPORT ERU0_3_IRQHandler [WEAK]
|
||||
EXPORT ERU1_0_IRQHandler [WEAK]
|
||||
EXPORT ERU1_1_IRQHandler [WEAK]
|
||||
EXPORT ERU1_2_IRQHandler [WEAK]
|
||||
EXPORT ERU1_3_IRQHandler [WEAK]
|
||||
EXPORT PMU0_0_IRQHandler [WEAK]
|
||||
EXPORT VADC0_C0_0_IRQHandler [WEAK]
|
||||
EXPORT VADC0_C0_1_IRQHandler [WEAK]
|
||||
EXPORT VADC0_C0_2_IRQHandler [WEAK]
|
||||
EXPORT VADC0_C0_3_IRQHandler [WEAK]
|
||||
EXPORT VADC0_G0_0_IRQHandler [WEAK]
|
||||
EXPORT VADC0_G0_1_IRQHandler [WEAK]
|
||||
EXPORT VADC0_G0_2_IRQHandler [WEAK]
|
||||
EXPORT VADC0_G0_3_IRQHandler [WEAK]
|
||||
EXPORT VADC0_G1_0_IRQHandler [WEAK]
|
||||
EXPORT VADC0_G1_1_IRQHandler [WEAK]
|
||||
EXPORT VADC0_G1_2_IRQHandler [WEAK]
|
||||
EXPORT VADC0_G1_3_IRQHandler [WEAK]
|
||||
EXPORT DSD0_0_IRQHandler [WEAK]
|
||||
EXPORT DSD0_1_IRQHandler [WEAK]
|
||||
EXPORT DSD0_2_IRQHandler [WEAK]
|
||||
EXPORT DSD0_3_IRQHandler [WEAK]
|
||||
EXPORT DSD0_4_IRQHandler [WEAK]
|
||||
EXPORT DSD0_5_IRQHandler [WEAK]
|
||||
EXPORT DSD0_6_IRQHandler [WEAK]
|
||||
EXPORT DSD0_7_IRQHandler [WEAK]
|
||||
EXPORT DAC0_0_IRQHandler [WEAK]
|
||||
EXPORT DAC0_1_IRQHandler [WEAK]
|
||||
EXPORT CCU40_0_IRQHandler [WEAK]
|
||||
EXPORT CCU40_1_IRQHandler [WEAK]
|
||||
EXPORT CCU40_2_IRQHandler [WEAK]
|
||||
EXPORT CCU40_3_IRQHandler [WEAK]
|
||||
EXPORT CCU41_0_IRQHandler [WEAK]
|
||||
EXPORT CCU41_1_IRQHandler [WEAK]
|
||||
EXPORT CCU41_2_IRQHandler [WEAK]
|
||||
EXPORT CCU41_3_IRQHandler [WEAK]
|
||||
EXPORT CCU80_0_IRQHandler [WEAK]
|
||||
EXPORT CCU80_1_IRQHandler [WEAK]
|
||||
EXPORT CCU80_2_IRQHandler [WEAK]
|
||||
EXPORT CCU80_3_IRQHandler [WEAK]
|
||||
EXPORT POSIF0_0_IRQHandler [WEAK]
|
||||
EXPORT POSIF0_1_IRQHandler [WEAK]
|
||||
EXPORT HRPWM_0_IRQHandler [WEAK]
|
||||
EXPORT HRPWM_1_IRQHandler [WEAK]
|
||||
EXPORT HRPWM_2_IRQHandler [WEAK]
|
||||
EXPORT HRPWM_3_IRQHandler [WEAK]
|
||||
EXPORT CAN0_0_IRQHandler [WEAK]
|
||||
EXPORT CAN0_1_IRQHandler [WEAK]
|
||||
EXPORT CAN0_2_IRQHandler [WEAK]
|
||||
EXPORT CAN0_3_IRQHandler [WEAK]
|
||||
EXPORT CAN0_4_IRQHandler [WEAK]
|
||||
EXPORT CAN0_5_IRQHandler [WEAK]
|
||||
EXPORT CAN0_6_IRQHandler [WEAK]
|
||||
EXPORT CAN0_7_IRQHandler [WEAK]
|
||||
EXPORT USIC0_0_IRQHandler [WEAK]
|
||||
EXPORT USIC0_1_IRQHandler [WEAK]
|
||||
EXPORT USIC0_2_IRQHandler [WEAK]
|
||||
EXPORT USIC0_3_IRQHandler [WEAK]
|
||||
EXPORT USIC0_4_IRQHandler [WEAK]
|
||||
EXPORT USIC0_5_IRQHandler [WEAK]
|
||||
EXPORT USIC1_0_IRQHandler [WEAK]
|
||||
EXPORT USIC1_1_IRQHandler [WEAK]
|
||||
EXPORT USIC1_2_IRQHandler [WEAK]
|
||||
EXPORT USIC1_3_IRQHandler [WEAK]
|
||||
EXPORT USIC1_4_IRQHandler [WEAK]
|
||||
EXPORT USIC1_5_IRQHandler [WEAK]
|
||||
EXPORT LEDTS0_0_IRQHandler [WEAK]
|
||||
EXPORT FCE0_0_IRQHandler [WEAK]
|
||||
EXPORT GPDMA0_0_IRQHandler [WEAK]
|
||||
EXPORT USB0_0_IRQHandler [WEAK]
|
||||
|
||||
NMI_Handler
|
||||
HardFault_Handler
|
||||
MemManage_Handler
|
||||
BusFault_Handler
|
||||
UsageFault_Handler
|
||||
SVC_Handler
|
||||
DebugMon_Handler
|
||||
PendSV_Handler
|
||||
SysTick_Handler
|
||||
SCU_0_IRQHandler
|
||||
ERU0_0_IRQHandler
|
||||
ERU0_1_IRQHandler
|
||||
ERU0_2_IRQHandler
|
||||
ERU0_3_IRQHandler
|
||||
ERU1_0_IRQHandler
|
||||
ERU1_1_IRQHandler
|
||||
ERU1_2_IRQHandler
|
||||
ERU1_3_IRQHandler
|
||||
PMU0_0_IRQHandler
|
||||
VADC0_C0_0_IRQHandler
|
||||
VADC0_C0_1_IRQHandler
|
||||
VADC0_C0_2_IRQHandler
|
||||
VADC0_C0_3_IRQHandler
|
||||
VADC0_G0_0_IRQHandler
|
||||
VADC0_G0_1_IRQHandler
|
||||
VADC0_G0_2_IRQHandler
|
||||
VADC0_G0_3_IRQHandler
|
||||
VADC0_G1_0_IRQHandler
|
||||
VADC0_G1_1_IRQHandler
|
||||
VADC0_G1_2_IRQHandler
|
||||
VADC0_G1_3_IRQHandler
|
||||
DSD0_0_IRQHandler
|
||||
DSD0_1_IRQHandler
|
||||
DSD0_2_IRQHandler
|
||||
DSD0_3_IRQHandler
|
||||
DSD0_4_IRQHandler
|
||||
DSD0_5_IRQHandler
|
||||
DSD0_6_IRQHandler
|
||||
DSD0_7_IRQHandler
|
||||
DAC0_0_IRQHandler
|
||||
DAC0_1_IRQHandler
|
||||
CCU40_0_IRQHandler
|
||||
CCU40_1_IRQHandler
|
||||
CCU40_2_IRQHandler
|
||||
CCU40_3_IRQHandler
|
||||
CCU41_0_IRQHandler
|
||||
CCU41_1_IRQHandler
|
||||
CCU41_2_IRQHandler
|
||||
CCU41_3_IRQHandler
|
||||
CCU80_0_IRQHandler
|
||||
CCU80_1_IRQHandler
|
||||
CCU80_2_IRQHandler
|
||||
CCU80_3_IRQHandler
|
||||
POSIF0_0_IRQHandler
|
||||
POSIF0_1_IRQHandler
|
||||
HRPWM_0_IRQHandler
|
||||
HRPWM_1_IRQHandler
|
||||
HRPWM_2_IRQHandler
|
||||
HRPWM_3_IRQHandler
|
||||
CAN0_0_IRQHandler
|
||||
CAN0_1_IRQHandler
|
||||
CAN0_2_IRQHandler
|
||||
CAN0_3_IRQHandler
|
||||
CAN0_4_IRQHandler
|
||||
CAN0_5_IRQHandler
|
||||
CAN0_6_IRQHandler
|
||||
CAN0_7_IRQHandler
|
||||
USIC0_0_IRQHandler
|
||||
USIC0_1_IRQHandler
|
||||
USIC0_2_IRQHandler
|
||||
USIC0_3_IRQHandler
|
||||
USIC0_4_IRQHandler
|
||||
USIC0_5_IRQHandler
|
||||
USIC1_0_IRQHandler
|
||||
USIC1_1_IRQHandler
|
||||
USIC1_2_IRQHandler
|
||||
USIC1_3_IRQHandler
|
||||
USIC1_4_IRQHandler
|
||||
USIC1_5_IRQHandler
|
||||
LEDTS0_0_IRQHandler
|
||||
FCE0_0_IRQHandler
|
||||
GPDMA0_0_IRQHandler
|
||||
USB0_0_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
IF :DEF:ENABLE_CPU_CM_001_WORKAROUND
|
||||
|
||||
MACRO
|
||||
Insert_ExceptionHandlerVeneer $Handler_Func
|
||||
$Handler_Func._Veneer\
|
||||
PROC
|
||||
EXPORT $Handler_Func._Veneer
|
||||
LDR R0, =$Handler_Func
|
||||
PUSH {LR} ;/* Breaks AAPCS */
|
||||
SUB SP,#4 ;/* Restores AAPCS */
|
||||
BLX R0
|
||||
ADD SP,#4
|
||||
POP {PC}
|
||||
ALIGN
|
||||
LTORG
|
||||
ENDP
|
||||
MEND
|
||||
|
||||
Insert_ExceptionHandlerVeneer NMI_Handler
|
||||
Insert_ExceptionHandlerVeneer HardFault_Handler
|
||||
Insert_ExceptionHandlerVeneer MemManage_Handler
|
||||
Insert_ExceptionHandlerVeneer BusFault_Handler
|
||||
Insert_ExceptionHandlerVeneer UsageFault_Handler
|
||||
Insert_ExceptionHandlerVeneer SVC_Handler
|
||||
Insert_ExceptionHandlerVeneer DebugMon_Handler
|
||||
Insert_ExceptionHandlerVeneer PendSV_Handler
|
||||
Insert_ExceptionHandlerVeneer SysTick_Handler
|
||||
|
||||
Insert_ExceptionHandlerVeneer SCU_0_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer ERU0_0_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer ERU0_1_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer ERU0_2_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer ERU0_3_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer ERU1_0_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer ERU1_1_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer ERU1_2_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer ERU1_3_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer PMU0_0_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer VADC0_C0_0_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer VADC0_C0_1_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer VADC0_C0_2_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer VADC0_C0_3_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer VADC0_G0_0_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer VADC0_G0_1_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer VADC0_G0_2_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer VADC0_G0_3_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer VADC0_G1_0_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer VADC0_G1_1_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer VADC0_G1_2_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer VADC0_G1_3_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer DSD0_0_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer DSD0_1_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer DSD0_2_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer DSD0_3_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer DSD0_4_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer DSD0_5_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer DSD0_6_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer DSD0_7_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer DAC0_0_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer DAC0_1_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer CCU40_0_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer CCU40_1_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer CCU40_2_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer CCU40_3_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer CCU41_0_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer CCU41_1_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer CCU41_2_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer CCU41_3_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer CCU80_0_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer CCU80_1_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer CCU80_2_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer CCU80_3_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer POSIF0_0_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer POSIF0_1_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer HRPWM_0_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer HRPWM_1_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer HRPWM_2_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer HRPWM_3_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer CAN0_0_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer CAN0_1_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer CAN0_2_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer CAN0_3_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer CAN0_4_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer CAN0_5_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer CAN0_6_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer CAN0_7_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer USIC0_0_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer USIC0_1_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer USIC0_2_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer USIC0_3_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer USIC0_4_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer USIC0_5_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer USIC1_0_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer USIC1_1_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer USIC1_2_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer USIC1_3_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer USIC1_4_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer USIC1_5_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer LEDTS0_0_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer FCE0_0_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer GPDMA0_0_IRQHandler
|
||||
Insert_ExceptionHandlerVeneer USB0_0_IRQHandler
|
||||
ENDIF
|
||||
|
||||
ALIGN
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
@ -0,0 +1,649 @@
|
||||
/******************************************************************************
|
||||
* @file system_XMC4200.c
|
||||
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File
|
||||
* for the Infineon XMC4200 Device Series
|
||||
* @version V3.1.0
|
||||
* @date 20. Dec 2014
|
||||
*
|
||||
* Copyright (C) 2014 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
* @par
|
||||
* Infineon Technologies AG (Infineon) is supplying this software for use with
|
||||
* Infineon's microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such microcontrollers.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/********************** Version History ***************************************
|
||||
* V3.1.0, Dec 2014, Added options to configure clock settings
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* HEADER FILES
|
||||
*******************************************************************************/
|
||||
#include <string.h>
|
||||
|
||||
#include <XMC4200.h>
|
||||
#include "system_XMC4200.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* MACROS
|
||||
*******************************************************************************/
|
||||
|
||||
#define CHIPID_LOC ((uint8_t *)0x20000000UL)
|
||||
#define HRPWM_CHARDATA_LOC ((uint8_t *)0x20000084UL)
|
||||
/* Define WEAK attribute */
|
||||
#if !defined(__WEAK)
|
||||
#if defined ( __CC_ARM )
|
||||
#define __WEAK __attribute__ ((weak))
|
||||
#elif defined ( __ICCARM__ )
|
||||
#define __WEAK __weak
|
||||
#elif defined ( __GNUC__ )
|
||||
#define __WEAK __attribute__ ((weak))
|
||||
#elif defined ( __TASKING__ )
|
||||
#define __WEAK __attribute__ ((weak))
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define PMU_FLASH_WS (0x2U)
|
||||
#define FPLL_FREQUENCY (80000000U)
|
||||
#define FOSCREF (2500000U)
|
||||
#define DELAY_CNT_50US_50MHZ (2500UL)
|
||||
#define DELAY_CNT_150US_50MHZ (7500UL)
|
||||
#define DELAY_CNT_50US_60MHZ (3000UL)
|
||||
#define DELAY_CNT_50US_80MHZ (4000UL)
|
||||
|
||||
#define SCU_PLL_PLLSTAT_OSC_USABLE (SCU_PLL_PLLSTAT_PLLHV_Msk | \
|
||||
SCU_PLL_PLLSTAT_PLLLV_Msk | \
|
||||
SCU_PLL_PLLSTAT_PLLSP_Msk)
|
||||
|
||||
/*
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
// <h> Clock configuration
|
||||
*/
|
||||
|
||||
/*
|
||||
// <o> External crystal frequency [Hz]
|
||||
// <8000000=> 8MHz
|
||||
// <12000000=> 12MHz
|
||||
// <16000000=> 16MHz
|
||||
// <i> Defines external crystal frequency
|
||||
// <i> Default: 8MHz
|
||||
*/
|
||||
#define OSCHP_FREQUENCY (12000000U)
|
||||
|
||||
#if OSCHP_FREQUENCY == 8000000U
|
||||
#define USB_PDIV (1U)
|
||||
#define USB_NDIV (95U)
|
||||
#define USB_DIV (3U)
|
||||
|
||||
#elif OSCHP_FREQUENCY == 12000000U
|
||||
#define USB_PDIV (1U)
|
||||
#define USB_NDIV (63U)
|
||||
#define USB_DIV (3U)
|
||||
|
||||
#elif OSCHP_FREQUENCY == 16000000U
|
||||
#define USB_PDIV (1U)
|
||||
#define USB_NDIV (47U)
|
||||
#define USB_DIV (3U)
|
||||
|
||||
#else
|
||||
#error "External crystal frequency not supported"
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
// <o> System clock (fSYS) source selection
|
||||
// <0=> Backup clock (24MHz)
|
||||
// <1=> Maximum clock frequency using PLL (80MHz)
|
||||
// <i> Default: Maximum clock frequency using PLL (80MHz)
|
||||
*/
|
||||
#define SYS_CLOCK_SRC 1
|
||||
#define SYS_CLOCK_SRC_OFI 0
|
||||
#define SYS_CLOCK_SRC_PLL 1
|
||||
|
||||
/*
|
||||
// <o> Backup clock calibration mode
|
||||
// <0=> Factory calibration
|
||||
// <1=> Automatic calibration
|
||||
// <i> Default: Automatic calibration
|
||||
*/
|
||||
#define FOFI_CALIBRATION_MODE 1
|
||||
#define FOFI_CALIBRATION_MODE_FACTORY 0
|
||||
#define FOFI_CALIBRATION_MODE_AUTOMATIC 1
|
||||
|
||||
/*
|
||||
// <o> Standby clock (fSTDBY) source selection
|
||||
// <0=> Internal slow oscillator (32768Hz)
|
||||
// <1=> External crystal (32768Hz)
|
||||
// <i> Default: Internal slow oscillator (32768Hz)
|
||||
*/
|
||||
#define STDBY_CLOCK_SRC 0
|
||||
#define STDBY_CLOCK_SRC_OSI 0
|
||||
#define STDBY_CLOCK_SRC_OSCULP 1
|
||||
|
||||
/*
|
||||
// <o> PLL clock source selection
|
||||
// <0=> External crystal
|
||||
// <1=> External direct input
|
||||
// <2=> Internal fast oscillator
|
||||
// <i> Default: External crystal
|
||||
*/
|
||||
#define PLL_CLOCK_SRC 0
|
||||
#define PLL_CLOCK_SRC_EXT_XTAL 0
|
||||
#define PLL_CLOCK_SRC_EXT_DIRECT 1
|
||||
#define PLL_CLOCK_SRC_OFI 2
|
||||
|
||||
#if PLL_CLOCK_SRC == PLL_CLOCK_SRC_EXT_XTAL
|
||||
#if OSCHP_FREQUENCY == 8000000U
|
||||
#define PLL_PDIV (1U)
|
||||
#define PLL_NDIV (79U)
|
||||
#define PLL_K2DIV (3U)
|
||||
|
||||
#elif OSCHP_FREQUENCY == 12000000U
|
||||
#define PLL_PDIV (2U)
|
||||
#define PLL_NDIV (79U)
|
||||
#define PLL_K2DIV (3U)
|
||||
|
||||
#elif OSCHP_FREQUENCY == 16000000U
|
||||
#define PLL_PDIV (1U)
|
||||
#define PLL_NDIV (39U)
|
||||
#define PLL_K2DIV (3U)
|
||||
|
||||
#else
|
||||
#error "External crystal frequency not supported"
|
||||
|
||||
#endif
|
||||
|
||||
#define VCO ((OSCHP_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL))
|
||||
#else /* PLL_CLOCK_SRC == PLL_CLOCK_SRC_EXT_XTAL */
|
||||
#define PLL_PDIV (5U)
|
||||
#define PLL_NDIV (79U)
|
||||
#define PLL_K2DIV (3U)
|
||||
|
||||
#define VCO ((OFI_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL))
|
||||
#endif /* PLL_CLOCK_SRC == PLL_CLOCK_SRC_OFI */
|
||||
|
||||
#define PLL_K2DIV_0 ((VCO / OFI_FREQUENCY) - 1UL)
|
||||
#define PLL_K2DIV_1 ((VCO / 60000000U) - 1UL)
|
||||
|
||||
#define SCU_CLK_CLKCLR_ENABLE_USBCLK SCU_CLK_CLKCLR_USBCDI_Msk
|
||||
#define SCU_CLK_CLKCLR_ENABLE_CCUCLK SCU_CLK_CLKCLR_CCUCDI_Msk
|
||||
#define SCU_CLK_CLKCLR_ENABLE_WDTCLK SCU_CLK_CLKCLR_WDTCDI_Msk
|
||||
|
||||
#define SCU_CLK_USBCLKCR_USBSEL_USBPLL (0U << SCU_CLK_USBCLKCR_USBSEL_Pos)
|
||||
#define SCU_CLK_USBCLKCR_USBSEL_PLL (1U << SCU_CLK_USBCLKCR_USBSEL_Pos)
|
||||
|
||||
#define SCU_CLK_WDTCLKCR_WDTSEL_OFI (0U << SCU_CLK_WDTCLKCR_WDTSEL_Pos)
|
||||
#define SCU_CLK_WDTCLKCR_WDTSEL_STANDBY (1U << SCU_CLK_WDTCLKCR_WDTSEL_Pos)
|
||||
#define SCU_CLK_WDTCLKCR_WDTSEL_PLL (2U << SCU_CLK_WDTCLKCR_WDTSEL_Pos)
|
||||
|
||||
#define SCU_CLK_EXTCLKCR_ECKSEL_SYS (0U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
|
||||
#define SCU_CLK_EXTCLKCR_ECKSEL_USBPLL (2U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
|
||||
#define SCU_CLK_EXTCLKCR_ECKSEL_PLL (3U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
|
||||
#define SCU_CLK_EXTCLKCR_ECKSEL_STANDBY (4U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
|
||||
|
||||
#define EXTCLK_PIN_P0_8 (0)
|
||||
#define EXTCLK_PIN_P1_15 (1)
|
||||
|
||||
/*
|
||||
// <h> Clock tree
|
||||
// <o1.0> CPU clock divider
|
||||
// <0=> fCPU = fSYS
|
||||
// <1=> fCPU = fSYS / 2
|
||||
// <o2.0> Peripheral clock divider
|
||||
// <0=> fPB = fCPU
|
||||
// <1=> fPB = fCPU / 2
|
||||
// <e.4> Enable CCU clock
|
||||
// <o3.0> CCU clock divider
|
||||
// <0=> fCCU = fCPU
|
||||
// <1=> fCCU = fCPU / 2
|
||||
// </e>
|
||||
// <e.5> Enable WDT clock
|
||||
// <o4.0..7> WDT clock divider <1-256><#-1>
|
||||
// <o4.16..17> WDT clock source <0=> fOFI
|
||||
// <1=> fSTDBY
|
||||
// <2=> fPLL
|
||||
// </e>
|
||||
// <e.0> Enable USB clock
|
||||
// <o5.16> USB clock source <0=> USBPLL
|
||||
// <1=> PLL
|
||||
// </e>
|
||||
// <e6> External Clock configuration
|
||||
// <o7.0..2> External clock source selection
|
||||
// <0=> System clock
|
||||
// <2=> USB PLL clock
|
||||
// <3=> PLL clock
|
||||
// <4=> Standby clock
|
||||
// <o7.16..24> External clock divider <1-512><#-1>
|
||||
// <i> Only valid for USB PLL and PLL clocks
|
||||
// <o8.0> External Pin Selection
|
||||
// <0=> P0.8
|
||||
// <1=> P1.15
|
||||
// </e>
|
||||
// </h>
|
||||
*/
|
||||
#define ENABLE_SCUCLK (0U)
|
||||
#define CPUCLKDIV (0U)
|
||||
#define PBCLKDIV (0U)
|
||||
#define CCUCLKDIV (0U)
|
||||
#define WDTCLKDIV (0U | SCU_CLK_WDTCLKCR_WDTSEL_OFI)
|
||||
#define USBCLKDIV (0U | SCU_CLK_USBCLKCR_USBSEL_USBPLL | USB_DIV)
|
||||
|
||||
#define ENABLE_EXTCLK (0U)
|
||||
#define EXTCLKDIV (0U | SCU_CLK_EXTCLKCR_ECKSEL_SYS)
|
||||
#define EXTCLK_PIN (0U)
|
||||
|
||||
#define ENABLE_PLL \
|
||||
(SYS_CLOCK_SRC == SYS_CLOCK_SRC_PLL) || \
|
||||
(((ENABLE_SCUCLK & SCU_CLK_CLKSET_USBCEN_Msk) != 0) && ((USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_PLL)) || \
|
||||
(((ENABLE_SCUCLK & SCU_CLK_CLKSET_WDTCEN_Msk) != 0) && ((WDTCLKDIV & SCU_CLK_WDTCLKCR_WDTSEL_Msk) == SCU_CLK_WDTCLKCR_WDTSEL_PLL))
|
||||
|
||||
/*
|
||||
// </h>
|
||||
*/
|
||||
|
||||
/*
|
||||
//-------- <<< end of configuration section >>> ------------------
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* GLOBAL VARIABLES
|
||||
*******************************************************************************/
|
||||
#if defined ( __CC_ARM )
|
||||
uint32_t SystemCoreClock __attribute__((at(0x20005FC0)));
|
||||
uint8_t g_chipid[16] __attribute__((at(0x20005FC4)));
|
||||
uint32_t g_hrpwm_char_data[3] __attribute__((at(0x20005FD4)));
|
||||
#elif defined ( __ICCARM__ )
|
||||
__no_init uint32_t SystemCoreClock;
|
||||
__no_init uint8_t g_chipid[16];
|
||||
__no_init uint32_t g_hrpwm_char_data[3];
|
||||
#elif defined ( __GNUC__ )
|
||||
uint32_t SystemCoreClock __attribute__((section(".no_init")));
|
||||
uint8_t g_chipid[16] __attribute__((section(".no_init")));
|
||||
uint32_t g_hrpwm_char_data[3] __attribute__((section(".no_init")));
|
||||
#elif defined ( __TASKING__ )
|
||||
uint32_t SystemCoreClock __at( 0x20005FC0 );
|
||||
uint8_t g_chipid[16] __at( 0x20005FC4 );
|
||||
uint32_t g_hrpwm_char_data[3] __at( 0x20005FD4 );
|
||||
#endif
|
||||
|
||||
extern uint32_t __Vectors;
|
||||
|
||||
/*******************************************************************************
|
||||
* LOCAL FUNCTIONS
|
||||
*******************************************************************************/
|
||||
static void delay(uint32_t cycles)
|
||||
{
|
||||
volatile uint32_t i;
|
||||
|
||||
for(i = 0UL; i < cycles ;++i)
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* API IMPLEMENTATION
|
||||
*******************************************************************************/
|
||||
|
||||
__WEAK void SystemInit(void)
|
||||
{
|
||||
memcpy(g_chipid, CHIPID_LOC, 16);
|
||||
memcpy(g_hrpwm_char_data, HRPWM_CHARDATA_LOC, 12);
|
||||
|
||||
SystemCoreSetup();
|
||||
SystemCoreClockSetup();
|
||||
}
|
||||
|
||||
__WEAK void SystemCoreSetup(void)
|
||||
{
|
||||
uint32_t temp;
|
||||
|
||||
/* relocate vector table */
|
||||
__disable_irq();
|
||||
SCB->VTOR = (uint32_t)(&__Vectors);
|
||||
__DSB();
|
||||
__enable_irq();
|
||||
|
||||
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
|
||||
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
|
||||
(3UL << 11*2) ); /* set CP11 Full Access */
|
||||
#endif
|
||||
|
||||
/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */
|
||||
SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);
|
||||
|
||||
temp = FLASH0->FCON;
|
||||
temp &= ~FLASH_FCON_WSPFLASH_Msk;
|
||||
temp |= PMU_FLASH_WS;
|
||||
FLASH0->FCON = temp;
|
||||
}
|
||||
|
||||
__WEAK void SystemCoreClockSetup(void)
|
||||
{
|
||||
#if FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_FACTORY
|
||||
/* Enable factory calibration */
|
||||
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FOTR_Msk;
|
||||
#else
|
||||
/* Automatic calibration uses the fSTDBY */
|
||||
|
||||
/* Enable HIB domain */
|
||||
/* Power up HIB domain if and only if it is currently powered down */
|
||||
if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
|
||||
{
|
||||
SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk;
|
||||
|
||||
while((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
|
||||
{
|
||||
/* wait until HIB domain is enabled */
|
||||
}
|
||||
}
|
||||
|
||||
/* Remove the reset only if HIB domain were in a state of reset */
|
||||
if((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_HIBRS_Msk)
|
||||
{
|
||||
SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk;
|
||||
delay(DELAY_CNT_150US_50MHZ);
|
||||
}
|
||||
|
||||
#if STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP
|
||||
/* Enable OSC_ULP */
|
||||
if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk) != 0UL)
|
||||
{
|
||||
/*enable OSC_ULP*/
|
||||
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk)
|
||||
{
|
||||
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
|
||||
}
|
||||
SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk;
|
||||
|
||||
/* Check if the clock is OK using OSCULP Oscillator Watchdog*/
|
||||
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk)
|
||||
{
|
||||
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
|
||||
}
|
||||
SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;
|
||||
|
||||
/* wait till clock is stable */
|
||||
do
|
||||
{
|
||||
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk)
|
||||
{
|
||||
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
|
||||
}
|
||||
SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
|
||||
|
||||
delay(DELAY_CNT_50US_50MHZ);
|
||||
|
||||
} while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk) != 0UL);
|
||||
|
||||
}
|
||||
|
||||
/* now OSC_ULP is running and can be used*/
|
||||
/* Select OSC_ULP as the clock source for RTC and STDBY*/
|
||||
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk)
|
||||
{
|
||||
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
|
||||
}
|
||||
SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk | SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
|
||||
|
||||
#endif /* STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP */
|
||||
|
||||
/* Enable automatic calibration of internal fast oscillator */
|
||||
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
|
||||
#endif /* FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_AUTOMATIC */
|
||||
|
||||
delay(DELAY_CNT_50US_50MHZ);
|
||||
|
||||
#if ENABLE_PLL
|
||||
|
||||
/* enable PLL */
|
||||
SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
|
||||
|
||||
#if PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI
|
||||
/* enable OSC_HP */
|
||||
if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U)
|
||||
{
|
||||
SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Pos);
|
||||
SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) << SCU_OSC_OSCHPCTRL_OSCVAL_Pos;
|
||||
|
||||
/* select OSC_HP clock as PLL input */
|
||||
SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
|
||||
|
||||
/* restart OSC Watchdog */
|
||||
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
|
||||
|
||||
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE)
|
||||
{
|
||||
/* wait till OSC_HP output frequency is usable */
|
||||
}
|
||||
}
|
||||
#else /* PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI */
|
||||
|
||||
/* select backup clock as PLL input */
|
||||
SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
|
||||
#endif
|
||||
|
||||
/* Go to bypass the Main PLL */
|
||||
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;
|
||||
|
||||
/* disconnect Oscillator from PLL */
|
||||
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;
|
||||
|
||||
/* Setup divider settings for main PLL */
|
||||
SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
|
||||
(PLL_K2DIV_0 << SCU_PLL_PLLCON1_K2DIV_Pos) |
|
||||
(PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
|
||||
|
||||
/* Set OSCDISCDIS */
|
||||
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
|
||||
|
||||
/* connect Oscillator to PLL */
|
||||
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;
|
||||
|
||||
/* restart PLL Lock detection */
|
||||
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;
|
||||
|
||||
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U)
|
||||
{
|
||||
/* wait for PLL Lock */
|
||||
}
|
||||
|
||||
/* Disable bypass- put PLL clock back */
|
||||
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
|
||||
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOBYST_Msk) != 0U)
|
||||
{
|
||||
/* wait for normal mode */
|
||||
}
|
||||
#endif /* ENABLE_PLL */
|
||||
|
||||
#if (SYS_CLOCK_SRC == SYS_CLOCK_SRC_PLL)
|
||||
/* Switch system clock to PLL */
|
||||
SCU_CLK->SYSCLKCR |= SCU_CLK_SYSCLKCR_SYSSEL_Msk;
|
||||
#else
|
||||
/* Switch system clock to backup clock */
|
||||
SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk;
|
||||
#endif
|
||||
|
||||
/* Before scaling to final frequency we need to setup the clock dividers */
|
||||
SCU_CLK->PBCLKCR = PBCLKDIV;
|
||||
SCU_CLK->CPUCLKCR = CPUCLKDIV;
|
||||
SCU_CLK->CCUCLKCR = CCUCLKDIV;
|
||||
SCU_CLK->WDTCLKCR = WDTCLKDIV;
|
||||
SCU_CLK->USBCLKCR = USBCLKDIV;
|
||||
|
||||
#if ENABLE_PLL
|
||||
/* PLL frequency stepping...*/
|
||||
/* Reset OSCDISCDIS */
|
||||
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
|
||||
|
||||
SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
|
||||
(PLL_K2DIV_1 << SCU_PLL_PLLCON1_K2DIV_Pos) |
|
||||
(PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
|
||||
|
||||
|
||||
delay(DELAY_CNT_50US_60MHZ);
|
||||
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U)
|
||||
{
|
||||
/* wait for PLL Lock */
|
||||
}
|
||||
|
||||
SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
|
||||
(PLL_K2DIV << SCU_PLL_PLLCON1_K2DIV_Pos) |
|
||||
(PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
|
||||
|
||||
|
||||
delay(DELAY_CNT_50US_80MHZ);
|
||||
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U)
|
||||
{
|
||||
/* wait for PLL Lock */
|
||||
}
|
||||
|
||||
SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;
|
||||
#endif /* ENABLE_PLL */
|
||||
|
||||
#if (((ENABLE_SCUCLK & SCU_CLK_CLKSET_USBCEN_Msk) != 0) && ((USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_USBPLL))
|
||||
/* enable USB PLL first */
|
||||
SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);
|
||||
|
||||
/* USB PLL uses as clock input the OSC_HP */
|
||||
/* check and if not already running enable OSC_HP */
|
||||
if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U)
|
||||
{
|
||||
/* check if Main PLL is switched on for OSC WDG*/
|
||||
if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0UL)
|
||||
{
|
||||
/* enable PLL first */
|
||||
SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
|
||||
}
|
||||
|
||||
SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Pos);
|
||||
SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) << SCU_OSC_OSCHPCTRL_OSCVAL_Pos;
|
||||
|
||||
/* restart OSC Watchdog */
|
||||
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
|
||||
|
||||
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE)
|
||||
{
|
||||
/* wait till OSC_HP output frequency is usable */
|
||||
}
|
||||
}
|
||||
|
||||
/* Setup USB PLL */
|
||||
/* Go to bypass the USB PLL */
|
||||
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;
|
||||
|
||||
/* disconnect Oscillator from USB PLL */
|
||||
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;
|
||||
|
||||
/* Setup Divider settings for USB PLL */
|
||||
SCU_PLL->USBPLLCON = ((USB_NDIV << SCU_PLL_USBPLLCON_NDIV_Pos) |
|
||||
(USB_PDIV << SCU_PLL_USBPLLCON_PDIV_Pos));
|
||||
|
||||
/* Set OSCDISCDIS */
|
||||
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;
|
||||
|
||||
/* connect Oscillator to USB PLL */
|
||||
SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;
|
||||
|
||||
/* restart PLL Lock detection */
|
||||
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;
|
||||
|
||||
while ((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk) == 0U)
|
||||
{
|
||||
/* wait for PLL Lock */
|
||||
}
|
||||
#endif /* (USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) */
|
||||
|
||||
/* Enable selected clocks */
|
||||
SCU_CLK->CLKSET = ENABLE_SCUCLK;
|
||||
|
||||
#if ENABLE_EXTCLK == 1
|
||||
/* Configure external clock */
|
||||
SCU_CLK->EXTCLKCR = EXTCLKDIV;
|
||||
|
||||
#if EXTCLK_PIN == EXTCLK_PIN_P1_15
|
||||
/* P1.15 */
|
||||
PORT1->PDR1 &= ~PORT1_PDR1_PD15_Msk;
|
||||
PORT1->IOCR12 = (PORT1->IOCR12 & ~PORT0_IOCR12_PC15_Msk) | (0x11U << PORT0_IOCR12_PC15_Pos);
|
||||
#else
|
||||
/* P0.8 */
|
||||
PORT0->HWSEL &= ~PORT0_HWSEL_HW8_Msk;
|
||||
PORT0->PDR1 &= ~PORT0_PDR1_PD8_Msk;
|
||||
PORT0->IOCR8 = (PORT0->IOCR8 & ~PORT0_IOCR8_PC8_Msk) | (0x11U << PORT0_IOCR8_PC8_Pos);
|
||||
#endif
|
||||
|
||||
#endif /* ENABLE_EXTCLK == 1 */
|
||||
|
||||
SystemCoreClockUpdate();
|
||||
}
|
||||
|
||||
__WEAK void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t pdiv;
|
||||
uint32_t ndiv;
|
||||
uint32_t kdiv;
|
||||
uint32_t temp;
|
||||
|
||||
if (SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk)
|
||||
{
|
||||
/* fPLL is clock source for fSYS */
|
||||
if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk)
|
||||
{
|
||||
/* PLL input clock is the backup clock (fOFI) */
|
||||
temp = OFI_FREQUENCY;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* PLL input clock is the high performance osicllator (fOSCHP) */
|
||||
temp = OSCHP_GetFrequency();
|
||||
}
|
||||
|
||||
/* check if PLL is locked */
|
||||
if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)
|
||||
{
|
||||
/* PLL normal mode */
|
||||
/* read back divider settings */
|
||||
pdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk) >> SCU_PLL_PLLCON1_PDIV_Pos) + 1;
|
||||
ndiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk) >> SCU_PLL_PLLCON1_NDIV_Pos) + 1;
|
||||
kdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk) >> SCU_PLL_PLLCON1_K2DIV_Pos) + 1;
|
||||
|
||||
temp = (temp / (pdiv * kdiv)) * ndiv;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* PLL prescalar mode */
|
||||
/* read back divider settings */
|
||||
kdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K1DIV_Msk) >> SCU_PLL_PLLCON1_K1DIV_Pos) + 1;
|
||||
|
||||
temp = (temp / kdiv);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* fOFI is clock source for fSYS */
|
||||
temp = OFI_FREQUENCY;
|
||||
}
|
||||
|
||||
temp = temp / ((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk) + 1);
|
||||
temp = temp / ((SCU_CLK->CPUCLKCR & SCU_CLK_CPUCLKCR_CPUDIV_Msk) + 1);
|
||||
|
||||
SystemCoreClock = temp;
|
||||
}
|
||||
|
||||
__WEAK uint32_t OSCHP_GetFrequency(void)
|
||||
{
|
||||
return OSCHP_FREQUENCY;
|
||||
}
|
||||
@ -0,0 +1,25 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Component Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'CMSIS_DAP'
|
||||
* Target: 'XMC4200'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
#define RTE_CMSIS_RTOS /* CMSIS-RTOS */
|
||||
#define RTE_CMSIS_RTOS_RTX /* CMSIS-RTOS Keil RTX */
|
||||
#define RTE_DEVICE
|
||||
#define RTE_DEVICE_STARTUP
|
||||
#define RTE_DEVICE_XMCLIB_GPIO
|
||||
#define RTE_DEVICE_XMCLIB_SCU
|
||||
#define RTE_DEVICE_XMCLIB_UART
|
||||
#define RTE_Drivers_USBD
|
||||
#define RTE_USB_Core /* USB Core */
|
||||
#define RTE_USB_Device_0 /* USB Device 0 */
|
||||
#define RTE_USB_Device_HID_0 /* USB Device HID instance 0 */
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@ -0,0 +1,171 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
* MDK Middleware - Component ::USB:Device
|
||||
* Copyright (c) 2004-2014 ARM Germany GmbH. All rights reserved.
|
||||
*------------------------------------------------------------------------------
|
||||
* Name: USBD_Config_0.c
|
||||
* Purpose: USB Device Configuration
|
||||
* Rev.: V5.00
|
||||
*------------------------------------------------------------------------------
|
||||
* Use the following configuration settings in the Device Class configuration
|
||||
* files to assign a Device Class to this USB Device 0.
|
||||
*
|
||||
* Configuration Setting Value
|
||||
* --------------------- -----
|
||||
* Assign Device Class to USB Device # = 0
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <h>USB Device 0
|
||||
// <o>Connect to hardware via Driver_USBD# <0-255>
|
||||
// <i>Select driver control block for hardware interface.
|
||||
#define USBD0_PORT 0
|
||||
|
||||
// <o.0>High-speed
|
||||
// <i>Enable High-speed functionality (if device supports it).
|
||||
#define USBD0_HS 0
|
||||
|
||||
// <h>Device Settings
|
||||
// <i>These settings are used to create the Device Descriptor
|
||||
// <o>Max Endpoint 0 Packet Size
|
||||
// <i>Maximum packet size for Endpoint 0 (bMaxPacketSize0).
|
||||
// <8=>8 Bytes <16=>16 Bytes <32=>32 Bytes <64=>64 Bytes
|
||||
#define USBD0_MAX_PACKET0 64
|
||||
|
||||
// <o.0..15>Vendor ID <0x0000-0xFFFF>
|
||||
// <i>Vendor ID assigned by USB-IF (idVendor).
|
||||
#define USBD0_DEV_DESC_IDVENDOR 0xC251
|
||||
|
||||
// <o.0..15>Product ID <0x0000-0xFFFF>
|
||||
// <i>Product ID assigned by manufacturer (idProduct).
|
||||
#define USBD0_DEV_DESC_IDPRODUCT 0xF008
|
||||
|
||||
// <o.0..15>Device Release Number <0x0000-0xFFFF>
|
||||
// <i>Device Release Number in binary-coded decimal (bcdDevice)
|
||||
#define USBD0_DEV_DESC_BCDDEVICE 0x0100
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Configuration Settings
|
||||
// <i>These settings are used to create the Configuration Descriptor.
|
||||
// <o.6>Power
|
||||
// <i>Default Power Setting (D6: of bmAttributes).
|
||||
// <0=>Bus-powered
|
||||
// <1=>Self-powered
|
||||
// <o.5>Remote Wakeup
|
||||
// <i>Configuration support for Remote Wakeup (D5: of bmAttributes).
|
||||
#define USBD0_CFG_DESC_BMATTRIBUTES 0x80
|
||||
|
||||
// <o.0..7>Maximum Power Consumption (in mA) <0-510><#/2>
|
||||
// <i>Maximum Power Consumption of USB Device from bus in this
|
||||
// <i>specific configuration when device is fully operational (bMaxPower).
|
||||
#define USBD0_CFG_DESC_BMAXPOWER 250
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>String Settings
|
||||
// <i>These settings are used to create the String Descriptor.
|
||||
// <o.0..15>Language ID <0x0000-0xFCFF>
|
||||
// <i>English (United States) = 0x0409.
|
||||
#define USBD0_STR_DESC_LANGID 0x0409
|
||||
|
||||
// <s.126>Manufacturer String
|
||||
// <i>String Descriptor describing Manufacturer.
|
||||
#define USBD0_STR_DESC_MAN L"KEIL - Tools By ARM"
|
||||
|
||||
// <s.126>Product String
|
||||
// <i>String Descriptor describing Product.
|
||||
#define USBD0_STR_DESC_PROD L"XMC4200 CMSIS-DAP"
|
||||
|
||||
// <e.0>Serial Number
|
||||
// <i>Enable Serial Number String.
|
||||
// <i>If disabled Serial Number String will not be assigned to USB Device.
|
||||
#define USBD0_STR_DESC_SER_EN 1
|
||||
|
||||
// <s.126>Serial Number String
|
||||
// <i>String Descriptor describing device's Serial Number.
|
||||
#define USBD0_STR_DESC_SER L"0001A0000000"
|
||||
|
||||
// </e>
|
||||
// </h>
|
||||
|
||||
// <h>OS Resources Settings
|
||||
// <i>These settings are used to optimize usage of OS resources.
|
||||
// <o>Core Thread Stack Size <64-65536>
|
||||
#define USBD0_CORE_THREAD_STACK_SIZE 512
|
||||
|
||||
// Core Thread Priority
|
||||
#define USBD0_CORE_THREAD_PRIORITY osPriorityAboveNormal
|
||||
|
||||
// </h>
|
||||
// </h>
|
||||
|
||||
|
||||
#include "..\RTE_Components.h"
|
||||
|
||||
#ifdef RTE_USB_Device_CustomClass_0
|
||||
#include "USBD_Config_CustomClass_0.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CustomClass_1
|
||||
#include "USBD_Config_CustomClass_1.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CustomClass_2
|
||||
#include "USBD_Config_CustomClass_2.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CustomClass_3
|
||||
#include "USBD_Config_CustomClass_3.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_USB_Device_HID_0
|
||||
#include "USBD_Config_HID_0.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_HID_1
|
||||
#include "USBD_Config_HID_1.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_HID_2
|
||||
#include "USBD_Config_HID_2.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_HID_3
|
||||
#include "USBD_Config_HID_3.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_USB_Device_MSC_0
|
||||
#include "USBD_Config_MSC_0.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_MSC_1
|
||||
#include "USBD_Config_MSC_1.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_MSC_2
|
||||
#include "USBD_Config_MSC_2.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_MSC_3
|
||||
#include "USBD_Config_MSC_3.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_USB_Device_CDC_0
|
||||
#include "USBD_Config_CDC_0.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CDC_1
|
||||
#include "USBD_Config_CDC_1.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CDC_2
|
||||
#include "USBD_Config_CDC_2.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CDC_3
|
||||
#include "USBD_Config_CDC_3.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_USB_Device_ADC_0
|
||||
#include "USBD_Config_ADC_0.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_ADC_1
|
||||
#include "USBD_Config_ADC_1.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_ADC_2
|
||||
#include "USBD_Config_ADC_2.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_ADC_3
|
||||
#include "USBD_Config_ADC_3.h"
|
||||
#endif
|
||||
|
||||
#include "usbd_config.h"
|
||||
@ -0,0 +1,171 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
* MDK Middleware - Component ::USB:Device
|
||||
* Copyright (c) 2004-2015 ARM Germany GmbH. All rights reserved.
|
||||
*------------------------------------------------------------------------------
|
||||
* Name: USBD_Config_HID_0.h
|
||||
* Purpose: USB Device Human Interface Device class (HID) Configuration
|
||||
* Rev.: V5.0.1
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <h>USB Device: Human Interface Device class (HID) 0
|
||||
// <o>Assign Device Class to USB Device # <0-3>
|
||||
// <i>Select USB Device that is used for this Device Class instance
|
||||
#define USBD_HID0_DEV 0
|
||||
|
||||
// <h>Interrupt Endpoint Settings
|
||||
// <i>By default, the settings match the first USB Class instance in a USB Device.
|
||||
// <i>Endpoint conflicts are flagged by compile-time error messages.
|
||||
//
|
||||
// <h>Interrupt IN Endpoint Settings
|
||||
// <o.0..3>Interrupt IN Endpoint Number
|
||||
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
|
||||
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
|
||||
#define USBD_HID0_EP_INT_IN 1
|
||||
|
||||
// <h>Endpoint Settings
|
||||
// <i>Parameters are used to create USB Descriptors, HID Device Descriptor
|
||||
// <i>and for memory allocation in the USB component.
|
||||
//
|
||||
// <h>Full/Low-speed (High-speed disabled)
|
||||
// <i>Parameters apply when High-speed is disabled in USBD_Config_n.c
|
||||
// <o.0..6>Maximum Endpoint Packet Size (in bytes) <0-64>
|
||||
// <i>Specifies the physical packet size used for information exchange.
|
||||
// <i>Maximum value is 64.
|
||||
#define USBD_HID0_EP_INT_IN_WMAXPACKETSIZE 64
|
||||
|
||||
// <o.0..7>Endpoint polling Interval (in ms) <1-255>
|
||||
// <i>Specifies the frequency of requests initiated by USB Host for
|
||||
// <i>function USBD_HIDn_GetReport.
|
||||
#define USBD_HID0_EP_INT_IN_BINTERVAL 1
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>High-speed
|
||||
// <i>Parameters apply when High-speed is enabled in USBD_Config_n.c
|
||||
//
|
||||
// <o.0..10>Maximum Endpoint Packet Size (in bytes) <0-1024>
|
||||
// <i>Specifies the physical packet size used for information exchange.
|
||||
// <i>Maximum value is 1024.
|
||||
// <o.11..12>Additional transactions per microframe
|
||||
// <i>Additional transactions improve communication performance.
|
||||
// <0=>None <1=>1 additional <2=>2 additional
|
||||
#define USBD_HID0_EP_INT_IN_HS_WMAXPACKETSIZE 64
|
||||
|
||||
// <o.0..4>Endpoint polling Interval (in 125 us intervals)
|
||||
// <i>Specifies the frequency of requests initiated by USB Host for
|
||||
// <i>function USBD_HIDn_GetReport.
|
||||
// <1=> 1 <2=> 2 <3=> 4 <4=> 8
|
||||
// <5=> 16 <6=> 32 <7=> 64 <8=> 128
|
||||
// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048
|
||||
// <13=>4096 <14=>8192 <15=>16384 <16=>32768
|
||||
#define USBD_HID0_EP_INT_IN_HS_BINTERVAL 1
|
||||
|
||||
// </h>
|
||||
// </h>
|
||||
// </h>
|
||||
|
||||
// <h>Interrupt OUT Endpoint Settings
|
||||
// <o.0..3>Interrupt OUT Endpoint Number
|
||||
// <i>When OUT Endpoint is set to "Not used" the USB Host uses
|
||||
// <i>the Control Endpoint 0 for Out Reports.
|
||||
// <0=>Not used
|
||||
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
|
||||
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
|
||||
#define USBD_HID0_EP_INT_OUT 1
|
||||
|
||||
// <h>Endpoint Settings
|
||||
// <i>Parameters are used to create USB Descriptors, HID Device Descriptor
|
||||
// <i>and for memory allocation in the USB component.
|
||||
//
|
||||
// <h>Full/Low-speed (High-speed disabled)
|
||||
// <i>Parameters apply when High-speed is disabled in USBD_Config_n.c
|
||||
// <o.0..6>Maximum Endpoint Packet Size (in bytes) <0-64>
|
||||
// <i>Specifies the physical packet size used for information exchange.
|
||||
// <i>Maximum value is 64.
|
||||
#define USBD_HID0_EP_INT_OUT_WMAXPACKETSIZE 64
|
||||
|
||||
// <o.0..7>Endpoint polling Interval (in ms) <1-255>
|
||||
// <i>Specifies the frequency of requests initiated by USB Host for
|
||||
// <i>function USBD_HIDn_GetReport.
|
||||
#define USBD_HID0_EP_INT_OUT_BINTERVAL 1
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>High-speed
|
||||
// <i>Parameters apply when High-speed is enabled in USBD_Config_n.c
|
||||
//
|
||||
// <o.0..10>Maximum Endpoint Packet Size (in bytes) <0-1024>
|
||||
// <i>Specifies the physical packet size used for information exchange.
|
||||
// <i>Maximum value is 1024.
|
||||
// <o.11..12>Additional transactions per microframe
|
||||
// <i>Additional transactions improve communication performance.
|
||||
// <0=>None <1=>1 additional <2=>2 additional
|
||||
#define USBD_HID0_EP_INT_OUT_HS_WMAXPACKETSIZE 64
|
||||
|
||||
// <o.0..4>Endpoint polling Interval (in 125 us intervals)
|
||||
// <i>Specifies the frequency of requests initiated by USB Host for
|
||||
// <i>function USBD_HIDn_GetReport.
|
||||
// <1=> 1 <2=> 2 <3=> 4 <4=> 8
|
||||
// <5=> 16 <6=> 32 <7=> 64 <8=> 128
|
||||
// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048
|
||||
// <13=>4096 <14=>8192 <15=>16384 <16=>32768
|
||||
#define USBD_HID0_EP_INT_OUT_HS_BINTERVAL 1
|
||||
|
||||
// </h>
|
||||
// </h>
|
||||
// </h>
|
||||
// </h>
|
||||
|
||||
// <h>Human Interface Device Class Settings
|
||||
// <i>Parameters are used to create USB Descriptors, USB HID Report Descriptor
|
||||
// <i>and for memory allocation in the USB component.
|
||||
//
|
||||
// <s.126>HID Interface String
|
||||
#define USBD_HID0_STR_DESC L"XMC4200 CMSIS-DAP"
|
||||
|
||||
// <o.0..4>Number of Input Reports <1-32>
|
||||
// <i>Configures max 'rid' value for USBD_HID0_GetReport and USBD_HID_GetReportTrigger
|
||||
#define USBD_HID0_IN_REPORT_NUM 1
|
||||
|
||||
// <o.0..4>Number of Output Reports <1-32>
|
||||
// <i>Configures max 'rid' value for USBD_HID0_SetReport
|
||||
#define USBD_HID0_OUT_REPORT_NUM 1
|
||||
|
||||
// <o.0..15>Maximum Input Report Size (in bytes) <1-65535>
|
||||
// <i>Allocates memory and configures 'len' value for USBD_HID0_GetReport
|
||||
// <i>and USBD_HID_GetReportTrigger
|
||||
#define USBD_HID0_IN_REPORT_MAX_SZ 64
|
||||
|
||||
// <o.0..15>Maximum Output Report Size (in bytes) <1-65535>
|
||||
// <i>Allocates memory and configures 'len' value for USBD_HID0_SetReport
|
||||
// <i>when rtype=HID_REPORT_OUTPUT.
|
||||
#define USBD_HID0_OUT_REPORT_MAX_SZ 64
|
||||
|
||||
// <o.0..15>Maximum Feature Report Size (in bytes) <1-65535>
|
||||
// <i>Allocates memory and configures 'len' value for USBD_HID0_SetReport
|
||||
// <i>when rtype=HID_REPORT_FEATURE
|
||||
#define USBD_HID0_FEAT_REPORT_MAX_SZ 1
|
||||
|
||||
// <e.0>Use User Provided HID Report Descriptor
|
||||
// <i>User needs to provide HID Report Descriptor in array
|
||||
// <i>const uint8_t usbd_hid0_report_descriptor[]
|
||||
#define USBD_HID0_USER_REPORT_DESCRIPTOR 0
|
||||
|
||||
// <o>User Provided HID Report Descriptor Size (in bytes) <1-65535>
|
||||
#define USBD_HID0_USER_REPORT_DESCRIPTOR_SIZE 33
|
||||
|
||||
// </e>
|
||||
// </h>
|
||||
|
||||
// <h>OS Resources Settings
|
||||
// <i>These settings are used to optimize usage of OS resources.
|
||||
// <o>Human Interface Device Class Thread Stack Size <64-65536>
|
||||
#define USBD_HID0_THREAD_STACK_SIZE 512
|
||||
|
||||
// Human Interface Device Class Thread Priority
|
||||
#define USBD_HID0_THREAD_PRIORITY osPriorityAboveNormal
|
||||
|
||||
// </h>
|
||||
// </h>
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,237 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
* MDK Middleware - Component ::USB:Device
|
||||
* Copyright (c) 2004-2014 ARM Germany GmbH. All rights reserved.
|
||||
*------------------------------------------------------------------------------
|
||||
* Name: USBD_User_HID_0.c
|
||||
* Purpose: USB Device Human Interface Device class (HID) User module
|
||||
* Rev.: V6.2
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* \addtogroup usbd_hidFunctions
|
||||
*
|
||||
* USBD_User_HID_0.c implements the application specific functionality of the
|
||||
* HID class and is used to receive and send data reports to the USB Host.
|
||||
*
|
||||
* The implementation must match the configuration file USBD_Config_HID_0.h.
|
||||
* The following values in USBD_Config_HID_0.h affect the user code:
|
||||
*
|
||||
* - 'Endpoint polling Interval' specifies the frequency of requests
|
||||
* initiated by USB Host for \ref USBD_HIDn_GetReport.
|
||||
*
|
||||
* - 'Number of Output Reports' configures the values for \em rid of
|
||||
* \ref USBD_HIDn_SetReport.
|
||||
*
|
||||
* - 'Number of Input Reports' configures the values for \em rid of
|
||||
* \ref USBD_HIDn_GetReport and \ref USBD_HID_GetReportTrigger.
|
||||
*
|
||||
* - 'Maximum Input Report Size' specifies the maximum value for:
|
||||
* - return of \ref USBD_HIDn_GetReport
|
||||
* - len of \ref USBD_HID_GetReportTrigger.
|
||||
*
|
||||
* - 'Maximum Output Report Size' specifies the maximum value for \em len
|
||||
* in \ref USBD_HIDn_SetReport for rtype=HID_REPORT_OUTPUT
|
||||
*
|
||||
* - 'Maximum Feature Report Size' specifies the maximum value for \em len
|
||||
* in \ref USBD_HIDn_SetReport for rtype=HID_REPORT_FEATURE
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
//! [code_USBD_User_HID]
|
||||
|
||||
#include <string.h>
|
||||
#define osObjectsExternal
|
||||
#include "cmsis_os.h"
|
||||
#include "osObjects.h"
|
||||
#include "rl_usb.h"
|
||||
#include "USB\USBD_Config_HID_0.h"
|
||||
#include "DAP_config.h"
|
||||
#include "DAP.h"
|
||||
|
||||
|
||||
#if (USBD_HID0_OUT_REPORT_MAX_SZ != DAP_PACKET_SIZE)
|
||||
#error "USB HID0 Output Report Size must match DAP Packet Size"
|
||||
#endif
|
||||
#if (USBD_HID0_IN_REPORT_MAX_SZ != DAP_PACKET_SIZE)
|
||||
#error "USB HID Input Report Size must match DAP Packet Size"
|
||||
#endif
|
||||
|
||||
static uint16_t USB_RequestIndexI; // Request Index In
|
||||
static uint16_t USB_RequestIndexO; // Request Index Out
|
||||
static uint16_t USB_RequestCountI; // Request Count In
|
||||
static uint16_t USB_RequestCountO; // Request Count Out
|
||||
|
||||
static uint16_t USB_ResponseIndexI; // Response Index In
|
||||
static uint16_t USB_ResponseIndexO; // Response Index Out
|
||||
static uint16_t USB_ResponseCountI; // Response Count In
|
||||
static uint16_t USB_ResponseCountO; // Response Count Out
|
||||
static uint8_t USB_ResponseIdle; // Response Idle Flag
|
||||
|
||||
static uint8_t USB_Request [DAP_PACKET_COUNT][DAP_PACKET_SIZE]; // Request Buffer
|
||||
static uint8_t USB_Response[DAP_PACKET_COUNT][DAP_PACKET_SIZE]; // Response Buffer
|
||||
|
||||
|
||||
// Called during USBD_Initialize to initialize the USB Device class.
|
||||
void USBD_HID0_Initialize (void) {
|
||||
// Initialize variables
|
||||
USB_RequestIndexI = 0U;
|
||||
USB_RequestIndexO = 0U;
|
||||
USB_RequestCountI = 0U;
|
||||
USB_RequestCountO = 0U;
|
||||
USB_ResponseIndexI = 0U;
|
||||
USB_ResponseIndexO = 0U;
|
||||
USB_ResponseCountI = 0U;
|
||||
USB_ResponseCountO = 0U;
|
||||
USB_ResponseIdle = 1U;
|
||||
}
|
||||
|
||||
|
||||
// Called during USBD_Uninitialize to de-initialize the USB Device class.
|
||||
void USBD_HID0_Uninitialize (void) {
|
||||
}
|
||||
|
||||
|
||||
// \brief Prepare HID Report data to send.
|
||||
// \param[in] rtype report type:
|
||||
// - HID_REPORT_INPUT = input report requested
|
||||
// - HID_REPORT_FEATURE = feature report requested
|
||||
// \param[in] req request type:
|
||||
// - USBD_HID_REQ_EP_CTRL = control endpoint request
|
||||
// - USBD_HID_REQ_PERIOD_UPDATE = idle period expiration request
|
||||
// - USBD_HID_REQ_EP_INT = previously sent report on interrupt endpoint request
|
||||
// \param[in] rid report ID (0 if only one report exists).
|
||||
// \param[out] buf buffer containing report data to send.
|
||||
// \return number of report data bytes prepared to send or invalid report requested.
|
||||
// - value >= 0: number of report data bytes prepared to send
|
||||
// - value = -1: invalid report requested
|
||||
int32_t USBD_HID0_GetReport (uint8_t rtype, uint8_t req, uint8_t rid, uint8_t *buf) {
|
||||
|
||||
switch (rtype) {
|
||||
case HID_REPORT_INPUT:
|
||||
switch (req) {
|
||||
case USBD_HID_REQ_EP_CTRL: // Explicit USB Host request via Control OUT Endpoint
|
||||
case USBD_HID_REQ_PERIOD_UPDATE: // Periodic USB Host request via Interrupt OUT Endpoint
|
||||
break;
|
||||
case USBD_HID_REQ_EP_INT: // Called after USBD_HID_GetReportTrigger to signal data obtained.
|
||||
if (USB_ResponseCountI != USB_ResponseCountO) {
|
||||
// Load data from response buffer to be sent back
|
||||
memcpy(buf, USB_Response[USB_ResponseIndexO], DAP_PACKET_SIZE);
|
||||
USB_ResponseIndexO++;
|
||||
if (USB_ResponseIndexO == DAP_PACKET_COUNT) {
|
||||
USB_ResponseIndexO = 0U;
|
||||
}
|
||||
USB_ResponseCountO++;
|
||||
return ((int32_t)DAP_PACKET_SIZE);
|
||||
} else {
|
||||
USB_ResponseIdle = 1U;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case HID_REPORT_FEATURE:
|
||||
break;
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
// \brief Process received HID Report data.
|
||||
// \param[in] rtype report type:
|
||||
// - HID_REPORT_OUTPUT = output report received
|
||||
// - HID_REPORT_FEATURE = feature report received
|
||||
// \param[in] req request type:
|
||||
// - USBD_HID_REQ_EP_CTRL = report received on control endpoint
|
||||
// - USBD_HID_REQ_EP_INT = report received on interrupt endpoint
|
||||
// \param[in] rid report ID (0 if only one report exists).
|
||||
// \param[in] buf buffer that receives report data.
|
||||
// \param[in] len length of received report data.
|
||||
// \return true received report data processed.
|
||||
// \return false received report data not processed or request not supported.
|
||||
bool USBD_HID0_SetReport (uint8_t rtype, uint8_t req, uint8_t rid, const uint8_t *buf, int32_t len) {
|
||||
|
||||
switch (rtype) {
|
||||
case HID_REPORT_OUTPUT:
|
||||
if (len == 0) { break; }
|
||||
if (buf[0] == ID_DAP_TransferAbort) {
|
||||
DAP_TransferAbort = 1U;
|
||||
break;
|
||||
}
|
||||
if ((uint16_t)(USB_RequestCountI - USB_RequestCountO) == DAP_PACKET_COUNT) {
|
||||
osSignalSet(HID0_ThreadId, 0x80);
|
||||
break; // Discard packet when buffer is full
|
||||
}
|
||||
// Store received data into request buffer
|
||||
memcpy(USB_Request[USB_RequestIndexI], buf, len);
|
||||
USB_RequestIndexI++;
|
||||
if (USB_RequestIndexI == DAP_PACKET_COUNT) {
|
||||
USB_RequestIndexI = 0U;
|
||||
}
|
||||
USB_RequestCountI++;
|
||||
osSignalSet(HID0_ThreadId, 0x01);
|
||||
break;
|
||||
case HID_REPORT_FEATURE:
|
||||
break;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
// HID0 Thread.
|
||||
void HID0_Thread (void const *arg) {
|
||||
osEvent evt;
|
||||
uint32_t n;
|
||||
|
||||
for (;;) {
|
||||
osSignalWait(0, osWaitForever);
|
||||
|
||||
// Process pending requests
|
||||
while (USB_RequestCountI != USB_RequestCountO) {
|
||||
|
||||
// Handle Queue Commands
|
||||
n = USB_RequestIndexO;
|
||||
while (USB_Request[n][0] == ID_DAP_QueueCommands) {
|
||||
USB_Request[n][0] = ID_DAP_ExecuteCommands;
|
||||
n++;
|
||||
if (n == DAP_PACKET_COUNT) {
|
||||
n = 0U;
|
||||
}
|
||||
if (n == USB_RequestIndexI) {
|
||||
evt = osSignalWait(0, osWaitForever);
|
||||
if (evt.value.signals & 0x80) { break; }
|
||||
}
|
||||
}
|
||||
|
||||
// Execute DAP Command (process request and prepare response)
|
||||
DAP_ExecuteCommand(USB_Request[USB_RequestIndexO], USB_Response[USB_ResponseIndexI]);
|
||||
|
||||
// Update Request Index and Count
|
||||
USB_RequestIndexO++;
|
||||
if (USB_RequestIndexO == DAP_PACKET_COUNT) {
|
||||
USB_RequestIndexO = 0U;
|
||||
}
|
||||
USB_RequestCountO++;
|
||||
|
||||
// Update Response Index and Count
|
||||
USB_ResponseIndexI++;
|
||||
if (USB_ResponseIndexI == DAP_PACKET_COUNT) {
|
||||
USB_ResponseIndexI = 0U;
|
||||
}
|
||||
USB_ResponseCountI++;
|
||||
|
||||
if (USB_ResponseIdle) {
|
||||
if (USB_ResponseCountI != USB_ResponseCountO) {
|
||||
// Load data from response buffer to be sent back
|
||||
n = USB_ResponseIndexO++;
|
||||
if (USB_ResponseIndexO == DAP_PACKET_COUNT) {
|
||||
USB_ResponseIndexO = 0U;
|
||||
}
|
||||
USB_ResponseCountO++;
|
||||
USB_ResponseIdle = 0U;
|
||||
USBD_HID_GetReportTrigger(0U, 0U, USB_Response[n], DAP_PACKET_SIZE);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//! [code_USBD_User_HID]
|
||||
@ -0,0 +1,50 @@
|
||||
/******************************************************************************
|
||||
* @file main.c
|
||||
* @brief CMSIS-DAP Main module
|
||||
* @version V1.10
|
||||
* @date 20. Jan 2015
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2012-2015 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "cmsis_os.h"
|
||||
#include "osObjects.h"
|
||||
#include "rl_usb.h"
|
||||
#include "DAP_config.h"
|
||||
#include "DAP.h"
|
||||
|
||||
// Main program
|
||||
int main (void) {
|
||||
|
||||
DAP_Setup(); // DAP Setup
|
||||
|
||||
USBD_Initialize(0U); // USB Device Initialization
|
||||
USBD_Connect(0U); // USB Device Connect
|
||||
|
||||
while (!USBD_Configured(0U)); // Wait for USB Device to configure
|
||||
|
||||
LED_CONNECTED_OUT(1U); // Turn on Debugger Connected LED
|
||||
LED_RUNNING_OUT(1U); // Turn on Target Running LED
|
||||
Delayms(500U); // Wait for 500ms
|
||||
LED_RUNNING_OUT(0U); // Turn off Target Running LED
|
||||
LED_CONNECTED_OUT(0U); // Turn off Debugger Connected LED
|
||||
|
||||
// Create HID Thread
|
||||
HID0_ThreadId = osThreadCreate(osThread(HID0_Thread), NULL);
|
||||
|
||||
osThreadSetPriority(osThreadGetId(), osPriorityIdle);
|
||||
for (;;); // Endless Loop
|
||||
}
|
||||
@ -0,0 +1,37 @@
|
||||
/******************************************************************************
|
||||
* @file osObjects.h
|
||||
* @brief CMSIS-DAP RTOS Objects
|
||||
* @version V1.10
|
||||
* @date 20. Jan 2015
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2012-2015 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __osObjects_h__
|
||||
#define __osObjects_h__
|
||||
|
||||
#include "cmsis_os.h"
|
||||
|
||||
#ifdef osObjectsExternal
|
||||
extern osThreadId HID0_ThreadId;
|
||||
#else
|
||||
osThreadId HID0_ThreadId;
|
||||
#endif
|
||||
|
||||
extern void HID0_Thread (void const *arg);
|
||||
osThreadDef(HID0_Thread, osPriorityNormal, 1U, 512U);
|
||||
|
||||
#endif /* __osObjects_h__ */
|
||||
264
PAN159/PAN159-Template/Library/CMSIS/DAP/Firmware/Include/DAP.h
Normal file
264
PAN159/PAN159-Template/Library/CMSIS/DAP/Firmware/Include/DAP.h
Normal file
@ -0,0 +1,264 @@
|
||||
/******************************************************************************
|
||||
* @file DAP.h
|
||||
* @brief CMSIS-DAP Definitions
|
||||
* @version V1.10
|
||||
* @date 20. May 2015
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2012-2015 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __DAP_H__
|
||||
#define __DAP_H__
|
||||
|
||||
|
||||
// DAP Command IDs
|
||||
#define ID_DAP_Info 0x00U
|
||||
#define ID_DAP_HostStatus 0x01U
|
||||
#define ID_DAP_Connect 0x02U
|
||||
#define ID_DAP_Disconnect 0x03U
|
||||
#define ID_DAP_TransferConfigure 0x04U
|
||||
#define ID_DAP_Transfer 0x05U
|
||||
#define ID_DAP_TransferBlock 0x06U
|
||||
#define ID_DAP_TransferAbort 0x07U
|
||||
#define ID_DAP_WriteABORT 0x08U
|
||||
#define ID_DAP_Delay 0x09U
|
||||
#define ID_DAP_ResetTarget 0x0AU
|
||||
#define ID_DAP_SWJ_Pins 0x10U
|
||||
#define ID_DAP_SWJ_Clock 0x11U
|
||||
#define ID_DAP_SWJ_Sequence 0x12U
|
||||
#define ID_DAP_SWD_Configure 0x13U
|
||||
#define ID_DAP_JTAG_Sequence 0x14U
|
||||
#define ID_DAP_JTAG_Configure 0x15U
|
||||
#define ID_DAP_JTAG_IDCODE 0x16U
|
||||
#define ID_DAP_SWO_Transport 0x17U
|
||||
#define ID_DAP_SWO_Mode 0x18U
|
||||
#define ID_DAP_SWO_Baudrate 0x19U
|
||||
#define ID_DAP_SWO_Control 0x1AU
|
||||
#define ID_DAP_SWO_Status 0x1BU
|
||||
#define ID_DAP_SWO_Data 0x1CU
|
||||
|
||||
#define ID_DAP_QueueCommands 0x7EU
|
||||
#define ID_DAP_ExecuteCommands 0x7FU
|
||||
|
||||
// DAP Vendor Command IDs
|
||||
#define ID_DAP_Vendor0 0x80U
|
||||
#define ID_DAP_Vendor1 0x81U
|
||||
#define ID_DAP_Vendor2 0x82U
|
||||
#define ID_DAP_Vendor3 0x83U
|
||||
#define ID_DAP_Vendor4 0x84U
|
||||
#define ID_DAP_Vendor5 0x85U
|
||||
#define ID_DAP_Vendor6 0x86U
|
||||
#define ID_DAP_Vendor7 0x87U
|
||||
#define ID_DAP_Vendor8 0x88U
|
||||
#define ID_DAP_Vendor9 0x89U
|
||||
#define ID_DAP_Vendor10 0x8AU
|
||||
#define ID_DAP_Vendor11 0x8BU
|
||||
#define ID_DAP_Vendor12 0x8CU
|
||||
#define ID_DAP_Vendor13 0x8DU
|
||||
#define ID_DAP_Vendor14 0x8EU
|
||||
#define ID_DAP_Vendor15 0x8FU
|
||||
#define ID_DAP_Vendor16 0x90U
|
||||
#define ID_DAP_Vendor17 0x91U
|
||||
#define ID_DAP_Vendor18 0x92U
|
||||
#define ID_DAP_Vendor19 0x93U
|
||||
#define ID_DAP_Vendor20 0x94U
|
||||
#define ID_DAP_Vendor21 0x95U
|
||||
#define ID_DAP_Vendor22 0x96U
|
||||
#define ID_DAP_Vendor23 0x97U
|
||||
#define ID_DAP_Vendor24 0x98U
|
||||
#define ID_DAP_Vendor25 0x99U
|
||||
#define ID_DAP_Vendor26 0x9AU
|
||||
#define ID_DAP_Vendor27 0x9BU
|
||||
#define ID_DAP_Vendor28 0x9CU
|
||||
#define ID_DAP_Vendor29 0x9DU
|
||||
#define ID_DAP_Vendor30 0x9EU
|
||||
#define ID_DAP_Vendor31 0x9FU
|
||||
|
||||
#define ID_DAP_Invalid 0xFFU
|
||||
|
||||
// DAP Status Code
|
||||
#define DAP_OK 0U
|
||||
#define DAP_ERROR 0xFFU
|
||||
|
||||
// DAP ID
|
||||
#define DAP_ID_VENDOR 1U
|
||||
#define DAP_ID_PRODUCT 2U
|
||||
#define DAP_ID_SER_NUM 3U
|
||||
#define DAP_ID_FW_VER 4U
|
||||
#define DAP_ID_DEVICE_VENDOR 5U
|
||||
#define DAP_ID_DEVICE_NAME 6U
|
||||
#define DAP_ID_CAPABILITIES 0xF0U
|
||||
#define DAP_ID_SWO_BUFFER_SIZE 0xFDU
|
||||
#define DAP_ID_PACKET_COUNT 0xFEU
|
||||
#define DAP_ID_PACKET_SIZE 0xFFU
|
||||
|
||||
// DAP Host Status
|
||||
#define DAP_DEBUGGER_CONNECTED 0U
|
||||
#define DAP_TARGET_RUNNING 1U
|
||||
|
||||
// DAP Port
|
||||
#define DAP_PORT_AUTODETECT 0U // Autodetect Port
|
||||
#define DAP_PORT_DISABLED 0U // Port Disabled (I/O pins in High-Z)
|
||||
#define DAP_PORT_SWD 1U // SWD Port (SWCLK, SWDIO) + nRESET
|
||||
#define DAP_PORT_JTAG 2U // JTAG Port (TCK, TMS, TDI, TDO, nTRST) + nRESET
|
||||
|
||||
// DAP SWJ Pins
|
||||
#define DAP_SWJ_SWCLK_TCK 0 // SWCLK/TCK
|
||||
#define DAP_SWJ_SWDIO_TMS 1 // SWDIO/TMS
|
||||
#define DAP_SWJ_TDI 2 // TDI
|
||||
#define DAP_SWJ_TDO 3 // TDO
|
||||
#define DAP_SWJ_nTRST 5 // nTRST
|
||||
#define DAP_SWJ_nRESET 7 // nRESET
|
||||
|
||||
// DAP Transfer Request
|
||||
#define DAP_TRANSFER_APnDP (1U<<0)
|
||||
#define DAP_TRANSFER_RnW (1U<<1)
|
||||
#define DAP_TRANSFER_A2 (1U<<2)
|
||||
#define DAP_TRANSFER_A3 (1U<<3)
|
||||
#define DAP_TRANSFER_MATCH_VALUE (1U<<4)
|
||||
#define DAP_TRANSFER_MATCH_MASK (1U<<5)
|
||||
|
||||
// DAP Transfer Response
|
||||
#define DAP_TRANSFER_OK (1U<<0)
|
||||
#define DAP_TRANSFER_WAIT (1U<<1)
|
||||
#define DAP_TRANSFER_FAULT (1U<<2)
|
||||
#define DAP_TRANSFER_ERROR (1U<<3)
|
||||
#define DAP_TRANSFER_MISMATCH (1U<<4)
|
||||
|
||||
// DAP SWO Trace Mode
|
||||
#define DAP_SWO_OFF 0U
|
||||
#define DAP_SWO_UART 1U
|
||||
#define DAP_SWO_MANCHESTER 2U
|
||||
|
||||
// DAP SWO Trace Status
|
||||
#define DAP_SWO_CAPTURE_ACTIVE (1U<<0)
|
||||
#define DAP_SWO_CAPTURE_PAUSED (1U<<1)
|
||||
#define DAP_SWO_STREAM_ERROR (1U<<6)
|
||||
#define DAP_SWO_BUFFER_OVERRUN (1U<<7)
|
||||
|
||||
|
||||
// Debug Port Register Addresses
|
||||
#define DP_IDCODE 0x00U // IDCODE Register (SW Read only)
|
||||
#define DP_ABORT 0x00U // Abort Register (SW Write only)
|
||||
#define DP_CTRL_STAT 0x04U // Control & Status
|
||||
#define DP_WCR 0x04U // Wire Control Register (SW Only)
|
||||
#define DP_SELECT 0x08U // Select Register (JTAG R/W & SW W)
|
||||
#define DP_RESEND 0x08U // Resend (SW Read Only)
|
||||
#define DP_RDBUFF 0x0CU // Read Buffer (Read Only)
|
||||
|
||||
// JTAG IR Codes
|
||||
#define JTAG_ABORT 0x08U
|
||||
#define JTAG_DPACC 0x0AU
|
||||
#define JTAG_APACC 0x0BU
|
||||
#define JTAG_IDCODE 0x0EU
|
||||
#define JTAG_BYPASS 0x0FU
|
||||
|
||||
// JTAG Sequence Info
|
||||
#define JTAG_SEQUENCE_TCK 0x3FU // TCK count
|
||||
#define JTAG_SEQUENCE_TMS 0x40U // TMS value
|
||||
#define JTAG_SEQUENCE_TDO 0x80U // TDO capture
|
||||
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
||||
// DAP Data structure
|
||||
typedef struct {
|
||||
uint8_t debug_port; // Debug Port
|
||||
uint8_t fast_clock; // Fast Clock Flag
|
||||
uint32_t clock_delay; // Clock Delay
|
||||
struct { // Transfer Configuration
|
||||
uint8_t idle_cycles; // Idle cycles after transfer
|
||||
uint16_t retry_count; // Number of retries after WAIT response
|
||||
uint16_t match_retry; // Number of retries if read value does not match
|
||||
uint32_t match_mask; // Match Mask
|
||||
} transfer;
|
||||
#if (DAP_SWD != 0)
|
||||
struct { // SWD Configuration
|
||||
uint8_t turnaround; // Turnaround period
|
||||
uint8_t data_phase; // Always generate Data Phase
|
||||
} swd_conf;
|
||||
#endif
|
||||
#if (DAP_JTAG != 0)
|
||||
struct { // JTAG Device Chain
|
||||
uint8_t count; // Number of devices
|
||||
uint8_t index; // Device index (device at TDO has index 0)
|
||||
#if (DAP_JTAG_DEV_CNT != 0)
|
||||
uint8_t ir_length[DAP_JTAG_DEV_CNT]; // IR Length in bits
|
||||
uint16_t ir_before[DAP_JTAG_DEV_CNT]; // Bits before IR
|
||||
uint16_t ir_after [DAP_JTAG_DEV_CNT]; // Bits after IR
|
||||
#endif
|
||||
} jtag_dev;
|
||||
#endif
|
||||
} DAP_Data_t;
|
||||
|
||||
extern DAP_Data_t DAP_Data; // DAP Data
|
||||
extern volatile uint8_t DAP_TransferAbort; // Transfer Abort Flag
|
||||
|
||||
|
||||
// Functions
|
||||
extern void SWJ_Sequence (uint32_t count, const uint8_t *data);
|
||||
extern void JTAG_Sequence (uint32_t info, const uint8_t *tdi, uint8_t *tdo);
|
||||
extern void JTAG_IR (uint32_t ir);
|
||||
extern uint32_t JTAG_ReadIDCode (void);
|
||||
extern void JTAG_WriteAbort (uint32_t data);
|
||||
extern uint8_t JTAG_Transfer (uint32_t request, uint32_t *data);
|
||||
extern uint8_t SWD_Transfer (uint32_t request, uint32_t *data);
|
||||
|
||||
extern void Delayms (uint32_t delay);
|
||||
|
||||
extern uint32_t SWO_Transport (const uint8_t *request, uint8_t *response);
|
||||
extern uint32_t SWO_Mode (const uint8_t *request, uint8_t *response);
|
||||
extern uint32_t SWO_Baudrate (const uint8_t *request, uint8_t *response);
|
||||
extern uint32_t SWO_Control (const uint8_t *request, uint8_t *response);
|
||||
extern uint32_t SWO_Status (uint8_t *response);
|
||||
extern uint32_t SWO_Data (const uint8_t *request, uint8_t *response);
|
||||
|
||||
extern uint32_t DAP_ProcessVendorCommand (const uint8_t *request, uint8_t *response);
|
||||
extern uint32_t DAP_ProcessCommand (const uint8_t *request, uint8_t *response);
|
||||
extern uint32_t DAP_ExecuteCommand (const uint8_t *request, uint8_t *response);
|
||||
|
||||
extern void DAP_Setup (void);
|
||||
|
||||
// Configurable delay for clock generation
|
||||
#ifndef DELAY_SLOW_CYCLES
|
||||
#define DELAY_SLOW_CYCLES 3U // Number of cycles for one iteration
|
||||
#endif
|
||||
static __forceinline void PIN_DELAY_SLOW (uint32_t delay) {
|
||||
uint32_t count;
|
||||
|
||||
count = delay;
|
||||
while (--count);
|
||||
}
|
||||
|
||||
// Fixed delay for fast clock generation
|
||||
#ifndef DELAY_FAST_CYCLES
|
||||
#define DELAY_FAST_CYCLES 0U // Number of cycles: 0..3
|
||||
#endif
|
||||
static __forceinline void PIN_DELAY_FAST (void) {
|
||||
#if (DELAY_FAST_CYCLES >= 1U)
|
||||
__nop();
|
||||
#endif
|
||||
#if (DELAY_FAST_CYCLES >= 2U)
|
||||
__nop();
|
||||
#endif
|
||||
#if (DELAY_FAST_CYCLES >= 3U)
|
||||
__nop();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
#endif /* __DAP_H__ */
|
||||
1591
PAN159/PAN159-Template/Library/CMSIS/DAP/Firmware/Source/DAP.c
Normal file
1591
PAN159/PAN159-Template/Library/CMSIS/DAP/Firmware/Source/DAP.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,95 @@
|
||||
/**************************************************************************//**
|
||||
* @file DAP_vendor.c
|
||||
* @brief CMSIS-DAP Vendor Commands
|
||||
* @version V1.10
|
||||
* @date 20. May 2015
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2012-2015 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "DAP_config.h"
|
||||
#include "DAP.h"
|
||||
|
||||
//**************************************************************************************************
|
||||
/**
|
||||
\defgroup DAP_Vendor_Adapt_gr Adapt Vendor Commands
|
||||
\ingroup DAP_Vendor_gr
|
||||
@{
|
||||
|
||||
The file DAP_vendor.c provides template source code for extension of a Debug Unit with
|
||||
Vendor Commands. Copy this file to the project folder of the Debug Unit and add the
|
||||
file to the MDK-ARM project under the file group Configuration.
|
||||
*/
|
||||
|
||||
/** Process DAP Vendor Command and prepare Response Data
|
||||
\param request pointer to request data
|
||||
\param response pointer to response data
|
||||
\return number of bytes in response (lower 16 bits)
|
||||
number of bytes in request (upper 16 bits)
|
||||
*/
|
||||
uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) {
|
||||
uint32_t num = (1U << 16) | 1U;
|
||||
|
||||
*response++ = *request; // copy Command ID
|
||||
|
||||
switch (*request++) { // first byte in request is Command ID
|
||||
case ID_DAP_Vendor0:
|
||||
#if 0 // example user command
|
||||
num += 1U << 16; // increment request count
|
||||
if (*request == 1U) { // when first command data byte is 1
|
||||
*response++ = 'X'; // send 'X' as response
|
||||
num++; // increment response count
|
||||
}
|
||||
#endif
|
||||
break;
|
||||
|
||||
case ID_DAP_Vendor1: break;
|
||||
case ID_DAP_Vendor2: break;
|
||||
case ID_DAP_Vendor3: break;
|
||||
case ID_DAP_Vendor4: break;
|
||||
case ID_DAP_Vendor5: break;
|
||||
case ID_DAP_Vendor6: break;
|
||||
case ID_DAP_Vendor7: break;
|
||||
case ID_DAP_Vendor8: break;
|
||||
case ID_DAP_Vendor9: break;
|
||||
case ID_DAP_Vendor10: break;
|
||||
case ID_DAP_Vendor11: break;
|
||||
case ID_DAP_Vendor12: break;
|
||||
case ID_DAP_Vendor13: break;
|
||||
case ID_DAP_Vendor14: break;
|
||||
case ID_DAP_Vendor15: break;
|
||||
case ID_DAP_Vendor16: break;
|
||||
case ID_DAP_Vendor17: break;
|
||||
case ID_DAP_Vendor18: break;
|
||||
case ID_DAP_Vendor19: break;
|
||||
case ID_DAP_Vendor20: break;
|
||||
case ID_DAP_Vendor21: break;
|
||||
case ID_DAP_Vendor22: break;
|
||||
case ID_DAP_Vendor23: break;
|
||||
case ID_DAP_Vendor24: break;
|
||||
case ID_DAP_Vendor25: break;
|
||||
case ID_DAP_Vendor26: break;
|
||||
case ID_DAP_Vendor27: break;
|
||||
case ID_DAP_Vendor28: break;
|
||||
case ID_DAP_Vendor29: break;
|
||||
case ID_DAP_Vendor30: break;
|
||||
case ID_DAP_Vendor31: break;
|
||||
}
|
||||
|
||||
return (num);
|
||||
}
|
||||
|
||||
///@}
|
||||
@ -0,0 +1,358 @@
|
||||
/******************************************************************************
|
||||
* @file JTAG_DP.c
|
||||
* @brief CMSIS-DAP JTAG DP I/O
|
||||
* @version V1.10
|
||||
* @date 20. May 2015
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2012-2015 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "DAP_config.h"
|
||||
#include "DAP.h"
|
||||
|
||||
|
||||
// JTAG Macros
|
||||
|
||||
#define PIN_TCK_SET PIN_SWCLK_TCK_SET
|
||||
#define PIN_TCK_CLR PIN_SWCLK_TCK_CLR
|
||||
#define PIN_TMS_SET PIN_SWDIO_TMS_SET
|
||||
#define PIN_TMS_CLR PIN_SWDIO_TMS_CLR
|
||||
|
||||
#define JTAG_CYCLE_TCK() \
|
||||
PIN_TCK_CLR(); \
|
||||
PIN_DELAY(); \
|
||||
PIN_TCK_SET(); \
|
||||
PIN_DELAY()
|
||||
|
||||
#define JTAG_CYCLE_TDI(tdi) \
|
||||
PIN_TDI_OUT(tdi); \
|
||||
PIN_TCK_CLR(); \
|
||||
PIN_DELAY(); \
|
||||
PIN_TCK_SET(); \
|
||||
PIN_DELAY()
|
||||
|
||||
#define JTAG_CYCLE_TDO(tdo) \
|
||||
PIN_TCK_CLR(); \
|
||||
PIN_DELAY(); \
|
||||
tdo = PIN_TDO_IN(); \
|
||||
PIN_TCK_SET(); \
|
||||
PIN_DELAY()
|
||||
|
||||
#define JTAG_CYCLE_TDIO(tdi,tdo) \
|
||||
PIN_TDI_OUT(tdi); \
|
||||
PIN_TCK_CLR(); \
|
||||
PIN_DELAY(); \
|
||||
tdo = PIN_TDO_IN(); \
|
||||
PIN_TCK_SET(); \
|
||||
PIN_DELAY()
|
||||
|
||||
#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
|
||||
|
||||
|
||||
#if (DAP_JTAG != 0)
|
||||
|
||||
|
||||
// Generate JTAG Sequence
|
||||
// info: sequence information
|
||||
// tdi: pointer to TDI generated data
|
||||
// tdo: pointer to TDO captured data
|
||||
// return: none
|
||||
void JTAG_Sequence (uint32_t info, const uint8_t *tdi, uint8_t *tdo) {
|
||||
uint32_t i_val;
|
||||
uint32_t o_val;
|
||||
uint32_t bit;
|
||||
uint32_t n, k;
|
||||
|
||||
n = info & JTAG_SEQUENCE_TCK;
|
||||
if (n == 0U) { n = 64U; }
|
||||
|
||||
if (info & JTAG_SEQUENCE_TMS) {
|
||||
PIN_TMS_SET();
|
||||
} else {
|
||||
PIN_TMS_CLR();
|
||||
}
|
||||
|
||||
while (n) {
|
||||
i_val = *tdi++;
|
||||
o_val = 0U;
|
||||
for (k = 8U; k && n; k--, n--) {
|
||||
JTAG_CYCLE_TDIO(i_val, bit);
|
||||
i_val >>= 1;
|
||||
o_val >>= 1;
|
||||
o_val |= bit << 7;
|
||||
}
|
||||
o_val >>= k;
|
||||
if (info & JTAG_SEQUENCE_TDO) {
|
||||
*tdo++ = (uint8_t)o_val;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// JTAG Set IR
|
||||
// ir: IR value
|
||||
// return: none
|
||||
#define JTAG_IR_Function(speed) /**/ \
|
||||
void JTAG_IR_##speed (uint32_t ir) { \
|
||||
uint32_t n; \
|
||||
\
|
||||
PIN_TMS_SET(); \
|
||||
JTAG_CYCLE_TCK(); /* Select-DR-Scan */ \
|
||||
JTAG_CYCLE_TCK(); /* Select-IR-Scan */ \
|
||||
PIN_TMS_CLR(); \
|
||||
JTAG_CYCLE_TCK(); /* Capture-IR */ \
|
||||
JTAG_CYCLE_TCK(); /* Shift-IR */ \
|
||||
\
|
||||
PIN_TDI_OUT(1U); \
|
||||
for (n = DAP_Data.jtag_dev.ir_before[DAP_Data.jtag_dev.index]; n; n--) { \
|
||||
JTAG_CYCLE_TCK(); /* Bypass before data */ \
|
||||
} \
|
||||
for (n = DAP_Data.jtag_dev.ir_length[DAP_Data.jtag_dev.index] - 1U; n; n--) { \
|
||||
JTAG_CYCLE_TDI(ir); /* Set IR bits (except last) */ \
|
||||
ir >>= 1; \
|
||||
} \
|
||||
n = DAP_Data.jtag_dev.ir_after[DAP_Data.jtag_dev.index]; \
|
||||
if (n) { \
|
||||
JTAG_CYCLE_TDI(ir); /* Set last IR bit */ \
|
||||
PIN_TDI_OUT(1U); \
|
||||
for (--n; n; n--) { \
|
||||
JTAG_CYCLE_TCK(); /* Bypass after data */ \
|
||||
} \
|
||||
PIN_TMS_SET(); \
|
||||
JTAG_CYCLE_TCK(); /* Bypass & Exit1-IR */ \
|
||||
} else { \
|
||||
PIN_TMS_SET(); \
|
||||
JTAG_CYCLE_TDI(ir); /* Set last IR bit & Exit1-IR */ \
|
||||
} \
|
||||
\
|
||||
JTAG_CYCLE_TCK(); /* Update-IR */ \
|
||||
PIN_TMS_CLR(); \
|
||||
JTAG_CYCLE_TCK(); /* Idle */ \
|
||||
PIN_TDI_OUT(1U); \
|
||||
}
|
||||
|
||||
|
||||
// JTAG Transfer I/O
|
||||
// request: A[3:2] RnW APnDP
|
||||
// data: DATA[31:0]
|
||||
// return: ACK[2:0]
|
||||
#define JTAG_TransferFunction(speed) /**/ \
|
||||
uint8_t JTAG_Transfer##speed (uint32_t request, uint32_t *data) { \
|
||||
uint32_t ack; \
|
||||
uint32_t bit; \
|
||||
uint32_t val; \
|
||||
uint32_t n; \
|
||||
\
|
||||
PIN_TMS_SET(); \
|
||||
JTAG_CYCLE_TCK(); /* Select-DR-Scan */ \
|
||||
PIN_TMS_CLR(); \
|
||||
JTAG_CYCLE_TCK(); /* Capture-DR */ \
|
||||
JTAG_CYCLE_TCK(); /* Shift-DR */ \
|
||||
\
|
||||
for (n = DAP_Data.jtag_dev.index; n; n--) { \
|
||||
JTAG_CYCLE_TCK(); /* Bypass before data */ \
|
||||
} \
|
||||
\
|
||||
JTAG_CYCLE_TDIO(request >> 1, bit); /* Set RnW, Get ACK.0 */ \
|
||||
ack = bit << 1; \
|
||||
JTAG_CYCLE_TDIO(request >> 2, bit); /* Set A2, Get ACK.1 */ \
|
||||
ack |= bit << 0; \
|
||||
JTAG_CYCLE_TDIO(request >> 3, bit); /* Set A3, Get ACK.2 */ \
|
||||
ack |= bit << 2; \
|
||||
\
|
||||
if (ack != DAP_TRANSFER_OK) { \
|
||||
/* Exit on error */ \
|
||||
PIN_TMS_SET(); \
|
||||
JTAG_CYCLE_TCK(); /* Exit1-DR */ \
|
||||
goto exit; \
|
||||
} \
|
||||
\
|
||||
if (request & DAP_TRANSFER_RnW) { \
|
||||
/* Read Transfer */ \
|
||||
val = 0U; \
|
||||
for (n = 31U; n; n--) { \
|
||||
JTAG_CYCLE_TDO(bit); /* Get D0..D30 */ \
|
||||
val |= bit << 31; \
|
||||
val >>= 1; \
|
||||
} \
|
||||
n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1U; \
|
||||
if (n) { \
|
||||
JTAG_CYCLE_TDO(bit); /* Get D31 */ \
|
||||
for (--n; n; n--) { \
|
||||
JTAG_CYCLE_TCK(); /* Bypass after data */ \
|
||||
} \
|
||||
PIN_TMS_SET(); \
|
||||
JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */ \
|
||||
} else { \
|
||||
PIN_TMS_SET(); \
|
||||
JTAG_CYCLE_TDO(bit); /* Get D31 & Exit1-DR */ \
|
||||
} \
|
||||
val |= bit << 31; \
|
||||
if (data) { *data = val; } \
|
||||
} else { \
|
||||
/* Write Transfer */ \
|
||||
val = *data; \
|
||||
for (n = 31U; n; n--) { \
|
||||
JTAG_CYCLE_TDI(val); /* Set D0..D30 */ \
|
||||
val >>= 1; \
|
||||
} \
|
||||
n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1u; \
|
||||
if (n) { \
|
||||
JTAG_CYCLE_TDI(val); /* Set D31 */ \
|
||||
for (--n; n; n--) { \
|
||||
JTAG_CYCLE_TCK(); /* Bypass after data */ \
|
||||
} \
|
||||
PIN_TMS_SET(); \
|
||||
JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */ \
|
||||
} else { \
|
||||
PIN_TMS_SET(); \
|
||||
JTAG_CYCLE_TDI(val); /* Set D31 & Exit1-DR */ \
|
||||
} \
|
||||
} \
|
||||
\
|
||||
exit: \
|
||||
JTAG_CYCLE_TCK(); /* Update-DR */ \
|
||||
PIN_TMS_CLR(); \
|
||||
JTAG_CYCLE_TCK(); /* Idle */ \
|
||||
PIN_TDI_OUT(1U); \
|
||||
\
|
||||
/* Idle cycles */ \
|
||||
n = DAP_Data.transfer.idle_cycles; \
|
||||
while (n--) { \
|
||||
JTAG_CYCLE_TCK(); /* Idle */ \
|
||||
} \
|
||||
\
|
||||
return ((uint8_t)ack); \
|
||||
}
|
||||
|
||||
|
||||
#undef PIN_DELAY
|
||||
#define PIN_DELAY() PIN_DELAY_FAST()
|
||||
JTAG_IR_Function(Fast);
|
||||
JTAG_TransferFunction(Fast);
|
||||
|
||||
#undef PIN_DELAY
|
||||
#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
|
||||
JTAG_IR_Function(Slow);
|
||||
JTAG_TransferFunction(Slow);
|
||||
|
||||
|
||||
// JTAG Read IDCODE register
|
||||
// return: value read
|
||||
uint32_t JTAG_ReadIDCode (void) {
|
||||
uint32_t bit;
|
||||
uint32_t val;
|
||||
uint32_t n;
|
||||
|
||||
PIN_TMS_SET();
|
||||
JTAG_CYCLE_TCK(); /* Select-DR-Scan */
|
||||
PIN_TMS_CLR();
|
||||
JTAG_CYCLE_TCK(); /* Capture-DR */
|
||||
JTAG_CYCLE_TCK(); /* Shift-DR */
|
||||
|
||||
for (n = DAP_Data.jtag_dev.index; n; n--) {
|
||||
JTAG_CYCLE_TCK(); /* Bypass before data */
|
||||
}
|
||||
|
||||
val = 0U;
|
||||
for (n = 31U; n; n--) {
|
||||
JTAG_CYCLE_TDO(bit); /* Get D0..D30 */
|
||||
val |= bit << 31;
|
||||
val >>= 1;
|
||||
}
|
||||
PIN_TMS_SET();
|
||||
JTAG_CYCLE_TDO(bit); /* Get D31 & Exit1-DR */
|
||||
val |= bit << 31;
|
||||
|
||||
JTAG_CYCLE_TCK(); /* Update-DR */
|
||||
PIN_TMS_CLR();
|
||||
JTAG_CYCLE_TCK(); /* Idle */
|
||||
|
||||
return (val);
|
||||
}
|
||||
|
||||
|
||||
// JTAG Write ABORT register
|
||||
// data: value to write
|
||||
// return: none
|
||||
void JTAG_WriteAbort (uint32_t data) {
|
||||
uint32_t n;
|
||||
|
||||
PIN_TMS_SET();
|
||||
JTAG_CYCLE_TCK(); /* Select-DR-Scan */
|
||||
PIN_TMS_CLR();
|
||||
JTAG_CYCLE_TCK(); /* Capture-DR */
|
||||
JTAG_CYCLE_TCK(); /* Shift-DR */
|
||||
|
||||
for (n = DAP_Data.jtag_dev.index; n; n--) {
|
||||
JTAG_CYCLE_TCK(); /* Bypass before data */
|
||||
}
|
||||
|
||||
PIN_TDI_OUT(0U);
|
||||
JTAG_CYCLE_TCK(); /* Set RnW=0 (Write) */
|
||||
JTAG_CYCLE_TCK(); /* Set A2=0 */
|
||||
JTAG_CYCLE_TCK(); /* Set A3=0 */
|
||||
|
||||
for (n = 31U; n; n--) {
|
||||
JTAG_CYCLE_TDI(data); /* Set D0..D30 */
|
||||
data >>= 1;
|
||||
}
|
||||
n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1u;
|
||||
if (n) {
|
||||
JTAG_CYCLE_TDI(data); /* Set D31 */
|
||||
for (--n; n; n--) {
|
||||
JTAG_CYCLE_TCK(); /* Bypass after data */
|
||||
}
|
||||
PIN_TMS_SET();
|
||||
JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */
|
||||
} else {
|
||||
PIN_TMS_SET();
|
||||
JTAG_CYCLE_TDI(data); /* Set D31 & Exit1-DR */
|
||||
}
|
||||
|
||||
JTAG_CYCLE_TCK(); /* Update-DR */
|
||||
PIN_TMS_CLR();
|
||||
JTAG_CYCLE_TCK(); /* Idle */
|
||||
PIN_TDI_OUT(1U);
|
||||
}
|
||||
|
||||
|
||||
// JTAG Set IR
|
||||
// ir: IR value
|
||||
// return: none
|
||||
void JTAG_IR (uint32_t ir) {
|
||||
if (DAP_Data.fast_clock) {
|
||||
JTAG_IR_Fast(ir);
|
||||
} else {
|
||||
JTAG_IR_Slow(ir);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// JTAG Transfer I/O
|
||||
// request: A[3:2] RnW APnDP
|
||||
// data: DATA[31:0]
|
||||
// return: ACK[2:0]
|
||||
uint8_t JTAG_Transfer(uint32_t request, uint32_t *data) {
|
||||
if (DAP_Data.fast_clock) {
|
||||
return JTAG_TransferFast(request, data);
|
||||
} else {
|
||||
return JTAG_TransferSlow(request, data);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#endif /* (DAP_JTAG != 0) */
|
||||
603
PAN159/PAN159-Template/Library/CMSIS/DAP/Firmware/Source/SWO.c
Normal file
603
PAN159/PAN159-Template/Library/CMSIS/DAP/Firmware/Source/SWO.c
Normal file
@ -0,0 +1,603 @@
|
||||
/******************************************************************************
|
||||
* @file SWO.c
|
||||
* @brief CMSIS-DAP SWO I/O
|
||||
* @version V1.00
|
||||
* @date 20. May 2015
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "DAP_config.h"
|
||||
#include "DAP.h"
|
||||
#if (SWO_UART != 0)
|
||||
#include "Driver_USART.h"
|
||||
#endif
|
||||
|
||||
|
||||
#if (SWO_UART != 0)
|
||||
|
||||
#ifndef USART_PORT
|
||||
#define USART_PORT 0 /* USART Port Number */
|
||||
#endif
|
||||
|
||||
// USART Driver
|
||||
#define _USART_Driver_(n) Driver_USART##n
|
||||
#define USART_Driver_(n) _USART_Driver_(n)
|
||||
extern ARM_DRIVER_USART USART_Driver_(USART_PORT);
|
||||
#define pUSART (&USART_Driver_(USART_PORT))
|
||||
|
||||
static uint8_t USART_Ready;
|
||||
|
||||
#endif /* (SWO_UART != 0) */
|
||||
|
||||
|
||||
#if ((SWO_UART != 0) || (SWO_MANCHESTER != 0))
|
||||
|
||||
|
||||
// Trace State
|
||||
static uint8_t TraceTransport = 0U; /* Trace Transport */
|
||||
static uint8_t TraceMode = 0U; /* Trace Mode */
|
||||
static uint8_t TraceStatus = 0U; /* Trace Status without Errors */
|
||||
static uint8_t TraceError[2] = {0U, 0U}; /* Trace Error flags (banked) */
|
||||
static uint8_t TraceError_n = 0U; /* Active Trace Error bank */
|
||||
|
||||
// Trace Buffer
|
||||
static uint8_t TraceBuf[SWO_BUFFER_SIZE]; /* Trace Buffer (must be 2^n) */
|
||||
static volatile uint32_t TraceIn = 0U; /* Incoming Trace Index */
|
||||
static volatile uint32_t TraceOut = 0U; /* Outgoing Trace Index */
|
||||
static volatile uint32_t TracePending = 0U; /* Pending Trace Count */
|
||||
|
||||
// Trace Helper functions
|
||||
static void ClearTrace (void);
|
||||
static uint32_t GetTraceSpace (void);
|
||||
static uint32_t GetTraceCount (void);
|
||||
static uint8_t GetTraceStatus (void);
|
||||
static void SetTraceError (uint8_t flag);
|
||||
|
||||
|
||||
#if (SWO_UART != 0)
|
||||
|
||||
// USART Driver Callback function
|
||||
// event: event mask
|
||||
static void USART_Callback (uint32_t event) {
|
||||
uint32_t count;
|
||||
|
||||
if (event & ARM_USART_EVENT_RECEIVE_COMPLETE) {
|
||||
TracePending = 0U;
|
||||
TraceIn += pUSART->GetRxCount();
|
||||
count = GetTraceSpace();
|
||||
if (count != 0U) {
|
||||
pUSART->Receive(&TraceBuf[TraceIn & (SWO_BUFFER_SIZE-1U)], count);
|
||||
} else {
|
||||
TraceStatus = DAP_SWO_CAPTURE_ACTIVE | DAP_SWO_CAPTURE_PAUSED;
|
||||
}
|
||||
}
|
||||
if (event & ARM_USART_EVENT_RX_OVERFLOW) {
|
||||
SetTraceError(DAP_SWO_BUFFER_OVERRUN);
|
||||
}
|
||||
if (event & (ARM_USART_EVENT_RX_BREAK |
|
||||
ARM_USART_EVENT_RX_FRAMING_ERROR |
|
||||
ARM_USART_EVENT_RX_PARITY_ERROR)) {
|
||||
SetTraceError(DAP_SWO_STREAM_ERROR);
|
||||
}
|
||||
}
|
||||
|
||||
// Enable or disable UART SWO Mode
|
||||
// enable: enable flag
|
||||
// return: 1 - Success, 0 - Error
|
||||
__weak uint32_t UART_SWO_Mode (uint32_t enable) {
|
||||
int32_t status;
|
||||
|
||||
USART_Ready = 0U;
|
||||
|
||||
if (enable) {
|
||||
status = pUSART->Initialize(USART_Callback);
|
||||
if (status != ARM_DRIVER_OK) { return (0U); }
|
||||
status = pUSART->PowerControl(ARM_POWER_FULL);
|
||||
if (status != ARM_DRIVER_OK) {
|
||||
pUSART->Uninitialize();
|
||||
return (0U);
|
||||
}
|
||||
} else {
|
||||
pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U);
|
||||
pUSART->PowerControl(ARM_POWER_OFF);
|
||||
pUSART->Uninitialize();
|
||||
}
|
||||
return (1U);
|
||||
}
|
||||
|
||||
// Configure UART SWO Baudrate
|
||||
// baudrate: requested baudrate
|
||||
// return: actual baudrate or 0 when not configured
|
||||
__weak uint32_t UART_SWO_Baudrate (uint32_t baudrate) {
|
||||
int32_t status;
|
||||
uint32_t count;
|
||||
|
||||
if (baudrate > SWO_UART_MAX_BAUDRATE) {
|
||||
baudrate = SWO_UART_MAX_BAUDRATE;
|
||||
}
|
||||
|
||||
if (TraceStatus & DAP_SWO_CAPTURE_ACTIVE) {
|
||||
pUSART->Control(ARM_USART_CONTROL_RX, 0U);
|
||||
if (pUSART->GetStatus().rx_busy) {
|
||||
TracePending = 0U;
|
||||
TraceIn += pUSART->GetRxCount();
|
||||
pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U);
|
||||
}
|
||||
}
|
||||
|
||||
status = pUSART->Control(ARM_USART_MODE_ASYNCHRONOUS |
|
||||
ARM_USART_DATA_BITS_8 |
|
||||
ARM_USART_PARITY_NONE |
|
||||
ARM_USART_STOP_BITS_1,
|
||||
baudrate);
|
||||
|
||||
if (status == ARM_DRIVER_OK) {
|
||||
USART_Ready = 1U;
|
||||
} else {
|
||||
USART_Ready = 0U;
|
||||
baudrate = 0U;
|
||||
}
|
||||
|
||||
if ((TraceStatus & DAP_SWO_CAPTURE_ACTIVE) && USART_Ready) {
|
||||
pUSART->Control(ARM_USART_CONTROL_RX, 1U);
|
||||
count = GetTraceSpace();
|
||||
if (count != 0U) {
|
||||
pUSART->Receive(&TraceBuf[TraceIn & (SWO_BUFFER_SIZE-1U)], count);
|
||||
} else {
|
||||
TraceStatus = DAP_SWO_CAPTURE_ACTIVE | DAP_SWO_CAPTURE_PAUSED;
|
||||
}
|
||||
}
|
||||
|
||||
return (baudrate);
|
||||
}
|
||||
|
||||
// Control UART SWO Capture
|
||||
// active: active flag
|
||||
// return: 1 - Success, 0 - Error
|
||||
__weak uint32_t UART_SWO_Control (uint32_t active) {
|
||||
int32_t status;
|
||||
|
||||
if (active) {
|
||||
if (!USART_Ready) { return (0U); }
|
||||
status = pUSART->Control(ARM_USART_CONTROL_RX, 1U);
|
||||
if (status != ARM_DRIVER_OK) { return (0U); }
|
||||
status = pUSART->Receive(TraceBuf, SWO_BUFFER_SIZE);
|
||||
if (status != ARM_DRIVER_OK) { return (0U); }
|
||||
} else {
|
||||
pUSART->Control(ARM_USART_CONTROL_RX, 0U);
|
||||
if (pUSART->GetStatus().rx_busy) {
|
||||
TracePending = 0U;
|
||||
TraceIn += pUSART->GetRxCount();
|
||||
pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U);
|
||||
}
|
||||
}
|
||||
return (1U);
|
||||
}
|
||||
|
||||
// Start UART SWO Capture
|
||||
// buf: pointer to buffer for capturing
|
||||
// count: number of bytes to capture
|
||||
__weak void UART_SWO_Capture (uint8_t *buf, uint32_t count) {
|
||||
pUSART->Receive(buf, count);
|
||||
}
|
||||
|
||||
// Update UART SWO Trace Info
|
||||
__weak void UART_SWO_Update (void) {
|
||||
TracePending = pUSART->GetRxCount();
|
||||
}
|
||||
|
||||
#endif /* (SWO_UART != 0) */
|
||||
|
||||
|
||||
#if (SWO_MANCHESTER != 0)
|
||||
|
||||
// Enable or disable Manchester SWO Mode
|
||||
// enable: enable flag
|
||||
// return: 1 - Success, 0 - Error
|
||||
__weak uint32_t Manchester_SWO_Mode (uint32_t enable) {
|
||||
return (0U);
|
||||
}
|
||||
|
||||
// Configure Manchester SWO Baudrate
|
||||
// baudrate: requested baudrate
|
||||
// return: actual baudrate or 0 when not configured
|
||||
__weak uint32_t Manchester_SWO_Baudrate (uint32_t baudrate) {
|
||||
return (0U);
|
||||
}
|
||||
|
||||
// Control Manchester SWO Capture
|
||||
// active: active flag
|
||||
// return: 1 - Success, 0 - Error
|
||||
__weak uint32_t Manchester_SWO_Control (uint32_t active) {
|
||||
return (0U);
|
||||
}
|
||||
|
||||
// Start Manchester SWO Capture
|
||||
// buf: pointer to buffer for capturing
|
||||
// count: number of bytes to capture
|
||||
__weak void Manchester_SWO_Capture (uint8_t *buf, uint32_t count) {
|
||||
}
|
||||
|
||||
// Update Manchester SWO Trace Info
|
||||
__weak void Manchester_SWO_Update (void) {
|
||||
}
|
||||
|
||||
#endif /* (SWO_MANCHESTER != 0) */
|
||||
|
||||
|
||||
// Clear Trace Errors and Data
|
||||
static void ClearTrace (void) {
|
||||
TraceError[0] = 0U;
|
||||
TraceError[1] = 0U;
|
||||
TraceError_n = 0U;
|
||||
TraceIn = 0U;
|
||||
TraceOut = 0U;
|
||||
TracePending = 0U;
|
||||
}
|
||||
|
||||
// Get Trace Space
|
||||
// return: number of contiguous free bytes in trace buffer
|
||||
static uint32_t GetTraceSpace (void) {
|
||||
uint32_t index;
|
||||
uint32_t limit;
|
||||
uint32_t count;
|
||||
|
||||
index = TraceIn & (SWO_BUFFER_SIZE-1U);
|
||||
limit = SWO_BUFFER_SIZE - index;
|
||||
count = SWO_BUFFER_SIZE - (TraceIn - TraceOut);
|
||||
if (count > limit) {
|
||||
count = limit;
|
||||
}
|
||||
|
||||
return (count);
|
||||
}
|
||||
|
||||
// Get Trace Count
|
||||
// return: number of available data bytes in trace buffer
|
||||
static uint32_t GetTraceCount (void) {
|
||||
uint32_t count;
|
||||
|
||||
if (TraceStatus == DAP_SWO_CAPTURE_ACTIVE) {
|
||||
count = (TraceIn - TraceOut) + TracePending;
|
||||
if (TracePending == 0U) {
|
||||
count = TraceIn - TraceOut;
|
||||
}
|
||||
} else {
|
||||
count = TraceIn - TraceOut;
|
||||
}
|
||||
|
||||
return (count);
|
||||
}
|
||||
|
||||
// Get Trace Status (clear Error flags)
|
||||
// return: Trace Status (Active flag and Error flags)
|
||||
static uint8_t GetTraceStatus (void) {
|
||||
uint8_t status;
|
||||
uint32_t n;
|
||||
|
||||
n = TraceError_n;
|
||||
TraceError_n ^= 1U;
|
||||
status = TraceStatus | TraceError[n];
|
||||
TraceError[n] = 0U;
|
||||
|
||||
return (status);
|
||||
}
|
||||
|
||||
// Set Trace Error flag(s)
|
||||
// flag: error flag(s) to set
|
||||
static void SetTraceError (uint8_t flag) {
|
||||
TraceError[TraceError_n] |= flag;
|
||||
}
|
||||
|
||||
|
||||
// Process SWO Transport command and prepare response
|
||||
// request: pointer to request data
|
||||
// response: pointer to response data
|
||||
// return: number of bytes in response (lower 16 bits)
|
||||
// number of bytes in request (upper 16 bits)
|
||||
uint32_t SWO_Transport (const uint8_t *request, uint8_t *response) {
|
||||
uint8_t transport;
|
||||
uint32_t result;
|
||||
|
||||
if (!(TraceStatus & DAP_SWO_CAPTURE_ACTIVE)) {
|
||||
transport = *request;
|
||||
switch (transport) {
|
||||
case 0:
|
||||
case 1:
|
||||
TraceTransport = transport;
|
||||
result = 1U;
|
||||
break;
|
||||
default:
|
||||
result = 0U;
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
result = 0U;
|
||||
}
|
||||
|
||||
if (result != 0U) {
|
||||
*response = DAP_OK;
|
||||
} else {
|
||||
*response = DAP_ERROR;
|
||||
}
|
||||
|
||||
return ((1U << 16) | 1U);
|
||||
}
|
||||
|
||||
|
||||
// Process SWO Mode command and prepare response
|
||||
// request: pointer to request data
|
||||
// response: pointer to response data
|
||||
// return: number of bytes in response (lower 16 bits)
|
||||
// number of bytes in request (upper 16 bits)
|
||||
uint32_t SWO_Mode (const uint8_t *request, uint8_t *response) {
|
||||
uint8_t mode;
|
||||
uint32_t result;
|
||||
|
||||
mode = *request;
|
||||
|
||||
switch (TraceMode) {
|
||||
#if (SWO_UART != 0)
|
||||
case DAP_SWO_UART:
|
||||
UART_SWO_Mode(0U);
|
||||
break;
|
||||
#endif
|
||||
#if (SWO_MANCHESTER != 0)
|
||||
case DAP_SWO_MANCHESTER:
|
||||
Manchester_SWO_Mode(0U);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
break;
|
||||
}
|
||||
switch (mode) {
|
||||
case DAP_SWO_OFF:
|
||||
result = 1U;
|
||||
break;
|
||||
#if (SWO_UART != 0)
|
||||
case DAP_SWO_UART:
|
||||
result = UART_SWO_Mode(1U);
|
||||
break;
|
||||
#endif
|
||||
#if (SWO_MANCHESTER != 0)
|
||||
case DAP_SWO_MANCHESTER:
|
||||
result = Manchester_SWO_Mode(1U);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = 0U;
|
||||
break;
|
||||
}
|
||||
if (result != 0U) {
|
||||
TraceMode = mode;
|
||||
} else {
|
||||
TraceMode = DAP_SWO_OFF;
|
||||
}
|
||||
TraceStatus = 0U;
|
||||
ClearTrace();
|
||||
|
||||
if (result != 0U) {
|
||||
*response = DAP_OK;
|
||||
} else {
|
||||
*response = DAP_ERROR;
|
||||
}
|
||||
|
||||
return ((1U << 16) | 1U);
|
||||
}
|
||||
|
||||
|
||||
// Process SWO Baudrate command and prepare response
|
||||
// request: pointer to request data
|
||||
// response: pointer to response data
|
||||
// return: number of bytes in response (lower 16 bits)
|
||||
// number of bytes in request (upper 16 bits)
|
||||
uint32_t SWO_Baudrate (const uint8_t *request, uint8_t *response) {
|
||||
uint32_t baudrate;
|
||||
|
||||
baudrate = (*(request+0) << 0) |
|
||||
(*(request+1) << 8) |
|
||||
(*(request+2) << 16) |
|
||||
(*(request+3) << 24);
|
||||
|
||||
switch (TraceMode) {
|
||||
#if (SWO_UART != 0)
|
||||
case DAP_SWO_UART:
|
||||
baudrate = UART_SWO_Baudrate(baudrate);
|
||||
break;
|
||||
#endif
|
||||
#if (SWO_MANCHESTER != 0)
|
||||
case DAP_SWO_MANCHESTER:
|
||||
baudrate = Manchester_SWO_Baudrate(baudrate);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
baudrate = 0U;
|
||||
break;
|
||||
}
|
||||
|
||||
if (baudrate == 0U) {
|
||||
TraceStatus = 0U;
|
||||
}
|
||||
|
||||
*response++ = (uint8_t)(baudrate >> 0);
|
||||
*response++ = (uint8_t)(baudrate >> 8);
|
||||
*response++ = (uint8_t)(baudrate >> 16);
|
||||
*response = (uint8_t)(baudrate >> 24);
|
||||
|
||||
return ((4U << 16) | 4U);
|
||||
}
|
||||
|
||||
|
||||
// Process SWO Control command and prepare response
|
||||
// request: pointer to request data
|
||||
// response: pointer to response data
|
||||
// return: number of bytes in response (lower 16 bits)
|
||||
// number of bytes in request (upper 16 bits)
|
||||
uint32_t SWO_Control (const uint8_t *request, uint8_t *response) {
|
||||
uint8_t active;
|
||||
uint32_t result;
|
||||
|
||||
active = *request & DAP_SWO_CAPTURE_ACTIVE;
|
||||
|
||||
if (active != (TraceStatus & DAP_SWO_CAPTURE_ACTIVE)) {
|
||||
if (active) {
|
||||
ClearTrace();
|
||||
}
|
||||
switch (TraceMode) {
|
||||
#if (SWO_UART != 0)
|
||||
case DAP_SWO_UART:
|
||||
result = UART_SWO_Control(active);
|
||||
break;
|
||||
#endif
|
||||
#if (SWO_MANCHESTER != 0)
|
||||
case DAP_SWO_MANCHESTER:
|
||||
result = Manchester_SWO_Control(active);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = 0U;
|
||||
break;
|
||||
}
|
||||
if (result != 0U) {
|
||||
TraceStatus = active;
|
||||
}
|
||||
} else {
|
||||
result = 1U;
|
||||
}
|
||||
|
||||
if (result != 0U) {
|
||||
*response = DAP_OK;
|
||||
} else {
|
||||
*response = DAP_ERROR;
|
||||
}
|
||||
|
||||
return ((1U << 16) | 1U);
|
||||
}
|
||||
|
||||
|
||||
// Process SWO Status command and prepare response
|
||||
// response: pointer to response data
|
||||
// return: number of bytes in response
|
||||
uint32_t SWO_Status (uint8_t *response) {
|
||||
uint8_t status;
|
||||
uint32_t count;
|
||||
|
||||
if (TraceStatus == DAP_SWO_CAPTURE_ACTIVE) {
|
||||
switch (TraceMode) {
|
||||
#if (SWO_UART != 0)
|
||||
case DAP_SWO_UART:
|
||||
UART_SWO_Update();
|
||||
break;
|
||||
#endif
|
||||
#if (SWO_MANCHESTER != 0)
|
||||
case DAP_SWO_MANCHESTER:
|
||||
Manchester_SWO_Update();
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
status = GetTraceStatus();
|
||||
count = GetTraceCount();
|
||||
|
||||
*response++ = status;
|
||||
*response++ = (uint8_t)(count >> 0);
|
||||
*response++ = (uint8_t)(count >> 8);
|
||||
*response++ = (uint8_t)(count >> 16);
|
||||
*response = (uint8_t)(count >> 24);
|
||||
|
||||
return (5U);
|
||||
}
|
||||
|
||||
|
||||
// Process SWO Data command and prepare response
|
||||
// request: pointer to request data
|
||||
// response: pointer to response data
|
||||
// return: number of bytes in response (lower 16 bits)
|
||||
// number of bytes in request (upper 16 bits)
|
||||
uint32_t SWO_Data (const uint8_t *request, uint8_t *response) {
|
||||
uint8_t status;
|
||||
uint32_t count;
|
||||
uint32_t n;
|
||||
|
||||
if (TraceStatus == DAP_SWO_CAPTURE_ACTIVE) {
|
||||
switch (TraceMode) {
|
||||
#if (SWO_UART != 0)
|
||||
case DAP_SWO_UART:
|
||||
UART_SWO_Update();
|
||||
break;
|
||||
#endif
|
||||
#if (SWO_MANCHESTER != 0)
|
||||
case DAP_SWO_MANCHESTER:
|
||||
Manchester_SWO_Update();
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
status = GetTraceStatus();
|
||||
count = GetTraceCount();
|
||||
|
||||
if (TraceTransport == 1U) {
|
||||
n = (*(request+0) << 0) |
|
||||
(*(request+1) << 8);
|
||||
} else {
|
||||
n = 0U;
|
||||
}
|
||||
if (count > n) {
|
||||
count = n;
|
||||
}
|
||||
|
||||
*response++ = status;
|
||||
*response++ = (uint8_t)(count >> 0);
|
||||
*response++ = (uint8_t)(count >> 8);
|
||||
|
||||
for (n = count; n; n--) {
|
||||
*response++ = TraceBuf[TraceOut++ & (SWO_BUFFER_SIZE-1U)];
|
||||
}
|
||||
|
||||
if (TraceStatus == (DAP_SWO_CAPTURE_ACTIVE | DAP_SWO_CAPTURE_PAUSED)) {
|
||||
n = GetTraceSpace();
|
||||
if (n != 0U) {
|
||||
switch (TraceMode) {
|
||||
#if (SWO_UART != 0)
|
||||
case DAP_SWO_UART:
|
||||
UART_SWO_Capture(&TraceBuf[TraceIn & (SWO_BUFFER_SIZE-1U)], n);
|
||||
TraceStatus = DAP_SWO_CAPTURE_ACTIVE;
|
||||
break;
|
||||
#endif
|
||||
#if (SWO_MANCHESTER != 0)
|
||||
case DAP_SWO_MANCHESTER:
|
||||
Manchester_SWO_Capture(&TraceBuf[TraceIn & (SWO_BUFFER_SIZE-1U)], n);
|
||||
TraceStatus = DAP_SWO_CAPTURE_ACTIVE;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return ((2U << 16) | (3U + count));
|
||||
}
|
||||
|
||||
|
||||
#endif /* ((SWO_UART != 0) || (SWO_MANCHESTER != 0)) */
|
||||
237
PAN159/PAN159-Template/Library/CMSIS/DAP/Firmware/Source/SW_DP.c
Normal file
237
PAN159/PAN159-Template/Library/CMSIS/DAP/Firmware/Source/SW_DP.c
Normal file
@ -0,0 +1,237 @@
|
||||
/******************************************************************************
|
||||
* @file SW_DP.c
|
||||
* @brief CMSIS-DAP SW DP I/O
|
||||
* @version V1.10
|
||||
* @date 20. May 2015
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2012-2015 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "DAP_config.h"
|
||||
#include "DAP.h"
|
||||
|
||||
|
||||
// SW Macros
|
||||
|
||||
#define PIN_SWCLK_SET PIN_SWCLK_TCK_SET
|
||||
#define PIN_SWCLK_CLR PIN_SWCLK_TCK_CLR
|
||||
|
||||
#define SW_CLOCK_CYCLE() \
|
||||
PIN_SWCLK_CLR(); \
|
||||
PIN_DELAY(); \
|
||||
PIN_SWCLK_SET(); \
|
||||
PIN_DELAY()
|
||||
|
||||
#define SW_WRITE_BIT(bit) \
|
||||
PIN_SWDIO_OUT(bit); \
|
||||
PIN_SWCLK_CLR(); \
|
||||
PIN_DELAY(); \
|
||||
PIN_SWCLK_SET(); \
|
||||
PIN_DELAY()
|
||||
|
||||
#define SW_READ_BIT(bit) \
|
||||
PIN_SWCLK_CLR(); \
|
||||
PIN_DELAY(); \
|
||||
bit = PIN_SWDIO_IN(); \
|
||||
PIN_SWCLK_SET(); \
|
||||
PIN_DELAY()
|
||||
|
||||
#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
|
||||
|
||||
|
||||
// Generate SWJ Sequence
|
||||
// count: sequence bit count
|
||||
// data: pointer to sequence bit data
|
||||
// return: none
|
||||
#if ((DAP_SWD != 0) || (DAP_JTAG != 0))
|
||||
void SWJ_Sequence (uint32_t count, const uint8_t *data) {
|
||||
uint32_t val;
|
||||
uint32_t n;
|
||||
|
||||
val = 0U;
|
||||
n = 0U;
|
||||
while (count--) {
|
||||
if (n == 0U) {
|
||||
val = *data++;
|
||||
n = 8U;
|
||||
}
|
||||
if (val & 1U) {
|
||||
PIN_SWDIO_TMS_SET();
|
||||
} else {
|
||||
PIN_SWDIO_TMS_CLR();
|
||||
}
|
||||
SW_CLOCK_CYCLE();
|
||||
val >>= 1;
|
||||
n--;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#if (DAP_SWD != 0)
|
||||
|
||||
|
||||
// SWD Transfer I/O
|
||||
// request: A[3:2] RnW APnDP
|
||||
// data: DATA[31:0]
|
||||
// return: ACK[2:0]
|
||||
#define SWD_TransferFunction(speed) /**/ \
|
||||
uint8_t SWD_Transfer##speed (uint32_t request, uint32_t *data) { \
|
||||
uint32_t ack; \
|
||||
uint32_t bit; \
|
||||
uint32_t val; \
|
||||
uint32_t parity; \
|
||||
\
|
||||
uint32_t n; \
|
||||
\
|
||||
/* Packet Request */ \
|
||||
parity = 0U; \
|
||||
SW_WRITE_BIT(1U); /* Start Bit */ \
|
||||
bit = request >> 0; \
|
||||
SW_WRITE_BIT(bit); /* APnDP Bit */ \
|
||||
parity += bit; \
|
||||
bit = request >> 1; \
|
||||
SW_WRITE_BIT(bit); /* RnW Bit */ \
|
||||
parity += bit; \
|
||||
bit = request >> 2; \
|
||||
SW_WRITE_BIT(bit); /* A2 Bit */ \
|
||||
parity += bit; \
|
||||
bit = request >> 3; \
|
||||
SW_WRITE_BIT(bit); /* A3 Bit */ \
|
||||
parity += bit; \
|
||||
SW_WRITE_BIT(parity); /* Parity Bit */ \
|
||||
SW_WRITE_BIT(0U); /* Stop Bit */ \
|
||||
SW_WRITE_BIT(1U); /* Park Bit */ \
|
||||
\
|
||||
/* Turnaround */ \
|
||||
PIN_SWDIO_OUT_DISABLE(); \
|
||||
for (n = DAP_Data.swd_conf.turnaround; n; n--) { \
|
||||
SW_CLOCK_CYCLE(); \
|
||||
} \
|
||||
\
|
||||
/* Acknowledge response */ \
|
||||
SW_READ_BIT(bit); \
|
||||
ack = bit << 0; \
|
||||
SW_READ_BIT(bit); \
|
||||
ack |= bit << 1; \
|
||||
SW_READ_BIT(bit); \
|
||||
ack |= bit << 2; \
|
||||
\
|
||||
if (ack == DAP_TRANSFER_OK) { /* OK response */ \
|
||||
/* Data transfer */ \
|
||||
if (request & DAP_TRANSFER_RnW) { \
|
||||
/* Read data */ \
|
||||
val = 0U; \
|
||||
parity = 0U; \
|
||||
for (n = 32U; n; n--) { \
|
||||
SW_READ_BIT(bit); /* Read RDATA[0:31] */ \
|
||||
parity += bit; \
|
||||
val >>= 1; \
|
||||
val |= bit << 31; \
|
||||
} \
|
||||
SW_READ_BIT(bit); /* Read Parity */ \
|
||||
if ((parity ^ bit) & 1U) { \
|
||||
ack = DAP_TRANSFER_ERROR; \
|
||||
} \
|
||||
if (data) { *data = val; } \
|
||||
/* Turnaround */ \
|
||||
for (n = DAP_Data.swd_conf.turnaround; n; n--) { \
|
||||
SW_CLOCK_CYCLE(); \
|
||||
} \
|
||||
PIN_SWDIO_OUT_ENABLE(); \
|
||||
} else { \
|
||||
/* Turnaround */ \
|
||||
for (n = DAP_Data.swd_conf.turnaround; n; n--) { \
|
||||
SW_CLOCK_CYCLE(); \
|
||||
} \
|
||||
PIN_SWDIO_OUT_ENABLE(); \
|
||||
/* Write data */ \
|
||||
val = *data; \
|
||||
parity = 0U; \
|
||||
for (n = 32U; n; n--) { \
|
||||
SW_WRITE_BIT(val); /* Write WDATA[0:31] */ \
|
||||
parity += val; \
|
||||
val >>= 1; \
|
||||
} \
|
||||
SW_WRITE_BIT(parity); /* Write Parity Bit */ \
|
||||
} \
|
||||
/* Idle cycles */ \
|
||||
n = DAP_Data.transfer.idle_cycles; \
|
||||
if (n) { \
|
||||
PIN_SWDIO_OUT(0U); \
|
||||
for (; n; n--) { \
|
||||
SW_CLOCK_CYCLE(); \
|
||||
} \
|
||||
} \
|
||||
PIN_SWDIO_OUT(1U); \
|
||||
return ((uint8_t)ack); \
|
||||
} \
|
||||
\
|
||||
if ((ack == DAP_TRANSFER_WAIT) || (ack == DAP_TRANSFER_FAULT)) { \
|
||||
/* WAIT or FAULT response */ \
|
||||
if (DAP_Data.swd_conf.data_phase && ((request & DAP_TRANSFER_RnW) != 0U)) { \
|
||||
for (n = 32U+1U; n; n--) { \
|
||||
SW_CLOCK_CYCLE(); /* Dummy Read RDATA[0:31] + Parity */ \
|
||||
} \
|
||||
} \
|
||||
/* Turnaround */ \
|
||||
for (n = DAP_Data.swd_conf.turnaround; n; n--) { \
|
||||
SW_CLOCK_CYCLE(); \
|
||||
} \
|
||||
PIN_SWDIO_OUT_ENABLE(); \
|
||||
if (DAP_Data.swd_conf.data_phase && ((request & DAP_TRANSFER_RnW) == 0U)) { \
|
||||
PIN_SWDIO_OUT(0U); \
|
||||
for (n = 32U+1U; n; n--) { \
|
||||
SW_CLOCK_CYCLE(); /* Dummy Write WDATA[0:31] + Parity */ \
|
||||
} \
|
||||
} \
|
||||
PIN_SWDIO_OUT(1U); \
|
||||
return ((uint8_t)ack); \
|
||||
} \
|
||||
\
|
||||
/* Protocol error */ \
|
||||
for (n = DAP_Data.swd_conf.turnaround + 32U + 1U; n; n--) { \
|
||||
SW_CLOCK_CYCLE(); /* Back off data phase */ \
|
||||
} \
|
||||
PIN_SWDIO_OUT_ENABLE(); \
|
||||
PIN_SWDIO_OUT(1U); \
|
||||
return ((uint8_t)ack); \
|
||||
}
|
||||
|
||||
|
||||
#undef PIN_DELAY
|
||||
#define PIN_DELAY() PIN_DELAY_FAST()
|
||||
SWD_TransferFunction(Fast);
|
||||
|
||||
#undef PIN_DELAY
|
||||
#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
|
||||
SWD_TransferFunction(Slow);
|
||||
|
||||
|
||||
// SWD Transfer I/O
|
||||
// request: A[3:2] RnW APnDP
|
||||
// data: DATA[31:0]
|
||||
// return: ACK[2:0]
|
||||
uint8_t SWD_Transfer(uint32_t request, uint32_t *data) {
|
||||
if (DAP_Data.fast_clock) {
|
||||
return SWD_TransferFast(request, data);
|
||||
} else {
|
||||
return SWD_TransferSlow(request, data);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#endif /* (DAP_SWD != 0) */
|
||||
@ -0,0 +1,237 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
* MDK Middleware - Component ::USB:Device
|
||||
* Copyright (c) 2004-2014 ARM Germany GmbH. All rights reserved.
|
||||
*------------------------------------------------------------------------------
|
||||
* Name: USBD_User_HID_0.c
|
||||
* Purpose: USB Device Human Interface Device class (HID) User module
|
||||
* Rev.: V6.2
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* \addtogroup usbd_hidFunctions
|
||||
*
|
||||
* USBD_User_HID_0.c implements the application specific functionality of the
|
||||
* HID class and is used to receive and send data reports to the USB Host.
|
||||
*
|
||||
* The implementation must match the configuration file USBD_Config_HID_0.h.
|
||||
* The following values in USBD_Config_HID_0.h affect the user code:
|
||||
*
|
||||
* - 'Endpoint polling Interval' specifies the frequency of requests
|
||||
* initiated by USB Host for \ref USBD_HIDn_GetReport.
|
||||
*
|
||||
* - 'Number of Output Reports' configures the values for \em rid of
|
||||
* \ref USBD_HIDn_SetReport.
|
||||
*
|
||||
* - 'Number of Input Reports' configures the values for \em rid of
|
||||
* \ref USBD_HIDn_GetReport and \ref USBD_HID_GetReportTrigger.
|
||||
*
|
||||
* - 'Maximum Input Report Size' specifies the maximum value for:
|
||||
* - return of \ref USBD_HIDn_GetReport
|
||||
* - len of \ref USBD_HID_GetReportTrigger.
|
||||
*
|
||||
* - 'Maximum Output Report Size' specifies the maximum value for \em len
|
||||
* in \ref USBD_HIDn_SetReport for rtype=HID_REPORT_OUTPUT
|
||||
*
|
||||
* - 'Maximum Feature Report Size' specifies the maximum value for \em len
|
||||
* in \ref USBD_HIDn_SetReport for rtype=HID_REPORT_FEATURE
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
//! [code_USBD_User_HID]
|
||||
|
||||
#include <string.h>
|
||||
#define osObjectsExternal
|
||||
#include "cmsis_os.h"
|
||||
#include "osObjects.h"
|
||||
#include "rl_usb.h"
|
||||
#include "USB\USBD_Config_HID_0.h"
|
||||
#include "DAP_config.h"
|
||||
#include "DAP.h"
|
||||
|
||||
|
||||
#if (USBD_HID0_OUT_REPORT_MAX_SZ != DAP_PACKET_SIZE)
|
||||
#error "USB HID0 Output Report Size must match DAP Packet Size"
|
||||
#endif
|
||||
#if (USBD_HID0_IN_REPORT_MAX_SZ != DAP_PACKET_SIZE)
|
||||
#error "USB HID Input Report Size must match DAP Packet Size"
|
||||
#endif
|
||||
|
||||
static uint16_t USB_RequestIndexI; // Request Index In
|
||||
static uint16_t USB_RequestIndexO; // Request Index Out
|
||||
static uint16_t USB_RequestCountI; // Request Count In
|
||||
static uint16_t USB_RequestCountO; // Request Count Out
|
||||
|
||||
static uint16_t USB_ResponseIndexI; // Response Index In
|
||||
static uint16_t USB_ResponseIndexO; // Response Index Out
|
||||
static uint16_t USB_ResponseCountI; // Response Count In
|
||||
static uint16_t USB_ResponseCountO; // Response Count Out
|
||||
static uint8_t USB_ResponseIdle; // Response Idle Flag
|
||||
|
||||
static uint8_t USB_Request [DAP_PACKET_COUNT][DAP_PACKET_SIZE]; // Request Buffer
|
||||
static uint8_t USB_Response[DAP_PACKET_COUNT][DAP_PACKET_SIZE]; // Response Buffer
|
||||
|
||||
|
||||
// Called during USBD_Initialize to initialize the USB Device class.
|
||||
void USBD_HID0_Initialize (void) {
|
||||
// Initialize variables
|
||||
USB_RequestIndexI = 0U;
|
||||
USB_RequestIndexO = 0U;
|
||||
USB_RequestCountI = 0U;
|
||||
USB_RequestCountO = 0U;
|
||||
USB_ResponseIndexI = 0U;
|
||||
USB_ResponseIndexO = 0U;
|
||||
USB_ResponseCountI = 0U;
|
||||
USB_ResponseCountO = 0U;
|
||||
USB_ResponseIdle = 1U;
|
||||
}
|
||||
|
||||
|
||||
// Called during USBD_Uninitialize to de-initialize the USB Device class.
|
||||
void USBD_HID0_Uninitialize (void) {
|
||||
}
|
||||
|
||||
|
||||
// \brief Prepare HID Report data to send.
|
||||
// \param[in] rtype report type:
|
||||
// - HID_REPORT_INPUT = input report requested
|
||||
// - HID_REPORT_FEATURE = feature report requested
|
||||
// \param[in] req request type:
|
||||
// - USBD_HID_REQ_EP_CTRL = control endpoint request
|
||||
// - USBD_HID_REQ_PERIOD_UPDATE = idle period expiration request
|
||||
// - USBD_HID_REQ_EP_INT = previously sent report on interrupt endpoint request
|
||||
// \param[in] rid report ID (0 if only one report exists).
|
||||
// \param[out] buf buffer containing report data to send.
|
||||
// \return number of report data bytes prepared to send or invalid report requested.
|
||||
// - value >= 0: number of report data bytes prepared to send
|
||||
// - value = -1: invalid report requested
|
||||
int32_t USBD_HID0_GetReport (uint8_t rtype, uint8_t req, uint8_t rid, uint8_t *buf) {
|
||||
|
||||
switch (rtype) {
|
||||
case HID_REPORT_INPUT:
|
||||
switch (req) {
|
||||
case USBD_HID_REQ_EP_CTRL: // Explicit USB Host request via Control OUT Endpoint
|
||||
case USBD_HID_REQ_PERIOD_UPDATE: // Periodic USB Host request via Interrupt OUT Endpoint
|
||||
break;
|
||||
case USBD_HID_REQ_EP_INT: // Called after USBD_HID_GetReportTrigger to signal data obtained.
|
||||
if (USB_ResponseCountI != USB_ResponseCountO) {
|
||||
// Load data from response buffer to be sent back
|
||||
memcpy(buf, USB_Response[USB_ResponseIndexO], DAP_PACKET_SIZE);
|
||||
USB_ResponseIndexO++;
|
||||
if (USB_ResponseIndexO == DAP_PACKET_COUNT) {
|
||||
USB_ResponseIndexO = 0U;
|
||||
}
|
||||
USB_ResponseCountO++;
|
||||
return ((int32_t)DAP_PACKET_SIZE);
|
||||
} else {
|
||||
USB_ResponseIdle = 1U;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case HID_REPORT_FEATURE:
|
||||
break;
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
// \brief Process received HID Report data.
|
||||
// \param[in] rtype report type:
|
||||
// - HID_REPORT_OUTPUT = output report received
|
||||
// - HID_REPORT_FEATURE = feature report received
|
||||
// \param[in] req request type:
|
||||
// - USBD_HID_REQ_EP_CTRL = report received on control endpoint
|
||||
// - USBD_HID_REQ_EP_INT = report received on interrupt endpoint
|
||||
// \param[in] rid report ID (0 if only one report exists).
|
||||
// \param[in] buf buffer that receives report data.
|
||||
// \param[in] len length of received report data.
|
||||
// \return true received report data processed.
|
||||
// \return false received report data not processed or request not supported.
|
||||
bool USBD_HID0_SetReport (uint8_t rtype, uint8_t req, uint8_t rid, const uint8_t *buf, int32_t len) {
|
||||
|
||||
switch (rtype) {
|
||||
case HID_REPORT_OUTPUT:
|
||||
if (len == 0) { break; }
|
||||
if (buf[0] == ID_DAP_TransferAbort) {
|
||||
DAP_TransferAbort = 1U;
|
||||
break;
|
||||
}
|
||||
if ((uint16_t)(USB_RequestCountI - USB_RequestCountO) == DAP_PACKET_COUNT) {
|
||||
osSignalSet(HID0_ThreadId, 0x80);
|
||||
break; // Discard packet when buffer is full
|
||||
}
|
||||
// Store received data into request buffer
|
||||
memcpy(USB_Request[USB_RequestIndexI], buf, len);
|
||||
USB_RequestIndexI++;
|
||||
if (USB_RequestIndexI == DAP_PACKET_COUNT) {
|
||||
USB_RequestIndexI = 0U;
|
||||
}
|
||||
USB_RequestCountI++;
|
||||
osSignalSet(HID0_ThreadId, 0x01);
|
||||
break;
|
||||
case HID_REPORT_FEATURE:
|
||||
break;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
// HID0 Thread.
|
||||
void HID0_Thread (void const *arg) {
|
||||
osEvent evt;
|
||||
uint32_t n;
|
||||
|
||||
for (;;) {
|
||||
osSignalWait(0, osWaitForever);
|
||||
|
||||
// Process pending requests
|
||||
while (USB_RequestCountI != USB_RequestCountO) {
|
||||
|
||||
// Handle Queue Commands
|
||||
n = USB_RequestIndexO;
|
||||
while (USB_Request[n][0] == ID_DAP_QueueCommands) {
|
||||
USB_Request[n][0] = ID_DAP_ExecuteCommands;
|
||||
n++;
|
||||
if (n == DAP_PACKET_COUNT) {
|
||||
n = 0U;
|
||||
}
|
||||
if (n == USB_RequestIndexI) {
|
||||
evt = osSignalWait(0, osWaitForever);
|
||||
if (evt.value.signals & 0x80) { break; }
|
||||
}
|
||||
}
|
||||
|
||||
// Execute DAP Command (process request and prepare response)
|
||||
DAP_ExecuteCommand(USB_Request[USB_RequestIndexO], USB_Response[USB_ResponseIndexI]);
|
||||
|
||||
// Update Request Index and Count
|
||||
USB_RequestIndexO++;
|
||||
if (USB_RequestIndexO == DAP_PACKET_COUNT) {
|
||||
USB_RequestIndexO = 0U;
|
||||
}
|
||||
USB_RequestCountO++;
|
||||
|
||||
// Update Response Index and Count
|
||||
USB_ResponseIndexI++;
|
||||
if (USB_ResponseIndexI == DAP_PACKET_COUNT) {
|
||||
USB_ResponseIndexI = 0U;
|
||||
}
|
||||
USB_ResponseCountI++;
|
||||
|
||||
if (USB_ResponseIdle) {
|
||||
if (USB_ResponseCountI != USB_ResponseCountO) {
|
||||
// Load data from response buffer to be sent back
|
||||
n = USB_ResponseIndexO++;
|
||||
if (USB_ResponseIndexO == DAP_PACKET_COUNT) {
|
||||
USB_ResponseIndexO = 0U;
|
||||
}
|
||||
USB_ResponseCountO++;
|
||||
USB_ResponseIdle = 0U;
|
||||
USBD_HID_GetReportTrigger(0U, 0U, USB_Response[n], DAP_PACKET_SIZE);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//! [code_USBD_User_HID]
|
||||
@ -0,0 +1,50 @@
|
||||
/******************************************************************************
|
||||
* @file main.c
|
||||
* @brief CMSIS-DAP Main module
|
||||
* @version V1.10
|
||||
* @date 20. Jan 2015
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2012-2015 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "cmsis_os.h"
|
||||
#include "osObjects.h"
|
||||
#include "rl_usb.h"
|
||||
#include "DAP_config.h"
|
||||
#include "DAP.h"
|
||||
|
||||
// Main program
|
||||
int main (void) {
|
||||
|
||||
DAP_Setup(); // DAP Setup
|
||||
|
||||
USBD_Initialize(0U); // USB Device Initialization
|
||||
USBD_Connect(0U); // USB Device Connect
|
||||
|
||||
while (!USBD_Configured(0U)); // Wait for USB Device to configure
|
||||
|
||||
LED_CONNECTED_OUT(1U); // Turn on Debugger Connected LED
|
||||
LED_RUNNING_OUT(1U); // Turn on Target Running LED
|
||||
Delayms(500U); // Wait for 500ms
|
||||
LED_RUNNING_OUT(0U); // Turn off Target Running LED
|
||||
LED_CONNECTED_OUT(0U); // Turn off Debugger Connected LED
|
||||
|
||||
// Create HID Thread
|
||||
HID0_ThreadId = osThreadCreate(osThread(HID0_Thread), NULL);
|
||||
|
||||
osThreadSetPriority(osThreadGetId(), osPriorityIdle);
|
||||
for (;;); // Endless Loop
|
||||
}
|
||||
@ -0,0 +1,37 @@
|
||||
/******************************************************************************
|
||||
* @file osObjects.h
|
||||
* @brief CMSIS-DAP RTOS Objects
|
||||
* @version V1.10
|
||||
* @date 20. Jan 2015
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2012-2015 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __osObjects_h__
|
||||
#define __osObjects_h__
|
||||
|
||||
#include "cmsis_os.h"
|
||||
|
||||
#ifdef osObjectsExternal
|
||||
extern osThreadId HID0_ThreadId;
|
||||
#else
|
||||
osThreadId HID0_ThreadId;
|
||||
#endif
|
||||
|
||||
extern void HID0_Thread (void const *arg);
|
||||
osThreadDef(HID0_Thread, osPriorityNormal, 1U, 512U);
|
||||
|
||||
#endif /* __osObjects_h__ */
|
||||
@ -0,0 +1,4 @@
|
||||
CMSIS DSP_Lib example arm_class_marks_example for
|
||||
Cortex-M0, Cortex-M3 and Cortex-M4 with FPU
|
||||
|
||||
The example is configured for uVision Simulator
|
||||
@ -0,0 +1,253 @@
|
||||
;/**************************************************************************//**
|
||||
; * @file startup_ARMCM0.s
|
||||
; * @brief CMSIS Core Device Startup File for
|
||||
; * ARMCM0 Device Series
|
||||
; * @version V1.08
|
||||
; * @date 23. November 2012
|
||||
; *
|
||||
; * @note
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
;/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
; ---------------------------------------------------------------------------*/
|
||||
;/*
|
||||
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
;*/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000C00
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WDT_IRQHandler ; 0: Watchdog Timer
|
||||
DCD RTC_IRQHandler ; 1: Real Time Clock
|
||||
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
|
||||
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
|
||||
DCD MCIA_IRQHandler ; 4: MCIa
|
||||
DCD MCIB_IRQHandler ; 5: MCIb
|
||||
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
|
||||
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
|
||||
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
|
||||
DCD UART4_IRQHandler ; 9: UART4 - not connected
|
||||
DCD AACI_IRQHandler ; 10: AACI / AC97
|
||||
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
|
||||
DCD ENET_IRQHandler ; 12: Ethernet
|
||||
DCD USBDC_IRQHandler ; 13: USB Device
|
||||
DCD USBHC_IRQHandler ; 14: USB Host Controller
|
||||
DCD CHLCD_IRQHandler ; 15: Character LCD
|
||||
DCD FLEXRAY_IRQHandler ; 16: Flexray
|
||||
DCD CAN_IRQHandler ; 17: CAN
|
||||
DCD LIN_IRQHandler ; 18: LIN
|
||||
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
|
||||
DCD 0 ; 20: Reserved
|
||||
DCD 0 ; 21: Reserved
|
||||
DCD 0 ; 22: Reserved
|
||||
DCD 0 ; 23: Reserved
|
||||
DCD 0 ; 24: Reserved
|
||||
DCD 0 ; 25: Reserved
|
||||
DCD 0 ; 26: Reserved
|
||||
DCD 0 ; 27: Reserved
|
||||
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
|
||||
DCD 0 ; 29: Reserved - CPU FPGA
|
||||
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
|
||||
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT TIM0_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT MCIA_IRQHandler [WEAK]
|
||||
EXPORT MCIB_IRQHandler [WEAK]
|
||||
EXPORT UART0_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT UART2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT AACI_IRQHandler [WEAK]
|
||||
EXPORT CLCD_IRQHandler [WEAK]
|
||||
EXPORT ENET_IRQHandler [WEAK]
|
||||
EXPORT USBDC_IRQHandler [WEAK]
|
||||
EXPORT USBHC_IRQHandler [WEAK]
|
||||
EXPORT CHLCD_IRQHandler [WEAK]
|
||||
EXPORT FLEXRAY_IRQHandler [WEAK]
|
||||
EXPORT CAN_IRQHandler [WEAK]
|
||||
EXPORT LIN_IRQHandler [WEAK]
|
||||
EXPORT I2C_IRQHandler [WEAK]
|
||||
EXPORT CPU_CLCD_IRQHandler [WEAK]
|
||||
EXPORT SPI_IRQHandler [WEAK]
|
||||
|
||||
WDT_IRQHandler
|
||||
RTC_IRQHandler
|
||||
TIM0_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
MCIA_IRQHandler
|
||||
MCIB_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
AACI_IRQHandler
|
||||
CLCD_IRQHandler
|
||||
ENET_IRQHandler
|
||||
USBDC_IRQHandler
|
||||
USBHC_IRQHandler
|
||||
CHLCD_IRQHandler
|
||||
FLEXRAY_IRQHandler
|
||||
CAN_IRQHandler
|
||||
LIN_IRQHandler
|
||||
I2C_IRQHandler
|
||||
CPU_CLCD_IRQHandler
|
||||
SPI_IRQHandler
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
@ -0,0 +1,80 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_ARMCM0.c
|
||||
* @brief CMSIS Device System Source File for
|
||||
* ARMCM0 Device Series
|
||||
* @version V1.08
|
||||
* @date 23. November 2012
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#include "ARMCM0.h"
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __HSI ( 8000000UL)
|
||||
#define __XTAL ( 5000000UL) /* Oscillator frequency */
|
||||
|
||||
#define __SYSTEM_CLOCK (5*__XTAL)
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||
{
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
@ -0,0 +1,273 @@
|
||||
;/**************************************************************************//**
|
||||
; * @file startup_ARMCM3.s
|
||||
; * @brief CMSIS Core Device Startup File for
|
||||
; * ARMCM3 Device Series
|
||||
; * @version V1.08
|
||||
; * @date 23. November 2012
|
||||
; *
|
||||
; * @note
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
;/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
; ---------------------------------------------------------------------------*/
|
||||
;/*
|
||||
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
;*/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000C00
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WDT_IRQHandler ; 0: Watchdog Timer
|
||||
DCD RTC_IRQHandler ; 1: Real Time Clock
|
||||
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
|
||||
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
|
||||
DCD MCIA_IRQHandler ; 4: MCIa
|
||||
DCD MCIB_IRQHandler ; 5: MCIb
|
||||
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
|
||||
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
|
||||
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
|
||||
DCD UART4_IRQHandler ; 9: UART4 - not connected
|
||||
DCD AACI_IRQHandler ; 10: AACI / AC97
|
||||
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
|
||||
DCD ENET_IRQHandler ; 12: Ethernet
|
||||
DCD USBDC_IRQHandler ; 13: USB Device
|
||||
DCD USBHC_IRQHandler ; 14: USB Host Controller
|
||||
DCD CHLCD_IRQHandler ; 15: Character LCD
|
||||
DCD FLEXRAY_IRQHandler ; 16: Flexray
|
||||
DCD CAN_IRQHandler ; 17: CAN
|
||||
DCD LIN_IRQHandler ; 18: LIN
|
||||
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
|
||||
DCD 0 ; 20: Reserved
|
||||
DCD 0 ; 21: Reserved
|
||||
DCD 0 ; 22: Reserved
|
||||
DCD 0 ; 23: Reserved
|
||||
DCD 0 ; 24: Reserved
|
||||
DCD 0 ; 25: Reserved
|
||||
DCD 0 ; 26: Reserved
|
||||
DCD 0 ; 27: Reserved
|
||||
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
|
||||
DCD 0 ; 29: Reserved - CPU FPGA
|
||||
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
|
||||
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT TIM0_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT MCIA_IRQHandler [WEAK]
|
||||
EXPORT MCIB_IRQHandler [WEAK]
|
||||
EXPORT UART0_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT UART2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT AACI_IRQHandler [WEAK]
|
||||
EXPORT CLCD_IRQHandler [WEAK]
|
||||
EXPORT ENET_IRQHandler [WEAK]
|
||||
EXPORT USBDC_IRQHandler [WEAK]
|
||||
EXPORT USBHC_IRQHandler [WEAK]
|
||||
EXPORT CHLCD_IRQHandler [WEAK]
|
||||
EXPORT FLEXRAY_IRQHandler [WEAK]
|
||||
EXPORT CAN_IRQHandler [WEAK]
|
||||
EXPORT LIN_IRQHandler [WEAK]
|
||||
EXPORT I2C_IRQHandler [WEAK]
|
||||
EXPORT CPU_CLCD_IRQHandler [WEAK]
|
||||
EXPORT SPI_IRQHandler [WEAK]
|
||||
|
||||
WDT_IRQHandler
|
||||
RTC_IRQHandler
|
||||
TIM0_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
MCIA_IRQHandler
|
||||
MCIB_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
AACI_IRQHandler
|
||||
CLCD_IRQHandler
|
||||
ENET_IRQHandler
|
||||
USBDC_IRQHandler
|
||||
USBHC_IRQHandler
|
||||
CHLCD_IRQHandler
|
||||
FLEXRAY_IRQHandler
|
||||
CAN_IRQHandler
|
||||
LIN_IRQHandler
|
||||
I2C_IRQHandler
|
||||
CPU_CLCD_IRQHandler
|
||||
SPI_IRQHandler
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
@ -0,0 +1,84 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_ARMCM3.c
|
||||
* @brief CMSIS Device System Source File for
|
||||
* ARMCM3 Device Series
|
||||
* @version V1.08
|
||||
* @date 23. November 2012
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#include "ARMCM3.h"
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __HSI ( 8000000UL)
|
||||
#define __XTAL ( 5000000UL) /* Oscillator frequency */
|
||||
|
||||
#define __SYSTEM_CLOCK (5*__XTAL)
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||
{
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
|
||||
#ifdef UNALIGNED_SUPPORT_DISABLE
|
||||
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
|
||||
#endif
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
@ -0,0 +1,273 @@
|
||||
;/**************************************************************************//**
|
||||
; * @file startup_ARMCM4.s
|
||||
; * @brief CMSIS Core Device Startup File for
|
||||
; * ARMCM4 Device Series
|
||||
; * @version V1.08
|
||||
; * @date 23. November 2012
|
||||
; *
|
||||
; * @note
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
;/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
; ---------------------------------------------------------------------------*/
|
||||
;/*
|
||||
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
;*/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000C00
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WDT_IRQHandler ; 0: Watchdog Timer
|
||||
DCD RTC_IRQHandler ; 1: Real Time Clock
|
||||
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
|
||||
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
|
||||
DCD MCIA_IRQHandler ; 4: MCIa
|
||||
DCD MCIB_IRQHandler ; 5: MCIb
|
||||
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
|
||||
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
|
||||
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
|
||||
DCD UART4_IRQHandler ; 9: UART4 - not connected
|
||||
DCD AACI_IRQHandler ; 10: AACI / AC97
|
||||
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
|
||||
DCD ENET_IRQHandler ; 12: Ethernet
|
||||
DCD USBDC_IRQHandler ; 13: USB Device
|
||||
DCD USBHC_IRQHandler ; 14: USB Host Controller
|
||||
DCD CHLCD_IRQHandler ; 15: Character LCD
|
||||
DCD FLEXRAY_IRQHandler ; 16: Flexray
|
||||
DCD CAN_IRQHandler ; 17: CAN
|
||||
DCD LIN_IRQHandler ; 18: LIN
|
||||
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
|
||||
DCD 0 ; 20: Reserved
|
||||
DCD 0 ; 21: Reserved
|
||||
DCD 0 ; 22: Reserved
|
||||
DCD 0 ; 23: Reserved
|
||||
DCD 0 ; 24: Reserved
|
||||
DCD 0 ; 25: Reserved
|
||||
DCD 0 ; 26: Reserved
|
||||
DCD 0 ; 27: Reserved
|
||||
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
|
||||
DCD 0 ; 29: Reserved - CPU FPGA
|
||||
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
|
||||
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT TIM0_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT MCIA_IRQHandler [WEAK]
|
||||
EXPORT MCIB_IRQHandler [WEAK]
|
||||
EXPORT UART0_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT UART2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT AACI_IRQHandler [WEAK]
|
||||
EXPORT CLCD_IRQHandler [WEAK]
|
||||
EXPORT ENET_IRQHandler [WEAK]
|
||||
EXPORT USBDC_IRQHandler [WEAK]
|
||||
EXPORT USBHC_IRQHandler [WEAK]
|
||||
EXPORT CHLCD_IRQHandler [WEAK]
|
||||
EXPORT FLEXRAY_IRQHandler [WEAK]
|
||||
EXPORT CAN_IRQHandler [WEAK]
|
||||
EXPORT LIN_IRQHandler [WEAK]
|
||||
EXPORT I2C_IRQHandler [WEAK]
|
||||
EXPORT CPU_CLCD_IRQHandler [WEAK]
|
||||
EXPORT SPI_IRQHandler [WEAK]
|
||||
|
||||
WDT_IRQHandler
|
||||
RTC_IRQHandler
|
||||
TIM0_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
MCIA_IRQHandler
|
||||
MCIB_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
AACI_IRQHandler
|
||||
CLCD_IRQHandler
|
||||
ENET_IRQHandler
|
||||
USBDC_IRQHandler
|
||||
USBHC_IRQHandler
|
||||
CHLCD_IRQHandler
|
||||
FLEXRAY_IRQHandler
|
||||
CAN_IRQHandler
|
||||
LIN_IRQHandler
|
||||
I2C_IRQHandler
|
||||
CPU_CLCD_IRQHandler
|
||||
SPI_IRQHandler
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
@ -0,0 +1,93 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_ARMCM4.c
|
||||
* @brief CMSIS Device System Source File for
|
||||
* ARMCM4 Device Series
|
||||
* @version V1.09
|
||||
* @date 26. August 2014
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
#if defined (ARMCM4)
|
||||
#include "ARMCM4.h"
|
||||
#elif defined (ARMCM4_FP)
|
||||
#include "ARMCM4_FP.h"
|
||||
#else
|
||||
#error device not specified!
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __HSI ( 8000000UL)
|
||||
#define __XTAL ( 5000000UL) /* Oscillator frequency */
|
||||
|
||||
#define __SYSTEM_CLOCK (5*__XTAL)
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||
{
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
#if (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
|
||||
(3UL << 11*2) ); /* set CP11 Full Access */
|
||||
#endif
|
||||
|
||||
#ifdef UNALIGNED_SUPPORT_DISABLE
|
||||
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
|
||||
#endif
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
@ -0,0 +1,273 @@
|
||||
;/**************************************************************************//**
|
||||
; * @file startup_ARMCM7.s
|
||||
; * @brief CMSIS Core Device Startup File for
|
||||
; * ARMCM7 Device Series
|
||||
; * @version V1.00
|
||||
; * @date 22. August 2014
|
||||
; *
|
||||
; * @note
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
;/* Copyright (c) 2011 - 2014 ARM LIMITED
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
; ---------------------------------------------------------------------------*/
|
||||
;/*
|
||||
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
;*/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000C00
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WDT_IRQHandler ; 0: Watchdog Timer
|
||||
DCD RTC_IRQHandler ; 1: Real Time Clock
|
||||
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
|
||||
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
|
||||
DCD MCIA_IRQHandler ; 4: MCIa
|
||||
DCD MCIB_IRQHandler ; 5: MCIb
|
||||
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
|
||||
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
|
||||
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
|
||||
DCD UART4_IRQHandler ; 9: UART4 - not connected
|
||||
DCD AACI_IRQHandler ; 10: AACI / AC97
|
||||
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
|
||||
DCD ENET_IRQHandler ; 12: Ethernet
|
||||
DCD USBDC_IRQHandler ; 13: USB Device
|
||||
DCD USBHC_IRQHandler ; 14: USB Host Controller
|
||||
DCD CHLCD_IRQHandler ; 15: Character LCD
|
||||
DCD FLEXRAY_IRQHandler ; 16: Flexray
|
||||
DCD CAN_IRQHandler ; 17: CAN
|
||||
DCD LIN_IRQHandler ; 18: LIN
|
||||
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
|
||||
DCD 0 ; 20: Reserved
|
||||
DCD 0 ; 21: Reserved
|
||||
DCD 0 ; 22: Reserved
|
||||
DCD 0 ; 23: Reserved
|
||||
DCD 0 ; 24: Reserved
|
||||
DCD 0 ; 25: Reserved
|
||||
DCD 0 ; 26: Reserved
|
||||
DCD 0 ; 27: Reserved
|
||||
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
|
||||
DCD 0 ; 29: Reserved - CPU FPGA
|
||||
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
|
||||
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT TIM0_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT MCIA_IRQHandler [WEAK]
|
||||
EXPORT MCIB_IRQHandler [WEAK]
|
||||
EXPORT UART0_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT UART2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT AACI_IRQHandler [WEAK]
|
||||
EXPORT CLCD_IRQHandler [WEAK]
|
||||
EXPORT ENET_IRQHandler [WEAK]
|
||||
EXPORT USBDC_IRQHandler [WEAK]
|
||||
EXPORT USBHC_IRQHandler [WEAK]
|
||||
EXPORT CHLCD_IRQHandler [WEAK]
|
||||
EXPORT FLEXRAY_IRQHandler [WEAK]
|
||||
EXPORT CAN_IRQHandler [WEAK]
|
||||
EXPORT LIN_IRQHandler [WEAK]
|
||||
EXPORT I2C_IRQHandler [WEAK]
|
||||
EXPORT CPU_CLCD_IRQHandler [WEAK]
|
||||
EXPORT SPI_IRQHandler [WEAK]
|
||||
|
||||
WDT_IRQHandler
|
||||
RTC_IRQHandler
|
||||
TIM0_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
MCIA_IRQHandler
|
||||
MCIB_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
AACI_IRQHandler
|
||||
CLCD_IRQHandler
|
||||
ENET_IRQHandler
|
||||
USBDC_IRQHandler
|
||||
USBHC_IRQHandler
|
||||
CHLCD_IRQHandler
|
||||
FLEXRAY_IRQHandler
|
||||
CAN_IRQHandler
|
||||
LIN_IRQHandler
|
||||
I2C_IRQHandler
|
||||
CPU_CLCD_IRQHandler
|
||||
SPI_IRQHandler
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
@ -0,0 +1,102 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_ARMCM7.c
|
||||
* @brief CMSIS Device System Source File for
|
||||
* ARMCM7 Device Series
|
||||
* @version V1.00
|
||||
* @date 27. August 2014
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2011 - 2014 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined (ARMCM7)
|
||||
#include "ARMCM7.h"
|
||||
#elif defined (ARMCM7_SP)
|
||||
#include "ARMCM7_SP.h"
|
||||
#elif defined (ARMCM7_DP)
|
||||
#include "ARMCM7_DP.h"
|
||||
#else
|
||||
#error device not specified!
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __HSI ( 8000000UL)
|
||||
#define __XTAL ( 5000000UL) /* Oscillator frequency */
|
||||
|
||||
#define __SYSTEM_CLOCK (5*__XTAL)
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Core Clock Variable
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/* System Core Clock Frequency */
|
||||
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
#if (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
|
||||
(3UL << 11*2) ); /* set CP11 Full Access */
|
||||
#endif
|
||||
|
||||
#ifdef UNALIGNED_SUPPORT_DISABLE
|
||||
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
|
||||
#endif
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
@ -0,0 +1,14 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Component Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'arm_class_marks_example'
|
||||
* Target: 'ARMCM0'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@ -0,0 +1,15 @@
|
||||
|
||||
/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions
|
||||
|
||||
The file can be executed in the following way:
|
||||
1) manually from uVision command window (in debug mode) using command:
|
||||
INCLUIDE arm_class_marks_example.ini
|
||||
|
||||
*/
|
||||
|
||||
|
||||
// usual initialisation for target setup
|
||||
MAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash
|
||||
MAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM
|
||||
|
||||
|
||||
@ -0,0 +1,997 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>ARMCM0</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>10000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\ARMCM0_debug\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>7</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>1</uSim>
|
||||
<uTrg>0</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>0</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<nTsel>0</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile>.\arm_class_marks_example.ini</sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\UL2CM3.DLL</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0$Device\ARM\Flash\NEW_DEVICE.FLM))</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGDARM</Key>
|
||||
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMDBGFLAGS</Key>
|
||||
<Name>-T0</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint>
|
||||
<Bp>
|
||||
<Number>0</Number>
|
||||
<Type>0</Type>
|
||||
<LineNumber>155</LineNumber>
|
||||
<EnabledFlag>1</EnabledFlag>
|
||||
<Address>0</Address>
|
||||
<ByteObject>0</ByteObject>
|
||||
<HtxType>0</HtxType>
|
||||
<ManyObjects>0</ManyObjects>
|
||||
<SizeOfObject>0</SizeOfObject>
|
||||
<BreakByAccess>0</BreakByAccess>
|
||||
<BreakIfRCount>0</BreakIfRCount>
|
||||
<Filename>C:\working\ARM\PACK\ARM\CMSIS\DSP_Lib\Examples\arm_class_marks_example\ARM\RTE\Device\ARMCM7_DP\startup_ARMCM7.s</Filename>
|
||||
<ExecCommand></ExecCommand>
|
||||
<Expression></Expression>
|
||||
</Bp>
|
||||
<Bp>
|
||||
<Number>1</Number>
|
||||
<Type>0</Type>
|
||||
<LineNumber>155</LineNumber>
|
||||
<EnabledFlag>1</EnabledFlag>
|
||||
<Address>0</Address>
|
||||
<ByteObject>0</ByteObject>
|
||||
<HtxType>0</HtxType>
|
||||
<ManyObjects>0</ManyObjects>
|
||||
<SizeOfObject>0</SizeOfObject>
|
||||
<BreakByAccess>0</BreakByAccess>
|
||||
<BreakIfRCount>0</BreakIfRCount>
|
||||
<Filename>RTE\Device\ARMCM7_SP\startup_ARMCM7.s</Filename>
|
||||
<ExecCommand></ExecCommand>
|
||||
<Expression></Expression>
|
||||
</Bp>
|
||||
<Bp>
|
||||
<Number>2</Number>
|
||||
<Type>0</Type>
|
||||
<LineNumber>210</LineNumber>
|
||||
<EnabledFlag>1</EnabledFlag>
|
||||
<Address>0</Address>
|
||||
<ByteObject>0</ByteObject>
|
||||
<HtxType>0</HtxType>
|
||||
<ManyObjects>0</ManyObjects>
|
||||
<SizeOfObject>0</SizeOfObject>
|
||||
<BreakByAccess>0</BreakByAccess>
|
||||
<BreakIfRCount>0</BreakIfRCount>
|
||||
<Filename>.\arm_class_marks_example_f32.c</Filename>
|
||||
<ExecCommand></ExecCommand>
|
||||
<Expression></Expression>
|
||||
</Bp>
|
||||
</Breakpoint>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>1</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>1</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Target>
|
||||
<TargetName>ARMCM3</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>10000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\ARMCM3_debug\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>0</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>7</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>1</uSim>
|
||||
<uTrg>0</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>0</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<nTsel>0</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile>.\arm_class_marks_example.ini</sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\UL2CM3.DLL</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM))</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGDARM</Key>
|
||||
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMDBGFLAGS</Key>
|
||||
<Name>-T0</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint>
|
||||
<Bp>
|
||||
<Number>0</Number>
|
||||
<Type>0</Type>
|
||||
<LineNumber>155</LineNumber>
|
||||
<EnabledFlag>1</EnabledFlag>
|
||||
<Address>0</Address>
|
||||
<ByteObject>0</ByteObject>
|
||||
<HtxType>0</HtxType>
|
||||
<ManyObjects>0</ManyObjects>
|
||||
<SizeOfObject>0</SizeOfObject>
|
||||
<BreakByAccess>0</BreakByAccess>
|
||||
<BreakIfRCount>0</BreakIfRCount>
|
||||
<Filename>C:\working\ARM\PACK\ARM\CMSIS\DSP_Lib\Examples\arm_class_marks_example\ARM\RTE\Device\ARMCM7_DP\startup_ARMCM7.s</Filename>
|
||||
<ExecCommand></ExecCommand>
|
||||
<Expression></Expression>
|
||||
</Bp>
|
||||
<Bp>
|
||||
<Number>1</Number>
|
||||
<Type>0</Type>
|
||||
<LineNumber>155</LineNumber>
|
||||
<EnabledFlag>1</EnabledFlag>
|
||||
<Address>0</Address>
|
||||
<ByteObject>0</ByteObject>
|
||||
<HtxType>0</HtxType>
|
||||
<ManyObjects>0</ManyObjects>
|
||||
<SizeOfObject>0</SizeOfObject>
|
||||
<BreakByAccess>0</BreakByAccess>
|
||||
<BreakIfRCount>0</BreakIfRCount>
|
||||
<Filename>RTE\Device\ARMCM7_SP\startup_ARMCM7.s</Filename>
|
||||
<ExecCommand></ExecCommand>
|
||||
<Expression></Expression>
|
||||
</Bp>
|
||||
<Bp>
|
||||
<Number>2</Number>
|
||||
<Type>0</Type>
|
||||
<LineNumber>210</LineNumber>
|
||||
<EnabledFlag>1</EnabledFlag>
|
||||
<Address>0</Address>
|
||||
<ByteObject>0</ByteObject>
|
||||
<HtxType>0</HtxType>
|
||||
<ManyObjects>0</ManyObjects>
|
||||
<SizeOfObject>0</SizeOfObject>
|
||||
<BreakByAccess>0</BreakByAccess>
|
||||
<BreakIfRCount>0</BreakIfRCount>
|
||||
<Filename>.\arm_class_marks_example_f32.c</Filename>
|
||||
<ExecCommand></ExecCommand>
|
||||
<Expression></Expression>
|
||||
</Bp>
|
||||
</Breakpoint>
|
||||
<Tracepoint>
|
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File diff suppressed because it is too large
Load Diff
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|
||||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
|
||||
*
|
||||
* $Date: 16/06/16 3:42p $Revision: V1.4.0
|
||||
*
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_class_marks_example_f32.c
|
||||
*
|
||||
* Description: Example code to calculate Minimum, Maximum
|
||||
* Mean, std and variance of marks obtained in a class
|
||||
*
|
||||
* Target Processor: Cortex-M4/Cortex-M3
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
/**
|
||||
* @ingroup groupExamples
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ClassMarks Class Marks Example
|
||||
*
|
||||
* \par Description:
|
||||
* \par
|
||||
* Demonstrates the use the Maximum, Minimum, Mean, Standard Deviation, Variance
|
||||
* and Matrix functions to calculate statistical values of marks obtained in a class.
|
||||
*
|
||||
* \note This example also demonstrates the usage of static initialization.
|
||||
*
|
||||
* \par Variables Description:
|
||||
* \par
|
||||
* \li \c testMarks_f32 points to the marks scored by 20 students in 4 subjects
|
||||
* \li \c max_marks Maximum of all marks
|
||||
* \li \c min_marks Minimum of all marks
|
||||
* \li \c mean Mean of all marks
|
||||
* \li \c var Variance of the marks
|
||||
* \li \c std Standard deviation of the marks
|
||||
* \li \c numStudents Total number of students in the class
|
||||
*
|
||||
* \par CMSIS DSP Software Library Functions Used:
|
||||
* \par
|
||||
* - arm_mat_init_f32()
|
||||
* - arm_mat_mult_f32()
|
||||
* - arm_max_f32()
|
||||
* - arm_min_f32()
|
||||
* - arm_mean_f32()
|
||||
* - arm_std_f32()
|
||||
* - arm_var_f32()
|
||||
*
|
||||
* <b> Refer </b>
|
||||
* \link arm_class_marks_example_f32.c \endlink
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
/** \example arm_class_marks_example_f32.c
|
||||
*/
|
||||
#include "arm_math.h"
|
||||
|
||||
#define USE_STATIC_INIT
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
** Global defines
|
||||
** ------------------------------------------------------------------- */
|
||||
|
||||
#define TEST_LENGTH_SAMPLES (20*4)
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
** List of Marks scored by 20 students for 4 subjects
|
||||
** ------------------------------------------------------------------- */
|
||||
const float32_t testMarks_f32[TEST_LENGTH_SAMPLES] =
|
||||
{
|
||||
42.000000, 37.000000, 81.000000, 28.000000,
|
||||
83.000000, 72.000000, 36.000000, 38.000000,
|
||||
32.000000, 51.000000, 63.000000, 64.000000,
|
||||
97.000000, 82.000000, 95.000000, 90.000000,
|
||||
66.000000, 51.000000, 54.000000, 42.000000,
|
||||
67.000000, 56.000000, 45.000000, 57.000000,
|
||||
67.000000, 69.000000, 35.000000, 52.000000,
|
||||
29.000000, 81.000000, 58.000000, 47.000000,
|
||||
38.000000, 76.000000, 100.000000, 29.000000,
|
||||
33.000000, 47.000000, 29.000000, 50.000000,
|
||||
34.000000, 41.000000, 61.000000, 46.000000,
|
||||
52.000000, 50.000000, 48.000000, 36.000000,
|
||||
47.000000, 55.000000, 44.000000, 40.000000,
|
||||
100.000000, 94.000000, 84.000000, 37.000000,
|
||||
32.000000, 71.000000, 47.000000, 77.000000,
|
||||
31.000000, 50.000000, 49.000000, 35.000000,
|
||||
63.000000, 67.000000, 40.000000, 31.000000,
|
||||
29.000000, 68.000000, 61.000000, 38.000000,
|
||||
31.000000, 28.000000, 28.000000, 76.000000,
|
||||
55.000000, 33.000000, 29.000000, 39.000000
|
||||
};
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
* Number of subjects X 1
|
||||
* ------------------------------------------------------------------- */
|
||||
const float32_t testUnity_f32[4] =
|
||||
{
|
||||
1.000, 1.000, 1.000, 1.000
|
||||
};
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
** f32 Output buffer
|
||||
** ------------------------------------------------------------------- */
|
||||
static float32_t testOutput[TEST_LENGTH_SAMPLES];
|
||||
|
||||
|
||||
/* ------------------------------------------------------------------
|
||||
* Global defines
|
||||
*------------------------------------------------------------------- */
|
||||
#define NUMSTUDENTS 20
|
||||
#define NUMSUBJECTS 4
|
||||
|
||||
/* ------------------------------------------------------------------
|
||||
* Global variables
|
||||
*------------------------------------------------------------------- */
|
||||
|
||||
uint32_t numStudents = 20;
|
||||
uint32_t numSubjects = 4;
|
||||
float32_t max_marks, min_marks, mean, std, var;
|
||||
uint32_t student_num;
|
||||
|
||||
/* ----------------------------------------------------------------------------------
|
||||
* Main f32 test function. It returns maximum marks secured and student number
|
||||
* ------------------------------------------------------------------------------- */
|
||||
|
||||
int32_t main()
|
||||
{
|
||||
|
||||
#ifndef USE_STATIC_INIT
|
||||
|
||||
arm_matrix_instance_f32 srcA;
|
||||
arm_matrix_instance_f32 srcB;
|
||||
arm_matrix_instance_f32 dstC;
|
||||
|
||||
/* Input and output matrices initializations */
|
||||
arm_mat_init_f32(&srcA, numStudents, numSubjects, (float32_t *)testMarks_f32);
|
||||
arm_mat_init_f32(&srcB, numSubjects, 1, (float32_t *)testUnity_f32);
|
||||
arm_mat_init_f32(&dstC, numStudents, 1, testOutput);
|
||||
|
||||
#else
|
||||
|
||||
/* Static Initializations of Input and output matrix sizes and array */
|
||||
arm_matrix_instance_f32 srcA = {NUMSTUDENTS, NUMSUBJECTS, (float32_t *)testMarks_f32};
|
||||
arm_matrix_instance_f32 srcB = {NUMSUBJECTS, 1, (float32_t *)testUnity_f32};
|
||||
arm_matrix_instance_f32 dstC = {NUMSTUDENTS, 1, testOutput};
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
*Call the Matrix multiplication process function
|
||||
* ------------------------------------------------------------------- */
|
||||
arm_mat_mult_f32(&srcA, &srcB, &dstC);
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
** Call the Max function to calculate max marks among numStudents
|
||||
** ------------------------------------------------------------------- */
|
||||
arm_max_f32(testOutput, numStudents, &max_marks, &student_num);
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
** Call the Min function to calculate min marks among numStudents
|
||||
** ------------------------------------------------------------------- */
|
||||
arm_min_f32(testOutput, numStudents, &min_marks, &student_num);
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
** Call the Mean function to calculate mean
|
||||
** ------------------------------------------------------------------- */
|
||||
arm_mean_f32(testOutput, numStudents, &mean);
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
** Call the std function to calculate standard deviation
|
||||
** ------------------------------------------------------------------- */
|
||||
arm_std_f32(testOutput, numStudents, &std);
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
** Call the var function to calculate variance
|
||||
** ------------------------------------------------------------------- */
|
||||
arm_var_f32(testOutput, numStudents, &var);
|
||||
|
||||
while(1); /* main function does not return */
|
||||
}
|
||||
@ -0,0 +1,4 @@
|
||||
CMSIS DSP_Lib example arm_class_marks_example for
|
||||
Cortex-M0, Cortex-M3 and Cortex-M4 with FPU
|
||||
|
||||
The example is configured for uVision Simulator
|
||||
@ -0,0 +1,195 @@
|
||||
/* Linker script to configure memory regions. */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 /* 256k */
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x08000 /* 32k */
|
||||
}
|
||||
|
||||
/* Library configurations */
|
||||
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __copy_table_start__
|
||||
* __copy_table_end__
|
||||
* __zero_table_start__
|
||||
* __zero_table_end__
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
* __Vectors_End
|
||||
* __Vectors_Size
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
KEEP(*(.vectors))
|
||||
__Vectors_End = .;
|
||||
__Vectors_Size = __Vectors_End - __Vectors;
|
||||
__end__ = .;
|
||||
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
/* To copy multiple ROM to RAM sections,
|
||||
* uncomment .copy.table section and,
|
||||
* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
|
||||
/*
|
||||
.copy.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__copy_table_start__ = .;
|
||||
LONG (__etext)
|
||||
LONG (__data_start__)
|
||||
LONG (__data_end__ - __data_start__)
|
||||
LONG (__etext2)
|
||||
LONG (__data2_start__)
|
||||
LONG (__data2_end__ - __data2_start__)
|
||||
__copy_table_end__ = .;
|
||||
} > FLASH
|
||||
*/
|
||||
|
||||
/* To clear multiple BSS sections,
|
||||
* uncomment .zero.table section and,
|
||||
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
|
||||
/*
|
||||
.zero.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__zero_table_start__ = .;
|
||||
LONG (__bss_start__)
|
||||
LONG (__bss_end__ - __bss_start__)
|
||||
LONG (__bss2_start__)
|
||||
LONG (__bss2_end__ - __bss2_start__)
|
||||
__zero_table_end__ = .;
|
||||
} > FLASH
|
||||
*/
|
||||
|
||||
__etext = .;
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
} > RAM
|
||||
|
||||
.heap (COPY):
|
||||
{
|
||||
__HeapBase = .;
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
KEEP(*(.heap*))
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy (COPY):
|
||||
{
|
||||
KEEP(*(.stack*)) /* changed MG 30.05.14 */
|
||||
} > RAM
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Check if data + heap + stack exceeds RAM limit */
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||
}
|
||||
@ -0,0 +1,320 @@
|
||||
/* File: startup_ARMCM0.S
|
||||
* Purpose: startup file for Cortex-M0 devices. Should use with
|
||||
* GCC for ARM Embedded Processors
|
||||
* Version: V2.01
|
||||
* Date: 12 June 2014
|
||||
*
|
||||
*/
|
||||
/* Copyright (c) 2011 - 2014 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
.syntax unified
|
||||
.arch armv6-m
|
||||
|
||||
.section .stack
|
||||
.align 3
|
||||
#ifdef __STACK_SIZE
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.equ Stack_Size, 0x00000400
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#ifdef __HEAP_SIZE
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 0x00000C00
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .vectors
|
||||
.align 2
|
||||
.globl __Vectors
|
||||
__Vectors:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long SVC_Handler /* SVCall Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long PendSV_Handler /* PendSV Handler */
|
||||
.long SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External interrupts */
|
||||
.long WDT_IRQHandler /* 0: Watchdog Timer */
|
||||
.long RTC_IRQHandler /* 1: Real Time Clock */
|
||||
.long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
|
||||
.long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
|
||||
.long MCIA_IRQHandler /* 4: MCIa */
|
||||
.long MCIB_IRQHandler /* 5: MCIb */
|
||||
.long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
|
||||
.long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
|
||||
.long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
|
||||
.long UART4_IRQHandler /* 9: UART4 - not connected */
|
||||
.long AACI_IRQHandler /* 10: AACI / AC97 */
|
||||
.long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
|
||||
.long ENET_IRQHandler /* 12: Ethernet */
|
||||
.long USBDC_IRQHandler /* 13: USB Device */
|
||||
.long USBHC_IRQHandler /* 14: USB Host Controller */
|
||||
.long CHLCD_IRQHandler /* 15: Character LCD */
|
||||
.long FLEXRAY_IRQHandler /* 16: Flexray */
|
||||
.long CAN_IRQHandler /* 17: CAN */
|
||||
.long LIN_IRQHandler /* 18: LIN */
|
||||
.long I2C_IRQHandler /* 19: I2C ADC/DAC */
|
||||
.long 0 /* 20: Reserved */
|
||||
.long 0 /* 21: Reserved */
|
||||
.long 0 /* 22: Reserved */
|
||||
.long 0 /* 23: Reserved */
|
||||
.long 0 /* 24: Reserved */
|
||||
.long 0 /* 25: Reserved */
|
||||
.long 0 /* 26: Reserved */
|
||||
.long 0 /* 27: Reserved */
|
||||
.long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
|
||||
.long 0 /* 29: Reserved - CPU FPGA */
|
||||
.long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
|
||||
.long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
|
||||
|
||||
.size __Vectors, . - __Vectors
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 1
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
/* Firstly it copies data from read only memory to RAM. There are two schemes
|
||||
* to copy. One can copy more than one sections. Another can only copy
|
||||
* one section. The former scheme needs more instructions and read-only
|
||||
* data to implement than the latter.
|
||||
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
|
||||
|
||||
#ifdef __STARTUP_COPY_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of triplets, each of which specify:
|
||||
* offset 0: LMA of start of a section to copy from
|
||||
* offset 4: VMA of start of a section to copy to
|
||||
* offset 8: size of the section to copy. Must be multiply of 4
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r4, =__copy_table_start__
|
||||
ldr r5, =__copy_table_end__
|
||||
|
||||
.L_loop0:
|
||||
cmp r4, r5
|
||||
bge .L_loop0_done
|
||||
ldr r1, [r4]
|
||||
ldr r2, [r4, #4]
|
||||
ldr r3, [r4, #8]
|
||||
|
||||
.L_loop0_0:
|
||||
subs r3, #4
|
||||
blt .L_loop0_0_done
|
||||
ldr r0, [r1, r3]
|
||||
str r0, [r2, r3]
|
||||
b .L_loop0_0
|
||||
|
||||
.L_loop0_0_done:
|
||||
adds r4, #12
|
||||
b .L_loop0
|
||||
|
||||
.L_loop0_done:
|
||||
#else
|
||||
/* Single section scheme.
|
||||
*
|
||||
* The ranges of copy from/to are specified by following symbols
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to
|
||||
* __data_end__: VMA of end of the section to copy to
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__data_end__
|
||||
|
||||
subs r3, r2
|
||||
ble .L_loop1_done
|
||||
|
||||
.L_loop1:
|
||||
subs r3, #4
|
||||
ldr r0, [r1,r3]
|
||||
str r0, [r2,r3]
|
||||
bgt .L_loop1
|
||||
|
||||
.L_loop1_done:
|
||||
#endif /*__STARTUP_COPY_MULTIPLE */
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define this macro to enable it in this startup.
|
||||
*
|
||||
* There are two schemes too. One can clear multiple BSS sections. Another
|
||||
* can only clear one section. The former is more size expensive than the
|
||||
* latter.
|
||||
*
|
||||
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
|
||||
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of tuples specifying:
|
||||
* offset 0: Start of a BSS section
|
||||
* offset 4: Size of this BSS section. Must be multiply of 4
|
||||
*/
|
||||
ldr r3, =__zero_table_start__
|
||||
ldr r4, =__zero_table_end__
|
||||
|
||||
.L_loop2:
|
||||
cmp r3, r4
|
||||
bge .L_loop2_done
|
||||
ldr r1, [r3]
|
||||
ldr r2, [r3, #4]
|
||||
movs r0, 0
|
||||
|
||||
.L_loop2_0:
|
||||
subs r2, #4
|
||||
blt .L_loop2_0_done
|
||||
str r0, [r1, r2]
|
||||
b .L_loop2_0
|
||||
.L_loop2_0_done:
|
||||
|
||||
adds r3, #8
|
||||
b .L_loop2
|
||||
.L_loop2_done:
|
||||
#elif defined (__STARTUP_CLEAR_BSS)
|
||||
/* Single BSS section scheme.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* Both addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
|
||||
subs r2, r1
|
||||
ble .L_loop3_done
|
||||
|
||||
.L_loop3:
|
||||
subs r2, #4
|
||||
str r0, [r1, r2]
|
||||
bgt .L_loop3
|
||||
.L_loop3_done:
|
||||
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
|
||||
|
||||
#ifndef __NO_SYSTEM_INIT
|
||||
bl SystemInit
|
||||
#endif
|
||||
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
bl __START
|
||||
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_irq_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, Default_Handler
|
||||
.endm
|
||||
|
||||
def_irq_handler NMI_Handler
|
||||
def_irq_handler HardFault_Handler
|
||||
def_irq_handler SVC_Handler
|
||||
def_irq_handler PendSV_Handler
|
||||
def_irq_handler SysTick_Handler
|
||||
|
||||
def_irq_handler WDT_IRQHandler
|
||||
def_irq_handler RTC_IRQHandler
|
||||
def_irq_handler TIM0_IRQHandler
|
||||
def_irq_handler TIM2_IRQHandler
|
||||
def_irq_handler MCIA_IRQHandler
|
||||
def_irq_handler MCIB_IRQHandler
|
||||
def_irq_handler UART0_IRQHandler
|
||||
def_irq_handler UART1_IRQHandler
|
||||
def_irq_handler UART2_IRQHandler
|
||||
def_irq_handler UART3_IRQHandler
|
||||
def_irq_handler UART4_IRQHandler
|
||||
def_irq_handler AACI_IRQHandler
|
||||
def_irq_handler CLCD_IRQHandler
|
||||
def_irq_handler ENET_IRQHandler
|
||||
def_irq_handler USBDC_IRQHandler
|
||||
def_irq_handler USBHC_IRQHandler
|
||||
def_irq_handler CHLCD_IRQHandler
|
||||
def_irq_handler FLEXRAY_IRQHandler
|
||||
def_irq_handler CAN_IRQHandler
|
||||
def_irq_handler LIN_IRQHandler
|
||||
def_irq_handler I2C_IRQHandler
|
||||
def_irq_handler CPU_CLCD_IRQHandler
|
||||
def_irq_handler SPI_IRQHandler
|
||||
|
||||
.end
|
||||
@ -0,0 +1,314 @@
|
||||
/* File: startup_ARMCM3.S
|
||||
* Purpose: startup file for Cortex-M3 devices. Should use with
|
||||
* GCC for ARM Embedded Processors
|
||||
* Version: V2.01
|
||||
* Date: 12 June 2014
|
||||
*
|
||||
*/
|
||||
/* Copyright (c) 2011 - 2014 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
.syntax unified
|
||||
.arch armv7-m
|
||||
|
||||
.section .stack
|
||||
.align 3
|
||||
#ifdef __STACK_SIZE
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.equ Stack_Size, 0x00000400
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#ifdef __HEAP_SIZE
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 0x00000C00
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .vectors
|
||||
.align 2
|
||||
.globl __Vectors
|
||||
__Vectors:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
.long MemManage_Handler /* MPU Fault Handler */
|
||||
.long BusFault_Handler /* Bus Fault Handler */
|
||||
.long UsageFault_Handler /* Usage Fault Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long SVC_Handler /* SVCall Handler */
|
||||
.long DebugMon_Handler /* Debug Monitor Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long PendSV_Handler /* PendSV Handler */
|
||||
.long SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External interrupts */
|
||||
.long WDT_IRQHandler /* 0: Watchdog Timer */
|
||||
.long RTC_IRQHandler /* 1: Real Time Clock */
|
||||
.long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
|
||||
.long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
|
||||
.long MCIA_IRQHandler /* 4: MCIa */
|
||||
.long MCIB_IRQHandler /* 5: MCIb */
|
||||
.long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
|
||||
.long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
|
||||
.long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
|
||||
.long UART4_IRQHandler /* 9: UART4 - not connected */
|
||||
.long AACI_IRQHandler /* 10: AACI / AC97 */
|
||||
.long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
|
||||
.long ENET_IRQHandler /* 12: Ethernet */
|
||||
.long USBDC_IRQHandler /* 13: USB Device */
|
||||
.long USBHC_IRQHandler /* 14: USB Host Controller */
|
||||
.long CHLCD_IRQHandler /* 15: Character LCD */
|
||||
.long FLEXRAY_IRQHandler /* 16: Flexray */
|
||||
.long CAN_IRQHandler /* 17: CAN */
|
||||
.long LIN_IRQHandler /* 18: LIN */
|
||||
.long I2C_IRQHandler /* 19: I2C ADC/DAC */
|
||||
.long 0 /* 20: Reserved */
|
||||
.long 0 /* 21: Reserved */
|
||||
.long 0 /* 22: Reserved */
|
||||
.long 0 /* 23: Reserved */
|
||||
.long 0 /* 24: Reserved */
|
||||
.long 0 /* 25: Reserved */
|
||||
.long 0 /* 26: Reserved */
|
||||
.long 0 /* 27: Reserved */
|
||||
.long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
|
||||
.long 0 /* 29: Reserved - CPU FPGA */
|
||||
.long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
|
||||
.long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
|
||||
|
||||
.size __Vectors, . - __Vectors
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 2
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
/* Firstly it copies data from read only memory to RAM. There are two schemes
|
||||
* to copy. One can copy more than one sections. Another can only copy
|
||||
* one section. The former scheme needs more instructions and read-only
|
||||
* data to implement than the latter.
|
||||
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
|
||||
|
||||
#ifdef __STARTUP_COPY_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of triplets, each of which specify:
|
||||
* offset 0: LMA of start of a section to copy from
|
||||
* offset 4: VMA of start of a section to copy to
|
||||
* offset 8: size of the section to copy. Must be multiply of 4
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r4, =__copy_table_start__
|
||||
ldr r5, =__copy_table_end__
|
||||
|
||||
.L_loop0:
|
||||
cmp r4, r5
|
||||
bge .L_loop0_done
|
||||
ldr r1, [r4]
|
||||
ldr r2, [r4, #4]
|
||||
ldr r3, [r4, #8]
|
||||
|
||||
.L_loop0_0:
|
||||
subs r3, #4
|
||||
ittt ge
|
||||
ldrge r0, [r1, r3]
|
||||
strge r0, [r2, r3]
|
||||
bge .L_loop0_0
|
||||
|
||||
adds r4, #12
|
||||
b .L_loop0
|
||||
|
||||
.L_loop0_done:
|
||||
#else
|
||||
/* Single section scheme.
|
||||
*
|
||||
* The ranges of copy from/to are specified by following symbols
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to
|
||||
* __data_end__: VMA of end of the section to copy to
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__data_end__
|
||||
|
||||
.L_loop1:
|
||||
cmp r2, r3
|
||||
ittt lt
|
||||
ldrlt r0, [r1], #4
|
||||
strlt r0, [r2], #4
|
||||
blt .L_loop1
|
||||
#endif /*__STARTUP_COPY_MULTIPLE */
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define this macro to enable it in this startup.
|
||||
*
|
||||
* There are two schemes too. One can clear multiple BSS sections. Another
|
||||
* can only clear one section. The former is more size expensive than the
|
||||
* latter.
|
||||
*
|
||||
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
|
||||
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of tuples specifying:
|
||||
* offset 0: Start of a BSS section
|
||||
* offset 4: Size of this BSS section. Must be multiply of 4
|
||||
*/
|
||||
ldr r3, =__zero_table_start__
|
||||
ldr r4, =__zero_table_end__
|
||||
|
||||
.L_loop2:
|
||||
cmp r3, r4
|
||||
bge .L_loop2_done
|
||||
ldr r1, [r3]
|
||||
ldr r2, [r3, #4]
|
||||
movs r0, 0
|
||||
|
||||
.L_loop2_0:
|
||||
subs r2, #4
|
||||
itt ge
|
||||
strge r0, [r1, r2]
|
||||
bge .L_loop2_0
|
||||
|
||||
adds r3, #8
|
||||
b .L_loop2
|
||||
.L_loop2_done:
|
||||
#elif defined (__STARTUP_CLEAR_BSS)
|
||||
/* Single BSS section scheme.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* Both addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
.L_loop3:
|
||||
cmp r1, r2
|
||||
itt lt
|
||||
strlt r0, [r1], #4
|
||||
blt .L_loop3
|
||||
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
|
||||
|
||||
#ifndef __NO_SYSTEM_INIT
|
||||
bl SystemInit
|
||||
#endif
|
||||
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
bl __START
|
||||
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_irq_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, Default_Handler
|
||||
.endm
|
||||
|
||||
def_irq_handler NMI_Handler
|
||||
def_irq_handler HardFault_Handler
|
||||
def_irq_handler MemManage_Handler
|
||||
def_irq_handler BusFault_Handler
|
||||
def_irq_handler UsageFault_Handler
|
||||
def_irq_handler SVC_Handler
|
||||
def_irq_handler DebugMon_Handler
|
||||
def_irq_handler PendSV_Handler
|
||||
def_irq_handler SysTick_Handler
|
||||
|
||||
def_irq_handler WDT_IRQHandler
|
||||
def_irq_handler RTC_IRQHandler
|
||||
def_irq_handler TIM0_IRQHandler
|
||||
def_irq_handler TIM2_IRQHandler
|
||||
def_irq_handler MCIA_IRQHandler
|
||||
def_irq_handler MCIB_IRQHandler
|
||||
def_irq_handler UART0_IRQHandler
|
||||
def_irq_handler UART1_IRQHandler
|
||||
def_irq_handler UART2_IRQHandler
|
||||
def_irq_handler UART3_IRQHandler
|
||||
def_irq_handler UART4_IRQHandler
|
||||
def_irq_handler AACI_IRQHandler
|
||||
def_irq_handler CLCD_IRQHandler
|
||||
def_irq_handler ENET_IRQHandler
|
||||
def_irq_handler USBDC_IRQHandler
|
||||
def_irq_handler USBHC_IRQHandler
|
||||
def_irq_handler CHLCD_IRQHandler
|
||||
def_irq_handler FLEXRAY_IRQHandler
|
||||
def_irq_handler CAN_IRQHandler
|
||||
def_irq_handler LIN_IRQHandler
|
||||
def_irq_handler I2C_IRQHandler
|
||||
def_irq_handler CPU_CLCD_IRQHandler
|
||||
def_irq_handler SPI_IRQHandler
|
||||
|
||||
.end
|
||||
@ -0,0 +1,314 @@
|
||||
/* File: startup_ARMCM4.S
|
||||
* Purpose: startup file for Cortex-M4 devices. Should use with
|
||||
* GCC for ARM Embedded Processors
|
||||
* Version: V2.01
|
||||
* Date: 12 June 2014
|
||||
*
|
||||
*/
|
||||
/* Copyright (c) 2011 - 2014 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
.syntax unified
|
||||
.arch armv7-m
|
||||
|
||||
.section .stack
|
||||
.align 3
|
||||
#ifdef __STACK_SIZE
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.equ Stack_Size, 0x00000400
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#ifdef __HEAP_SIZE
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 0x00000C00
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .vectors
|
||||
.align 2
|
||||
.globl __Vectors
|
||||
__Vectors:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
.long MemManage_Handler /* MPU Fault Handler */
|
||||
.long BusFault_Handler /* Bus Fault Handler */
|
||||
.long UsageFault_Handler /* Usage Fault Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long SVC_Handler /* SVCall Handler */
|
||||
.long DebugMon_Handler /* Debug Monitor Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long PendSV_Handler /* PendSV Handler */
|
||||
.long SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External interrupts */
|
||||
.long WDT_IRQHandler /* 0: Watchdog Timer */
|
||||
.long RTC_IRQHandler /* 1: Real Time Clock */
|
||||
.long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
|
||||
.long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
|
||||
.long MCIA_IRQHandler /* 4: MCIa */
|
||||
.long MCIB_IRQHandler /* 5: MCIb */
|
||||
.long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
|
||||
.long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
|
||||
.long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
|
||||
.long UART4_IRQHandler /* 9: UART4 - not connected */
|
||||
.long AACI_IRQHandler /* 10: AACI / AC97 */
|
||||
.long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
|
||||
.long ENET_IRQHandler /* 12: Ethernet */
|
||||
.long USBDC_IRQHandler /* 13: USB Device */
|
||||
.long USBHC_IRQHandler /* 14: USB Host Controller */
|
||||
.long CHLCD_IRQHandler /* 15: Character LCD */
|
||||
.long FLEXRAY_IRQHandler /* 16: Flexray */
|
||||
.long CAN_IRQHandler /* 17: CAN */
|
||||
.long LIN_IRQHandler /* 18: LIN */
|
||||
.long I2C_IRQHandler /* 19: I2C ADC/DAC */
|
||||
.long 0 /* 20: Reserved */
|
||||
.long 0 /* 21: Reserved */
|
||||
.long 0 /* 22: Reserved */
|
||||
.long 0 /* 23: Reserved */
|
||||
.long 0 /* 24: Reserved */
|
||||
.long 0 /* 25: Reserved */
|
||||
.long 0 /* 26: Reserved */
|
||||
.long 0 /* 27: Reserved */
|
||||
.long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
|
||||
.long 0 /* 29: Reserved - CPU FPGA */
|
||||
.long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
|
||||
.long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
|
||||
|
||||
.size __Vectors, . - __Vectors
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 2
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
/* Firstly it copies data from read only memory to RAM. There are two schemes
|
||||
* to copy. One can copy more than one sections. Another can only copy
|
||||
* one section. The former scheme needs more instructions and read-only
|
||||
* data to implement than the latter.
|
||||
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
|
||||
|
||||
#ifdef __STARTUP_COPY_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of triplets, each of which specify:
|
||||
* offset 0: LMA of start of a section to copy from
|
||||
* offset 4: VMA of start of a section to copy to
|
||||
* offset 8: size of the section to copy. Must be multiply of 4
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r4, =__copy_table_start__
|
||||
ldr r5, =__copy_table_end__
|
||||
|
||||
.L_loop0:
|
||||
cmp r4, r5
|
||||
bge .L_loop0_done
|
||||
ldr r1, [r4]
|
||||
ldr r2, [r4, #4]
|
||||
ldr r3, [r4, #8]
|
||||
|
||||
.L_loop0_0:
|
||||
subs r3, #4
|
||||
ittt ge
|
||||
ldrge r0, [r1, r3]
|
||||
strge r0, [r2, r3]
|
||||
bge .L_loop0_0
|
||||
|
||||
adds r4, #12
|
||||
b .L_loop0
|
||||
|
||||
.L_loop0_done:
|
||||
#else
|
||||
/* Single section scheme.
|
||||
*
|
||||
* The ranges of copy from/to are specified by following symbols
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to
|
||||
* __data_end__: VMA of end of the section to copy to
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__data_end__
|
||||
|
||||
.L_loop1:
|
||||
cmp r2, r3
|
||||
ittt lt
|
||||
ldrlt r0, [r1], #4
|
||||
strlt r0, [r2], #4
|
||||
blt .L_loop1
|
||||
#endif /*__STARTUP_COPY_MULTIPLE */
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define this macro to enable it in this startup.
|
||||
*
|
||||
* There are two schemes too. One can clear multiple BSS sections. Another
|
||||
* can only clear one section. The former is more size expensive than the
|
||||
* latter.
|
||||
*
|
||||
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
|
||||
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of tuples specifying:
|
||||
* offset 0: Start of a BSS section
|
||||
* offset 4: Size of this BSS section. Must be multiply of 4
|
||||
*/
|
||||
ldr r3, =__zero_table_start__
|
||||
ldr r4, =__zero_table_end__
|
||||
|
||||
.L_loop2:
|
||||
cmp r3, r4
|
||||
bge .L_loop2_done
|
||||
ldr r1, [r3]
|
||||
ldr r2, [r3, #4]
|
||||
movs r0, 0
|
||||
|
||||
.L_loop2_0:
|
||||
subs r2, #4
|
||||
itt ge
|
||||
strge r0, [r1, r2]
|
||||
bge .L_loop2_0
|
||||
|
||||
adds r3, #8
|
||||
b .L_loop2
|
||||
.L_loop2_done:
|
||||
#elif defined (__STARTUP_CLEAR_BSS)
|
||||
/* Single BSS section scheme.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* Both addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
.L_loop3:
|
||||
cmp r1, r2
|
||||
itt lt
|
||||
strlt r0, [r1], #4
|
||||
blt .L_loop3
|
||||
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
|
||||
|
||||
#ifndef __NO_SYSTEM_INIT
|
||||
bl SystemInit
|
||||
#endif
|
||||
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
bl __START
|
||||
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_irq_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, Default_Handler
|
||||
.endm
|
||||
|
||||
def_irq_handler NMI_Handler
|
||||
def_irq_handler HardFault_Handler
|
||||
def_irq_handler MemManage_Handler
|
||||
def_irq_handler BusFault_Handler
|
||||
def_irq_handler UsageFault_Handler
|
||||
def_irq_handler SVC_Handler
|
||||
def_irq_handler DebugMon_Handler
|
||||
def_irq_handler PendSV_Handler
|
||||
def_irq_handler SysTick_Handler
|
||||
|
||||
def_irq_handler WDT_IRQHandler
|
||||
def_irq_handler RTC_IRQHandler
|
||||
def_irq_handler TIM0_IRQHandler
|
||||
def_irq_handler TIM2_IRQHandler
|
||||
def_irq_handler MCIA_IRQHandler
|
||||
def_irq_handler MCIB_IRQHandler
|
||||
def_irq_handler UART0_IRQHandler
|
||||
def_irq_handler UART1_IRQHandler
|
||||
def_irq_handler UART2_IRQHandler
|
||||
def_irq_handler UART3_IRQHandler
|
||||
def_irq_handler UART4_IRQHandler
|
||||
def_irq_handler AACI_IRQHandler
|
||||
def_irq_handler CLCD_IRQHandler
|
||||
def_irq_handler ENET_IRQHandler
|
||||
def_irq_handler USBDC_IRQHandler
|
||||
def_irq_handler USBHC_IRQHandler
|
||||
def_irq_handler CHLCD_IRQHandler
|
||||
def_irq_handler FLEXRAY_IRQHandler
|
||||
def_irq_handler CAN_IRQHandler
|
||||
def_irq_handler LIN_IRQHandler
|
||||
def_irq_handler I2C_IRQHandler
|
||||
def_irq_handler CPU_CLCD_IRQHandler
|
||||
def_irq_handler SPI_IRQHandler
|
||||
|
||||
.end
|
||||
@ -0,0 +1,80 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_ARMCM0.c
|
||||
* @brief CMSIS Device System Source File for
|
||||
* ARMCM0 Device Series
|
||||
* @version V1.08
|
||||
* @date 23. November 2012
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#include "ARMCM0.h"
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __HSI ( 8000000UL)
|
||||
#define __XTAL ( 5000000UL) /* Oscillator frequency */
|
||||
|
||||
#define __SYSTEM_CLOCK (5*__XTAL)
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||
{
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
@ -0,0 +1,84 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_ARMCM3.c
|
||||
* @brief CMSIS Device System Source File for
|
||||
* ARMCM3 Device Series
|
||||
* @version V1.08
|
||||
* @date 23. November 2012
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#include "ARMCM3.h"
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __HSI ( 8000000UL)
|
||||
#define __XTAL ( 5000000UL) /* Oscillator frequency */
|
||||
|
||||
#define __SYSTEM_CLOCK (5*__XTAL)
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||
{
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
|
||||
#ifdef UNALIGNED_SUPPORT_DISABLE
|
||||
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
|
||||
#endif
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
@ -0,0 +1,93 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_ARMCM4.c
|
||||
* @brief CMSIS Device System Source File for
|
||||
* ARMCM4 Device Series
|
||||
* @version V1.09
|
||||
* @date 26. August 2014
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
#if defined (ARMCM4)
|
||||
#include "ARMCM4.h"
|
||||
#elif defined (ARMCM4_FP)
|
||||
#include "ARMCM4_FP.h"
|
||||
#else
|
||||
#error device not specified!
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __HSI ( 8000000UL)
|
||||
#define __XTAL ( 5000000UL) /* Oscillator frequency */
|
||||
|
||||
#define __SYSTEM_CLOCK (5*__XTAL)
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||
{
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
#if (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
|
||||
(3UL << 11*2) ); /* set CP11 Full Access */
|
||||
#endif
|
||||
|
||||
#ifdef UNALIGNED_SUPPORT_DISABLE
|
||||
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
|
||||
#endif
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
@ -0,0 +1,15 @@
|
||||
|
||||
/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions
|
||||
|
||||
The file can be executed in the following way:
|
||||
1) manually from uVision command window (in debug mode) using command:
|
||||
INCLUIDE arm_class_marks_example.ini
|
||||
|
||||
*/
|
||||
|
||||
|
||||
// usual initialisation for target setup
|
||||
MAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash
|
||||
MAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,210 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
|
||||
*
|
||||
* $Date: 16/06/16 3:43p $Revision: V1.4.0
|
||||
*
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_class_marks_example_f32.c
|
||||
*
|
||||
* Description: Example code to calculate Minimum, Maximum
|
||||
* Mean, std and variance of marks obtained in a class
|
||||
*
|
||||
* Target Processor: Cortex-M4/Cortex-M3
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
/**
|
||||
* @ingroup groupExamples
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ClassMarks Class Marks Example
|
||||
*
|
||||
* \par Description:
|
||||
* \par
|
||||
* Demonstrates the use the Maximum, Minimum, Mean, Standard Deviation, Variance
|
||||
* and Matrix functions to calculate statistical values of marks obtained in a class.
|
||||
*
|
||||
* \note This example also demonstrates the usage of static initialization.
|
||||
*
|
||||
* \par Variables Description:
|
||||
* \par
|
||||
* \li \c testMarks_f32 points to the marks scored by 20 students in 4 subjects
|
||||
* \li \c max_marks Maximum of all marks
|
||||
* \li \c min_marks Minimum of all marks
|
||||
* \li \c mean Mean of all marks
|
||||
* \li \c var Variance of the marks
|
||||
* \li \c std Standard deviation of the marks
|
||||
* \li \c numStudents Total number of students in the class
|
||||
*
|
||||
* \par CMSIS DSP Software Library Functions Used:
|
||||
* \par
|
||||
* - arm_mat_init_f32()
|
||||
* - arm_mat_mult_f32()
|
||||
* - arm_max_f32()
|
||||
* - arm_min_f32()
|
||||
* - arm_mean_f32()
|
||||
* - arm_std_f32()
|
||||
* - arm_var_f32()
|
||||
*
|
||||
* <b> Refer </b>
|
||||
* \link arm_class_marks_example_f32.c \endlink
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
/** \example arm_class_marks_example_f32.c
|
||||
*/
|
||||
#include "arm_math.h"
|
||||
|
||||
#define USE_STATIC_INIT
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
** Global defines
|
||||
** ------------------------------------------------------------------- */
|
||||
|
||||
#define TEST_LENGTH_SAMPLES (20*4)
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
** List of Marks scored by 20 students for 4 subjects
|
||||
** ------------------------------------------------------------------- */
|
||||
const float32_t testMarks_f32[TEST_LENGTH_SAMPLES] =
|
||||
{
|
||||
42.000000, 37.000000, 81.000000, 28.000000,
|
||||
83.000000, 72.000000, 36.000000, 38.000000,
|
||||
32.000000, 51.000000, 63.000000, 64.000000,
|
||||
97.000000, 82.000000, 95.000000, 90.000000,
|
||||
66.000000, 51.000000, 54.000000, 42.000000,
|
||||
67.000000, 56.000000, 45.000000, 57.000000,
|
||||
67.000000, 69.000000, 35.000000, 52.000000,
|
||||
29.000000, 81.000000, 58.000000, 47.000000,
|
||||
38.000000, 76.000000, 100.000000, 29.000000,
|
||||
33.000000, 47.000000, 29.000000, 50.000000,
|
||||
34.000000, 41.000000, 61.000000, 46.000000,
|
||||
52.000000, 50.000000, 48.000000, 36.000000,
|
||||
47.000000, 55.000000, 44.000000, 40.000000,
|
||||
100.000000, 94.000000, 84.000000, 37.000000,
|
||||
32.000000, 71.000000, 47.000000, 77.000000,
|
||||
31.000000, 50.000000, 49.000000, 35.000000,
|
||||
63.000000, 67.000000, 40.000000, 31.000000,
|
||||
29.000000, 68.000000, 61.000000, 38.000000,
|
||||
31.000000, 28.000000, 28.000000, 76.000000,
|
||||
55.000000, 33.000000, 29.000000, 39.000000
|
||||
};
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
* Number of subjects X 1
|
||||
* ------------------------------------------------------------------- */
|
||||
const float32_t testUnity_f32[4] =
|
||||
{
|
||||
1.000, 1.000, 1.000, 1.000
|
||||
};
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
** f32 Output buffer
|
||||
** ------------------------------------------------------------------- */
|
||||
static float32_t testOutput[TEST_LENGTH_SAMPLES];
|
||||
|
||||
|
||||
/* ------------------------------------------------------------------
|
||||
* Global defines
|
||||
*------------------------------------------------------------------- */
|
||||
#define NUMSTUDENTS 20
|
||||
#define NUMSUBJECTS 4
|
||||
|
||||
/* ------------------------------------------------------------------
|
||||
* Global variables
|
||||
*------------------------------------------------------------------- */
|
||||
|
||||
uint32_t numStudents = 20;
|
||||
uint32_t numSubjects = 4;
|
||||
float32_t max_marks, min_marks, mean, std, var;
|
||||
uint32_t student_num;
|
||||
|
||||
/* ----------------------------------------------------------------------------------
|
||||
* Main f32 test function. It returns maximum marks secured and student number
|
||||
* ------------------------------------------------------------------------------- */
|
||||
|
||||
int32_t main()
|
||||
{
|
||||
|
||||
#ifndef USE_STATIC_INIT
|
||||
|
||||
arm_matrix_instance_f32 srcA;
|
||||
arm_matrix_instance_f32 srcB;
|
||||
arm_matrix_instance_f32 dstC;
|
||||
|
||||
/* Input and output matrices initializations */
|
||||
arm_mat_init_f32(&srcA, numStudents, numSubjects, (float32_t *)testMarks_f32);
|
||||
arm_mat_init_f32(&srcB, numSubjects, 1, (float32_t *)testUnity_f32);
|
||||
arm_mat_init_f32(&dstC, numStudents, 1, testOutput);
|
||||
|
||||
#else
|
||||
|
||||
/* Static Initializations of Input and output matrix sizes and array */
|
||||
arm_matrix_instance_f32 srcA = {NUMSTUDENTS, NUMSUBJECTS, (float32_t *)testMarks_f32};
|
||||
arm_matrix_instance_f32 srcB = {NUMSUBJECTS, 1, (float32_t *)testUnity_f32};
|
||||
arm_matrix_instance_f32 dstC = {NUMSTUDENTS, 1, testOutput};
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
*Call the Matrix multiplication process function
|
||||
* ------------------------------------------------------------------- */
|
||||
arm_mat_mult_f32(&srcA, &srcB, &dstC);
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
** Call the Max function to calculate max marks among numStudents
|
||||
** ------------------------------------------------------------------- */
|
||||
arm_max_f32(testOutput, numStudents, &max_marks, &student_num);
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
** Call the Min function to calculate min marks among numStudents
|
||||
** ------------------------------------------------------------------- */
|
||||
arm_min_f32(testOutput, numStudents, &min_marks, &student_num);
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
** Call the Mean function to calculate mean
|
||||
** ------------------------------------------------------------------- */
|
||||
arm_mean_f32(testOutput, numStudents, &mean);
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
** Call the std function to calculate standard deviation
|
||||
** ------------------------------------------------------------------- */
|
||||
arm_std_f32(testOutput, numStudents, &std);
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
** Call the var function to calculate variance
|
||||
** ------------------------------------------------------------------- */
|
||||
arm_var_f32(testOutput, numStudents, &var);
|
||||
|
||||
while(1); /* main function does not return */
|
||||
}
|
||||
@ -0,0 +1,4 @@
|
||||
CMSIS DSP_Lib example arm_convolution_example for
|
||||
Cortex-M0, Cortex-M3 and Cortex-M4 with FPU
|
||||
|
||||
The example is configured for uVision Simulator
|
||||
@ -0,0 +1,253 @@
|
||||
;/**************************************************************************//**
|
||||
; * @file startup_ARMCM0.s
|
||||
; * @brief CMSIS Core Device Startup File for
|
||||
; * ARMCM0 Device Series
|
||||
; * @version V1.08
|
||||
; * @date 23. November 2012
|
||||
; *
|
||||
; * @note
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
;/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
; ---------------------------------------------------------------------------*/
|
||||
;/*
|
||||
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
;*/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000C00
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WDT_IRQHandler ; 0: Watchdog Timer
|
||||
DCD RTC_IRQHandler ; 1: Real Time Clock
|
||||
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
|
||||
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
|
||||
DCD MCIA_IRQHandler ; 4: MCIa
|
||||
DCD MCIB_IRQHandler ; 5: MCIb
|
||||
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
|
||||
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
|
||||
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
|
||||
DCD UART4_IRQHandler ; 9: UART4 - not connected
|
||||
DCD AACI_IRQHandler ; 10: AACI / AC97
|
||||
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
|
||||
DCD ENET_IRQHandler ; 12: Ethernet
|
||||
DCD USBDC_IRQHandler ; 13: USB Device
|
||||
DCD USBHC_IRQHandler ; 14: USB Host Controller
|
||||
DCD CHLCD_IRQHandler ; 15: Character LCD
|
||||
DCD FLEXRAY_IRQHandler ; 16: Flexray
|
||||
DCD CAN_IRQHandler ; 17: CAN
|
||||
DCD LIN_IRQHandler ; 18: LIN
|
||||
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
|
||||
DCD 0 ; 20: Reserved
|
||||
DCD 0 ; 21: Reserved
|
||||
DCD 0 ; 22: Reserved
|
||||
DCD 0 ; 23: Reserved
|
||||
DCD 0 ; 24: Reserved
|
||||
DCD 0 ; 25: Reserved
|
||||
DCD 0 ; 26: Reserved
|
||||
DCD 0 ; 27: Reserved
|
||||
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
|
||||
DCD 0 ; 29: Reserved - CPU FPGA
|
||||
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
|
||||
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT TIM0_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT MCIA_IRQHandler [WEAK]
|
||||
EXPORT MCIB_IRQHandler [WEAK]
|
||||
EXPORT UART0_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT UART2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT AACI_IRQHandler [WEAK]
|
||||
EXPORT CLCD_IRQHandler [WEAK]
|
||||
EXPORT ENET_IRQHandler [WEAK]
|
||||
EXPORT USBDC_IRQHandler [WEAK]
|
||||
EXPORT USBHC_IRQHandler [WEAK]
|
||||
EXPORT CHLCD_IRQHandler [WEAK]
|
||||
EXPORT FLEXRAY_IRQHandler [WEAK]
|
||||
EXPORT CAN_IRQHandler [WEAK]
|
||||
EXPORT LIN_IRQHandler [WEAK]
|
||||
EXPORT I2C_IRQHandler [WEAK]
|
||||
EXPORT CPU_CLCD_IRQHandler [WEAK]
|
||||
EXPORT SPI_IRQHandler [WEAK]
|
||||
|
||||
WDT_IRQHandler
|
||||
RTC_IRQHandler
|
||||
TIM0_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
MCIA_IRQHandler
|
||||
MCIB_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
AACI_IRQHandler
|
||||
CLCD_IRQHandler
|
||||
ENET_IRQHandler
|
||||
USBDC_IRQHandler
|
||||
USBHC_IRQHandler
|
||||
CHLCD_IRQHandler
|
||||
FLEXRAY_IRQHandler
|
||||
CAN_IRQHandler
|
||||
LIN_IRQHandler
|
||||
I2C_IRQHandler
|
||||
CPU_CLCD_IRQHandler
|
||||
SPI_IRQHandler
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
@ -0,0 +1,80 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_ARMCM0.c
|
||||
* @brief CMSIS Device System Source File for
|
||||
* ARMCM0 Device Series
|
||||
* @version V1.08
|
||||
* @date 23. November 2012
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#include "ARMCM0.h"
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __HSI ( 8000000UL)
|
||||
#define __XTAL ( 5000000UL) /* Oscillator frequency */
|
||||
|
||||
#define __SYSTEM_CLOCK (5*__XTAL)
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||
{
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
@ -0,0 +1,273 @@
|
||||
;/**************************************************************************//**
|
||||
; * @file startup_ARMCM3.s
|
||||
; * @brief CMSIS Core Device Startup File for
|
||||
; * ARMCM3 Device Series
|
||||
; * @version V1.08
|
||||
; * @date 23. November 2012
|
||||
; *
|
||||
; * @note
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
;/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
; ---------------------------------------------------------------------------*/
|
||||
;/*
|
||||
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
;*/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000C00
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WDT_IRQHandler ; 0: Watchdog Timer
|
||||
DCD RTC_IRQHandler ; 1: Real Time Clock
|
||||
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
|
||||
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
|
||||
DCD MCIA_IRQHandler ; 4: MCIa
|
||||
DCD MCIB_IRQHandler ; 5: MCIb
|
||||
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
|
||||
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
|
||||
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
|
||||
DCD UART4_IRQHandler ; 9: UART4 - not connected
|
||||
DCD AACI_IRQHandler ; 10: AACI / AC97
|
||||
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
|
||||
DCD ENET_IRQHandler ; 12: Ethernet
|
||||
DCD USBDC_IRQHandler ; 13: USB Device
|
||||
DCD USBHC_IRQHandler ; 14: USB Host Controller
|
||||
DCD CHLCD_IRQHandler ; 15: Character LCD
|
||||
DCD FLEXRAY_IRQHandler ; 16: Flexray
|
||||
DCD CAN_IRQHandler ; 17: CAN
|
||||
DCD LIN_IRQHandler ; 18: LIN
|
||||
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
|
||||
DCD 0 ; 20: Reserved
|
||||
DCD 0 ; 21: Reserved
|
||||
DCD 0 ; 22: Reserved
|
||||
DCD 0 ; 23: Reserved
|
||||
DCD 0 ; 24: Reserved
|
||||
DCD 0 ; 25: Reserved
|
||||
DCD 0 ; 26: Reserved
|
||||
DCD 0 ; 27: Reserved
|
||||
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
|
||||
DCD 0 ; 29: Reserved - CPU FPGA
|
||||
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
|
||||
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT TIM0_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT MCIA_IRQHandler [WEAK]
|
||||
EXPORT MCIB_IRQHandler [WEAK]
|
||||
EXPORT UART0_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT UART2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT AACI_IRQHandler [WEAK]
|
||||
EXPORT CLCD_IRQHandler [WEAK]
|
||||
EXPORT ENET_IRQHandler [WEAK]
|
||||
EXPORT USBDC_IRQHandler [WEAK]
|
||||
EXPORT USBHC_IRQHandler [WEAK]
|
||||
EXPORT CHLCD_IRQHandler [WEAK]
|
||||
EXPORT FLEXRAY_IRQHandler [WEAK]
|
||||
EXPORT CAN_IRQHandler [WEAK]
|
||||
EXPORT LIN_IRQHandler [WEAK]
|
||||
EXPORT I2C_IRQHandler [WEAK]
|
||||
EXPORT CPU_CLCD_IRQHandler [WEAK]
|
||||
EXPORT SPI_IRQHandler [WEAK]
|
||||
|
||||
WDT_IRQHandler
|
||||
RTC_IRQHandler
|
||||
TIM0_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
MCIA_IRQHandler
|
||||
MCIB_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
AACI_IRQHandler
|
||||
CLCD_IRQHandler
|
||||
ENET_IRQHandler
|
||||
USBDC_IRQHandler
|
||||
USBHC_IRQHandler
|
||||
CHLCD_IRQHandler
|
||||
FLEXRAY_IRQHandler
|
||||
CAN_IRQHandler
|
||||
LIN_IRQHandler
|
||||
I2C_IRQHandler
|
||||
CPU_CLCD_IRQHandler
|
||||
SPI_IRQHandler
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
@ -0,0 +1,84 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_ARMCM3.c
|
||||
* @brief CMSIS Device System Source File for
|
||||
* ARMCM3 Device Series
|
||||
* @version V1.08
|
||||
* @date 23. November 2012
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#include "ARMCM3.h"
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __HSI ( 8000000UL)
|
||||
#define __XTAL ( 5000000UL) /* Oscillator frequency */
|
||||
|
||||
#define __SYSTEM_CLOCK (5*__XTAL)
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||
{
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
|
||||
#ifdef UNALIGNED_SUPPORT_DISABLE
|
||||
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
|
||||
#endif
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
@ -0,0 +1,273 @@
|
||||
;/**************************************************************************//**
|
||||
; * @file startup_ARMCM4.s
|
||||
; * @brief CMSIS Core Device Startup File for
|
||||
; * ARMCM4 Device Series
|
||||
; * @version V1.08
|
||||
; * @date 23. November 2012
|
||||
; *
|
||||
; * @note
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
;/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
; ---------------------------------------------------------------------------*/
|
||||
;/*
|
||||
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
;*/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000C00
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WDT_IRQHandler ; 0: Watchdog Timer
|
||||
DCD RTC_IRQHandler ; 1: Real Time Clock
|
||||
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
|
||||
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
|
||||
DCD MCIA_IRQHandler ; 4: MCIa
|
||||
DCD MCIB_IRQHandler ; 5: MCIb
|
||||
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
|
||||
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
|
||||
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
|
||||
DCD UART4_IRQHandler ; 9: UART4 - not connected
|
||||
DCD AACI_IRQHandler ; 10: AACI / AC97
|
||||
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
|
||||
DCD ENET_IRQHandler ; 12: Ethernet
|
||||
DCD USBDC_IRQHandler ; 13: USB Device
|
||||
DCD USBHC_IRQHandler ; 14: USB Host Controller
|
||||
DCD CHLCD_IRQHandler ; 15: Character LCD
|
||||
DCD FLEXRAY_IRQHandler ; 16: Flexray
|
||||
DCD CAN_IRQHandler ; 17: CAN
|
||||
DCD LIN_IRQHandler ; 18: LIN
|
||||
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
|
||||
DCD 0 ; 20: Reserved
|
||||
DCD 0 ; 21: Reserved
|
||||
DCD 0 ; 22: Reserved
|
||||
DCD 0 ; 23: Reserved
|
||||
DCD 0 ; 24: Reserved
|
||||
DCD 0 ; 25: Reserved
|
||||
DCD 0 ; 26: Reserved
|
||||
DCD 0 ; 27: Reserved
|
||||
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
|
||||
DCD 0 ; 29: Reserved - CPU FPGA
|
||||
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
|
||||
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT TIM0_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT MCIA_IRQHandler [WEAK]
|
||||
EXPORT MCIB_IRQHandler [WEAK]
|
||||
EXPORT UART0_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT UART2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT AACI_IRQHandler [WEAK]
|
||||
EXPORT CLCD_IRQHandler [WEAK]
|
||||
EXPORT ENET_IRQHandler [WEAK]
|
||||
EXPORT USBDC_IRQHandler [WEAK]
|
||||
EXPORT USBHC_IRQHandler [WEAK]
|
||||
EXPORT CHLCD_IRQHandler [WEAK]
|
||||
EXPORT FLEXRAY_IRQHandler [WEAK]
|
||||
EXPORT CAN_IRQHandler [WEAK]
|
||||
EXPORT LIN_IRQHandler [WEAK]
|
||||
EXPORT I2C_IRQHandler [WEAK]
|
||||
EXPORT CPU_CLCD_IRQHandler [WEAK]
|
||||
EXPORT SPI_IRQHandler [WEAK]
|
||||
|
||||
WDT_IRQHandler
|
||||
RTC_IRQHandler
|
||||
TIM0_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
MCIA_IRQHandler
|
||||
MCIB_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
AACI_IRQHandler
|
||||
CLCD_IRQHandler
|
||||
ENET_IRQHandler
|
||||
USBDC_IRQHandler
|
||||
USBHC_IRQHandler
|
||||
CHLCD_IRQHandler
|
||||
FLEXRAY_IRQHandler
|
||||
CAN_IRQHandler
|
||||
LIN_IRQHandler
|
||||
I2C_IRQHandler
|
||||
CPU_CLCD_IRQHandler
|
||||
SPI_IRQHandler
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
@ -0,0 +1,93 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_ARMCM4.c
|
||||
* @brief CMSIS Device System Source File for
|
||||
* ARMCM4 Device Series
|
||||
* @version V1.09
|
||||
* @date 26. August 2014
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
#if defined (ARMCM4)
|
||||
#include "ARMCM4.h"
|
||||
#elif defined (ARMCM4_FP)
|
||||
#include "ARMCM4_FP.h"
|
||||
#else
|
||||
#error device not specified!
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __HSI ( 8000000UL)
|
||||
#define __XTAL ( 5000000UL) /* Oscillator frequency */
|
||||
|
||||
#define __SYSTEM_CLOCK (5*__XTAL)
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||
{
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
#if (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
|
||||
(3UL << 11*2) ); /* set CP11 Full Access */
|
||||
#endif
|
||||
|
||||
#ifdef UNALIGNED_SUPPORT_DISABLE
|
||||
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
|
||||
#endif
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
@ -0,0 +1,273 @@
|
||||
;/**************************************************************************//**
|
||||
; * @file startup_ARMCM7.s
|
||||
; * @brief CMSIS Core Device Startup File for
|
||||
; * ARMCM7 Device Series
|
||||
; * @version V1.00
|
||||
; * @date 22. August 2014
|
||||
; *
|
||||
; * @note
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
;/* Copyright (c) 2011 - 2014 ARM LIMITED
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
; ---------------------------------------------------------------------------*/
|
||||
;/*
|
||||
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
;*/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000C00
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WDT_IRQHandler ; 0: Watchdog Timer
|
||||
DCD RTC_IRQHandler ; 1: Real Time Clock
|
||||
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
|
||||
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
|
||||
DCD MCIA_IRQHandler ; 4: MCIa
|
||||
DCD MCIB_IRQHandler ; 5: MCIb
|
||||
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
|
||||
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
|
||||
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
|
||||
DCD UART4_IRQHandler ; 9: UART4 - not connected
|
||||
DCD AACI_IRQHandler ; 10: AACI / AC97
|
||||
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
|
||||
DCD ENET_IRQHandler ; 12: Ethernet
|
||||
DCD USBDC_IRQHandler ; 13: USB Device
|
||||
DCD USBHC_IRQHandler ; 14: USB Host Controller
|
||||
DCD CHLCD_IRQHandler ; 15: Character LCD
|
||||
DCD FLEXRAY_IRQHandler ; 16: Flexray
|
||||
DCD CAN_IRQHandler ; 17: CAN
|
||||
DCD LIN_IRQHandler ; 18: LIN
|
||||
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
|
||||
DCD 0 ; 20: Reserved
|
||||
DCD 0 ; 21: Reserved
|
||||
DCD 0 ; 22: Reserved
|
||||
DCD 0 ; 23: Reserved
|
||||
DCD 0 ; 24: Reserved
|
||||
DCD 0 ; 25: Reserved
|
||||
DCD 0 ; 26: Reserved
|
||||
DCD 0 ; 27: Reserved
|
||||
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
|
||||
DCD 0 ; 29: Reserved - CPU FPGA
|
||||
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
|
||||
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT TIM0_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT MCIA_IRQHandler [WEAK]
|
||||
EXPORT MCIB_IRQHandler [WEAK]
|
||||
EXPORT UART0_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT UART2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT AACI_IRQHandler [WEAK]
|
||||
EXPORT CLCD_IRQHandler [WEAK]
|
||||
EXPORT ENET_IRQHandler [WEAK]
|
||||
EXPORT USBDC_IRQHandler [WEAK]
|
||||
EXPORT USBHC_IRQHandler [WEAK]
|
||||
EXPORT CHLCD_IRQHandler [WEAK]
|
||||
EXPORT FLEXRAY_IRQHandler [WEAK]
|
||||
EXPORT CAN_IRQHandler [WEAK]
|
||||
EXPORT LIN_IRQHandler [WEAK]
|
||||
EXPORT I2C_IRQHandler [WEAK]
|
||||
EXPORT CPU_CLCD_IRQHandler [WEAK]
|
||||
EXPORT SPI_IRQHandler [WEAK]
|
||||
|
||||
WDT_IRQHandler
|
||||
RTC_IRQHandler
|
||||
TIM0_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
MCIA_IRQHandler
|
||||
MCIB_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
AACI_IRQHandler
|
||||
CLCD_IRQHandler
|
||||
ENET_IRQHandler
|
||||
USBDC_IRQHandler
|
||||
USBHC_IRQHandler
|
||||
CHLCD_IRQHandler
|
||||
FLEXRAY_IRQHandler
|
||||
CAN_IRQHandler
|
||||
LIN_IRQHandler
|
||||
I2C_IRQHandler
|
||||
CPU_CLCD_IRQHandler
|
||||
SPI_IRQHandler
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
@ -0,0 +1,102 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_ARMCM7.c
|
||||
* @brief CMSIS Device System Source File for
|
||||
* ARMCM7 Device Series
|
||||
* @version V1.00
|
||||
* @date 27. August 2014
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2011 - 2014 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined (ARMCM7)
|
||||
#include "ARMCM7.h"
|
||||
#elif defined (ARMCM7_SP)
|
||||
#include "ARMCM7_SP.h"
|
||||
#elif defined (ARMCM7_DP)
|
||||
#include "ARMCM7_DP.h"
|
||||
#else
|
||||
#error device not specified!
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __HSI ( 8000000UL)
|
||||
#define __XTAL ( 5000000UL) /* Oscillator frequency */
|
||||
|
||||
#define __SYSTEM_CLOCK (5*__XTAL)
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Core Clock Variable
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/* System Core Clock Frequency */
|
||||
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
#if (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
|
||||
(3UL << 11*2) ); /* set CP11 Full Access */
|
||||
#endif
|
||||
|
||||
#ifdef UNALIGNED_SUPPORT_DISABLE
|
||||
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
|
||||
#endif
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
@ -0,0 +1,14 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Component Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'arm_convolution_example'
|
||||
* Target: 'ARMCM0'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@ -0,0 +1,15 @@
|
||||
|
||||
/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions
|
||||
|
||||
The file can be executed in the following way:
|
||||
1) manually from uVision command window (in debug mode) using command:
|
||||
INCLUIDE arm_convolution_example.ini
|
||||
|
||||
*/
|
||||
|
||||
|
||||
// usual initialisation for target setup
|
||||
MAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash
|
||||
MAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM
|
||||
|
||||
|
||||
@ -0,0 +1,954 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>ARMCM0</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>10000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\ARMCM0_debug\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>7</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>1</uSim>
|
||||
<uTrg>0</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>0</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<nTsel>0</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile>.\arm_convolution_example.ini</sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\UL2CM3.DLL</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0$Device\ARM\Flash\NEW_DEVICE.FLM))</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGDARM</Key>
|
||||
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMDBGFLAGS</Key>
|
||||
<Name>-T0</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint>
|
||||
<Bp>
|
||||
<Number>0</Number>
|
||||
<Type>0</Type>
|
||||
<LineNumber>241</LineNumber>
|
||||
<EnabledFlag>1</EnabledFlag>
|
||||
<Address>1722</Address>
|
||||
<ByteObject>0</ByteObject>
|
||||
<HtxType>0</HtxType>
|
||||
<ManyObjects>0</ManyObjects>
|
||||
<SizeOfObject>0</SizeOfObject>
|
||||
<BreakByAccess>0</BreakByAccess>
|
||||
<BreakIfRCount>1</BreakIfRCount>
|
||||
<Filename>.\arm_convolution_example_f32.c</Filename>
|
||||
<ExecCommand></ExecCommand>
|
||||
<Expression>\\arm_convolution_example\arm_convolution_example_f32.c\241</Expression>
|
||||
</Bp>
|
||||
<Bp>
|
||||
<Number>1</Number>
|
||||
<Type>0</Type>
|
||||
<LineNumber>244</LineNumber>
|
||||
<EnabledFlag>1</EnabledFlag>
|
||||
<Address>1726</Address>
|
||||
<ByteObject>0</ByteObject>
|
||||
<HtxType>0</HtxType>
|
||||
<ManyObjects>0</ManyObjects>
|
||||
<SizeOfObject>0</SizeOfObject>
|
||||
<BreakByAccess>0</BreakByAccess>
|
||||
<BreakIfRCount>1</BreakIfRCount>
|
||||
<Filename>.\arm_convolution_example_f32.c</Filename>
|
||||
<ExecCommand></ExecCommand>
|
||||
<Expression>\\arm_convolution_example\arm_convolution_example_f32.c\244</Expression>
|
||||
</Bp>
|
||||
</Breakpoint>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>1</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>1</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Target>
|
||||
<TargetName>ARMCM3</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>10000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\ARMCM3_debug\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>0</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>7</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>1</uSim>
|
||||
<uTrg>0</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>0</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<nTsel>0</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile>.\arm_convolution_example.ini</sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\UL2CM3.DLL</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM))</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGDARM</Key>
|
||||
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMDBGFLAGS</Key>
|
||||
<Name>-T0</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint>
|
||||
<Bp>
|
||||
<Number>0</Number>
|
||||
<Type>0</Type>
|
||||
<LineNumber>244</LineNumber>
|
||||
<EnabledFlag>1</EnabledFlag>
|
||||
<Address>1696</Address>
|
||||
<ByteObject>0</ByteObject>
|
||||
<HtxType>0</HtxType>
|
||||
<ManyObjects>0</ManyObjects>
|
||||
<SizeOfObject>0</SizeOfObject>
|
||||
<BreakByAccess>0</BreakByAccess>
|
||||
<BreakIfRCount>1</BreakIfRCount>
|
||||
<Filename>.\arm_convolution_example_f32.c</Filename>
|
||||
<ExecCommand></ExecCommand>
|
||||
<Expression></Expression>
|
||||
</Bp>
|
||||
<Bp>
|
||||
<Number>1</Number>
|
||||
<Type>0</Type>
|
||||
<LineNumber>241</LineNumber>
|
||||
<EnabledFlag>1</EnabledFlag>
|
||||
<Address>1692</Address>
|
||||
<ByteObject>0</ByteObject>
|
||||
<HtxType>0</HtxType>
|
||||
<ManyObjects>0</ManyObjects>
|
||||
<SizeOfObject>0</SizeOfObject>
|
||||
<BreakByAccess>0</BreakByAccess>
|
||||
<BreakIfRCount>1</BreakIfRCount>
|
||||
<Filename>.\arm_convolution_example_f32.c</Filename>
|
||||
<ExecCommand></ExecCommand>
|
||||
<Expression></Expression>
|
||||
</Bp>
|
||||
</Breakpoint>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>1</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>1</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Target>
|
||||
<TargetName>ARMCM4_FP</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\ARMCM4_debug\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
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<GroupNumber>4</GroupNumber>
|
||||
<FileNumber>8</FileNumber>
|
||||
<FileType>2</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>RTE\Device\ARMCM0\startup_ARMCM0.s</PathWithFileName>
|
||||
<FilenameWithoutPath>startup_ARMCM0.s</FilenameWithoutPath>
|
||||
<RteFlg>1</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>4</GroupNumber>
|
||||
<FileNumber>9</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>RTE\Device\ARMCM0\system_ARMCM0.c</PathWithFileName>
|
||||
<FilenameWithoutPath>system_ARMCM0.c</FilenameWithoutPath>
|
||||
<RteFlg>1</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>4</GroupNumber>
|
||||
<FileNumber>10</FileNumber>
|
||||
<FileType>2</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>RTE\Device\ARMCM3\startup_ARMCM3.s</PathWithFileName>
|
||||
<FilenameWithoutPath>startup_ARMCM3.s</FilenameWithoutPath>
|
||||
<RteFlg>1</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>4</GroupNumber>
|
||||
<FileNumber>11</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>RTE\Device\ARMCM3\system_ARMCM3.c</PathWithFileName>
|
||||
<FilenameWithoutPath>system_ARMCM3.c</FilenameWithoutPath>
|
||||
<RteFlg>1</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>4</GroupNumber>
|
||||
<FileNumber>12</FileNumber>
|
||||
<FileType>2</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>RTE\Device\ARMCM4_FP\startup_ARMCM4.s</PathWithFileName>
|
||||
<FilenameWithoutPath>startup_ARMCM4.s</FilenameWithoutPath>
|
||||
<RteFlg>1</RteFlg>
|
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<bShared>0</bShared>
|
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</File>
|
||||
<File>
|
||||
<GroupNumber>4</GroupNumber>
|
||||
<FileNumber>13</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>RTE\Device\ARMCM4_FP\system_ARMCM4.c</PathWithFileName>
|
||||
<FilenameWithoutPath>system_ARMCM4.c</FilenameWithoutPath>
|
||||
<RteFlg>1</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>4</GroupNumber>
|
||||
<FileNumber>14</FileNumber>
|
||||
<FileType>2</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>RTE\Device\ARMCM7_SP\startup_ARMCM7.s</PathWithFileName>
|
||||
<FilenameWithoutPath>startup_ARMCM7.s</FilenameWithoutPath>
|
||||
<RteFlg>1</RteFlg>
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<bShared>0</bShared>
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<File>
|
||||
<GroupNumber>4</GroupNumber>
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||||
<FileNumber>15</FileNumber>
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||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>RTE\Device\ARMCM7_SP\system_ARMCM7.c</PathWithFileName>
|
||||
<FilenameWithoutPath>system_ARMCM7.c</FilenameWithoutPath>
|
||||
<RteFlg>1</RteFlg>
|
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<bShared>0</bShared>
|
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</File>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,246 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
|
||||
*
|
||||
* $Date: 16/06/16 3:43p $Revision: V1.4.0
|
||||
*
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_convolution_example_f32.c
|
||||
*
|
||||
* Description: Example code demonstrating Convolution of two input signals using fft.
|
||||
*
|
||||
* Target Processor: Cortex-M4/Cortex-M3
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
/**
|
||||
* @ingroup groupExamples
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ConvolutionExample Convolution Example
|
||||
*
|
||||
* \par Description:
|
||||
* \par
|
||||
* Demonstrates the convolution theorem with the use of the Complex FFT, Complex-by-Complex
|
||||
* Multiplication, and Support Functions.
|
||||
*
|
||||
* \par Algorithm:
|
||||
* \par
|
||||
* The convolution theorem states that convolution in the time domain corresponds to
|
||||
* multiplication in the frequency domain. Therefore, the Fourier transform of the convoution of
|
||||
* two signals is equal to the product of their individual Fourier transforms.
|
||||
* The Fourier transform of a signal can be evaluated efficiently using the Fast Fourier Transform (FFT).
|
||||
* \par
|
||||
* Two input signals, <code>a[n]</code> and <code>b[n]</code>, with lengths \c n1 and \c n2 respectively,
|
||||
* are zero padded so that their lengths become \c N, which is greater than or equal to <code>(n1+n2-1)</code>
|
||||
* and is a power of 4 as FFT implementation is radix-4.
|
||||
* The convolution of <code>a[n]</code> and <code>b[n]</code> is obtained by taking the FFT of the input
|
||||
* signals, multiplying the Fourier transforms of the two signals, and taking the inverse FFT of
|
||||
* the multiplied result.
|
||||
* \par
|
||||
* This is denoted by the following equations:
|
||||
* <pre> A[k] = FFT(a[n],N)
|
||||
* B[k] = FFT(b[n],N)
|
||||
* conv(a[n], b[n]) = IFFT(A[k] * B[k], N)</pre>
|
||||
* where <code>A[k]</code> and <code>B[k]</code> are the N-point FFTs of the signals <code>a[n]</code>
|
||||
* and <code>b[n]</code> respectively.
|
||||
* The length of the convolved signal is <code>(n1+n2-1)</code>.
|
||||
*
|
||||
* \par Block Diagram:
|
||||
* \par
|
||||
* \image html Convolution.gif
|
||||
*
|
||||
* \par Variables Description:
|
||||
* \par
|
||||
* \li \c testInputA_f32 points to the first input sequence
|
||||
* \li \c srcALen length of the first input sequence
|
||||
* \li \c testInputB_f32 points to the second input sequence
|
||||
* \li \c srcBLen length of the second input sequence
|
||||
* \li \c outLen length of convolution output sequence, <code>(srcALen + srcBLen - 1)</code>
|
||||
* \li \c AxB points to the output array where the product of individual FFTs of inputs is stored.
|
||||
*
|
||||
* \par CMSIS DSP Software Library Functions Used:
|
||||
* \par
|
||||
* - arm_fill_f32()
|
||||
* - arm_copy_f32()
|
||||
* - arm_cfft_radix4_init_f32()
|
||||
* - arm_cfft_radix4_f32()
|
||||
* - arm_cmplx_mult_cmplx_f32()
|
||||
*
|
||||
* <b> Refer </b>
|
||||
* \link arm_convolution_example_f32.c \endlink
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
/** \example arm_convolution_example_f32.c
|
||||
*/
|
||||
|
||||
#include "arm_math.h"
|
||||
#include "math_helper.h"
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
* Defines each of the tests performed
|
||||
* ------------------------------------------------------------------- */
|
||||
#define MAX_BLOCKSIZE 128
|
||||
#define DELTA (0.000001f)
|
||||
#define SNR_THRESHOLD 90
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
* Declare I/O buffers
|
||||
* ------------------------------------------------------------------- */
|
||||
float32_t Ak[MAX_BLOCKSIZE]; /* Input A */
|
||||
float32_t Bk[MAX_BLOCKSIZE]; /* Input B */
|
||||
float32_t AxB[MAX_BLOCKSIZE * 2]; /* Output */
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
* Test input data for Floating point Convolution example for 32-blockSize
|
||||
* Generated by the MATLAB randn() function
|
||||
* ------------------------------------------------------------------- */
|
||||
float32_t testInputA_f32[64] =
|
||||
{
|
||||
-0.808920, 1.357369, 1.180861, -0.504544, 1.762637, -0.703285,
|
||||
1.696966, 0.620571, -0.151093, -0.100235, -0.872382, -0.403579,
|
||||
-0.860749, -0.382648, -1.052338, 0.128113, -0.646269, 1.093377,
|
||||
-2.209198, 0.471706, 0.408901, 1.266242, 0.598252, 1.176827,
|
||||
-0.203421, 0.213596, -0.851964, -0.466958, 0.021841, -0.698938,
|
||||
-0.604107, 0.461778, -0.318219, 0.942520, 0.577585, 0.417619,
|
||||
0.614665, 0.563679, -1.295073, -0.764437, 0.952194, -0.859222,
|
||||
-0.618554, -2.268542, -1.210592, 1.655853, -2.627219, -0.994249,
|
||||
-1.374704, 0.343799, 0.025619, 1.227481, -0.708031, 0.069355,
|
||||
-1.845228, -1.570886, 1.010668, -1.802084, 1.630088, 1.286090,
|
||||
-0.161050, -0.940794, 0.367961, 0.291907
|
||||
|
||||
};
|
||||
|
||||
float32_t testInputB_f32[64] =
|
||||
{
|
||||
0.933724, 0.046881, 1.316470, 0.438345, 0.332682, 2.094885,
|
||||
0.512081, 0.035546, 0.050894, -2.320371, 0.168711, -1.830493,
|
||||
-0.444834, -1.003242, -0.531494, -1.365600, -0.155420, -0.757692,
|
||||
-0.431880, -0.380021, 0.096243, -0.695835, 0.558850, -1.648962,
|
||||
0.020369, -0.363630, 0.887146, 0.845503, -0.252864, -0.330397,
|
||||
1.269131, -1.109295, -1.027876, 0.135940, 0.116721, -0.293399,
|
||||
-1.349799, 0.166078, -0.802201, 0.369367, -0.964568, -2.266011,
|
||||
0.465178, 0.651222, -0.325426, 0.320245, -0.784178, -0.579456,
|
||||
0.093374, 0.604778, -0.048225, 0.376297, -0.394412, 0.578182,
|
||||
-1.218141, -1.387326, 0.692462, -0.631297, 0.153137, -0.638952,
|
||||
0.635474, -0.970468, 1.334057, -0.111370
|
||||
};
|
||||
|
||||
const float testRefOutput_f32[127] =
|
||||
{
|
||||
-0.818943, 1.229484, -0.533664, 1.016604, 0.341875, -1.963656,
|
||||
5.171476, 3.478033, 7.616361, 6.648384, 0.479069, 1.792012,
|
||||
-1.295591, -7.447818, 0.315830, -10.657445, -2.483469, -6.524236,
|
||||
-7.380591, -3.739005, -8.388957, 0.184147, -1.554888, 3.786508,
|
||||
-1.684421, 5.400610, -1.578126, 7.403361, 8.315999, 2.080267,
|
||||
11.077776, 2.749673, 7.138962, 2.748762, 0.660363, 0.981552,
|
||||
1.442275, 0.552721, -2.576892, 4.703989, 0.989156, 8.759344,
|
||||
-0.564825, -3.994680, 0.954710, -5.014144, 6.592329, 1.599488,
|
||||
-13.979146, -0.391891, -4.453369, -2.311242, -2.948764, 1.761415,
|
||||
-0.138322, 10.433007, -2.309103, 4.297153, 8.535523, 3.209462,
|
||||
8.695819, 5.569919, 2.514304, 5.582029, 2.060199, 0.642280,
|
||||
7.024616, 1.686615, -6.481756, 1.343084, -3.526451, 1.099073,
|
||||
-2.965764, -0.173723, -4.111484, 6.528384, -6.965658, 1.726291,
|
||||
1.535172, 11.023435, 2.338401, -4.690188, 1.298210, 3.943885,
|
||||
8.407885, 5.168365, 0.684131, 1.559181, 1.859998, 2.852417,
|
||||
8.574070, -6.369078, 6.023458, 11.837963, -6.027632, 4.469678,
|
||||
-6.799093, -2.674048, 6.250367, -6.809971, -3.459360, 9.112410,
|
||||
-2.711621, -1.336678, 1.564249, -1.564297, -1.296760, 8.904013,
|
||||
-3.230109, 6.878013, -7.819823, 3.369909, -1.657410, -2.007358,
|
||||
-4.112825, 1.370685, -3.420525, -6.276605, 3.244873, -3.352638,
|
||||
1.545372, 0.902211, 0.197489, -1.408732, 0.523390, 0.348440, 0
|
||||
};
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
* Declare Global variables
|
||||
* ------------------------------------------------------------------- */
|
||||
uint32_t srcALen = 64; /* Length of Input A */
|
||||
uint32_t srcBLen = 64; /* Length of Input B */
|
||||
uint32_t outLen; /* Length of convolution output */
|
||||
float32_t snr; /* output SNR */
|
||||
|
||||
int32_t main(void)
|
||||
{
|
||||
arm_status status; /* Status of the example */
|
||||
arm_cfft_radix4_instance_f32 cfft_instance; /* CFFT Structure instance */
|
||||
|
||||
/* CFFT Structure instance pointer */
|
||||
arm_cfft_radix4_instance_f32 *cfft_instance_ptr =
|
||||
(arm_cfft_radix4_instance_f32*) &cfft_instance;
|
||||
|
||||
/* output length of convolution */
|
||||
outLen = srcALen + srcBLen - 1;
|
||||
|
||||
/* Initialise the fft input buffers with all zeros */
|
||||
arm_fill_f32(0.0, Ak, MAX_BLOCKSIZE);
|
||||
arm_fill_f32(0.0, Bk, MAX_BLOCKSIZE);
|
||||
|
||||
/* Copy the input values to the fft input buffers */
|
||||
arm_copy_f32(testInputA_f32, Ak, MAX_BLOCKSIZE/2);
|
||||
arm_copy_f32(testInputB_f32, Bk, MAX_BLOCKSIZE/2);
|
||||
|
||||
/* Initialize the CFFT function to compute 64 point fft */
|
||||
status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 0, 1);
|
||||
|
||||
/* Transform input a[n] from time domain to frequency domain A[k] */
|
||||
arm_cfft_radix4_f32(cfft_instance_ptr, Ak);
|
||||
/* Transform input b[n] from time domain to frequency domain B[k] */
|
||||
arm_cfft_radix4_f32(cfft_instance_ptr, Bk);
|
||||
|
||||
/* Complex Multiplication of the two input buffers in frequency domain */
|
||||
arm_cmplx_mult_cmplx_f32(Ak, Bk, AxB, MAX_BLOCKSIZE/2);
|
||||
|
||||
/* Initialize the CIFFT function to compute 64 point ifft */
|
||||
status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 1, 1);
|
||||
|
||||
/* Transform the multiplication output from frequency domain to time domain,
|
||||
that gives the convolved output */
|
||||
arm_cfft_radix4_f32(cfft_instance_ptr, AxB);
|
||||
|
||||
/* SNR Calculation */
|
||||
snr = arm_snr_f32((float32_t *)testRefOutput_f32, AxB, srcALen + srcBLen - 1);
|
||||
|
||||
/* Compare the SNR with threshold to test whether the
|
||||
computed output is matched with the reference output values. */
|
||||
if( snr > SNR_THRESHOLD)
|
||||
{
|
||||
status = ARM_MATH_SUCCESS;
|
||||
}
|
||||
|
||||
if( status != ARM_MATH_SUCCESS)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
while(1); /* main function does not return */
|
||||
}
|
||||
|
||||
/** \endlink */
|
||||
@ -0,0 +1,457 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
|
||||
*
|
||||
* $Date: 16/06/16 3:43p $Revision: V1.4.0
|
||||
*
|
||||
* Project: CMSIS DSP Library
|
||||
*
|
||||
* Title: math_helper.c
|
||||
*
|
||||
* Description: Definition of all helper functions required.
|
||||
*
|
||||
* Target Processor: Cortex-M4/Cortex-M3
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
* Include standard header files
|
||||
* -------------------------------------------------------------------- */
|
||||
#include<math.h>
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
* Include project header files
|
||||
* -------------------------------------------------------------------- */
|
||||
#include "math_helper.h"
|
||||
|
||||
/**
|
||||
* @brief Caluclation of SNR
|
||||
* @param float* Pointer to the reference buffer
|
||||
* @param float* Pointer to the test buffer
|
||||
* @param uint32_t total number of samples
|
||||
* @return float SNR
|
||||
* The function Caluclates signal to noise ratio for the reference output
|
||||
* and test output
|
||||
*/
|
||||
|
||||
float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize)
|
||||
{
|
||||
float EnergySignal = 0.0, EnergyError = 0.0;
|
||||
uint32_t i;
|
||||
float SNR;
|
||||
int temp;
|
||||
int *test;
|
||||
|
||||
for (i = 0; i < buffSize; i++)
|
||||
{
|
||||
/* Checking for a NAN value in pRef array */
|
||||
test = (int *)(&pRef[i]);
|
||||
temp = *test;
|
||||
|
||||
if(temp == 0x7FC00000)
|
||||
{
|
||||
return(0);
|
||||
}
|
||||
|
||||
/* Checking for a NAN value in pTest array */
|
||||
test = (int *)(&pTest[i]);
|
||||
temp = *test;
|
||||
|
||||
if(temp == 0x7FC00000)
|
||||
{
|
||||
return(0);
|
||||
}
|
||||
EnergySignal += pRef[i] * pRef[i];
|
||||
EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]);
|
||||
}
|
||||
|
||||
/* Checking for a NAN value in EnergyError */
|
||||
test = (int *)(&EnergyError);
|
||||
temp = *test;
|
||||
|
||||
if(temp == 0x7FC00000)
|
||||
{
|
||||
return(0);
|
||||
}
|
||||
|
||||
|
||||
SNR = 10 * log10 (EnergySignal / EnergyError);
|
||||
|
||||
return (SNR);
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Provide guard bits for Input buffer
|
||||
* @param q15_t* Pointer to input buffer
|
||||
* @param uint32_t blockSize
|
||||
* @param uint32_t guard_bits
|
||||
* @return none
|
||||
* The function Provides the guard bits for the buffer
|
||||
* to avoid overflow
|
||||
*/
|
||||
|
||||
void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize,
|
||||
uint32_t guard_bits)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < blockSize; i++)
|
||||
{
|
||||
input_buf[i] = input_buf[i] >> guard_bits;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Converts float to fixed in q12.20 format
|
||||
* @param uint32_t number of samples in the buffer
|
||||
* @return none
|
||||
* The function converts floating point values to fixed point(q12.20) values
|
||||
*/
|
||||
|
||||
void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < numSamples; i++)
|
||||
{
|
||||
/* 1048576.0f corresponds to pow(2, 20) */
|
||||
pOut[i] = (q31_t) (pIn[i] * 1048576.0f);
|
||||
|
||||
pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
|
||||
|
||||
if (pIn[i] == (float) 1.0)
|
||||
{
|
||||
pOut[i] = 0x000FFFFF;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Compare MATLAB Reference Output and ARM Test output
|
||||
* @param q15_t* Pointer to Ref buffer
|
||||
* @param q15_t* Pointer to Test buffer
|
||||
* @param uint32_t number of samples in the buffer
|
||||
* @return none
|
||||
*/
|
||||
|
||||
uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples)
|
||||
{
|
||||
uint32_t i;
|
||||
int32_t diff, diffCrnt = 0;
|
||||
uint32_t maxDiff = 0;
|
||||
|
||||
for (i = 0; i < numSamples; i++)
|
||||
{
|
||||
diff = pIn[i] - pOut[i];
|
||||
diffCrnt = (diff > 0) ? diff : -diff;
|
||||
|
||||
if(diffCrnt > maxDiff)
|
||||
{
|
||||
maxDiff = diffCrnt;
|
||||
}
|
||||
}
|
||||
|
||||
return(maxDiff);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Compare MATLAB Reference Output and ARM Test output
|
||||
* @param q31_t* Pointer to Ref buffer
|
||||
* @param q31_t* Pointer to Test buffer
|
||||
* @param uint32_t number of samples in the buffer
|
||||
* @return none
|
||||
*/
|
||||
|
||||
uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples)
|
||||
{
|
||||
uint32_t i;
|
||||
int32_t diff, diffCrnt = 0;
|
||||
uint32_t maxDiff = 0;
|
||||
|
||||
for (i = 0; i < numSamples; i++)
|
||||
{
|
||||
diff = pIn[i] - pOut[i];
|
||||
diffCrnt = (diff > 0) ? diff : -diff;
|
||||
|
||||
if(diffCrnt > maxDiff)
|
||||
{
|
||||
maxDiff = diffCrnt;
|
||||
}
|
||||
}
|
||||
|
||||
return(maxDiff);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Provide guard bits for Input buffer
|
||||
* @param q31_t* Pointer to input buffer
|
||||
* @param uint32_t blockSize
|
||||
* @param uint32_t guard_bits
|
||||
* @return none
|
||||
* The function Provides the guard bits for the buffer
|
||||
* to avoid overflow
|
||||
*/
|
||||
|
||||
void arm_provide_guard_bits_q31 (q31_t * input_buf,
|
||||
uint32_t blockSize,
|
||||
uint32_t guard_bits)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < blockSize; i++)
|
||||
{
|
||||
input_buf[i] = input_buf[i] >> guard_bits;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Provide guard bits for Input buffer
|
||||
* @param q31_t* Pointer to input buffer
|
||||
* @param uint32_t blockSize
|
||||
* @param uint32_t guard_bits
|
||||
* @return none
|
||||
* The function Provides the guard bits for the buffer
|
||||
* to avoid overflow
|
||||
*/
|
||||
|
||||
void arm_provide_guard_bits_q7 (q7_t * input_buf,
|
||||
uint32_t blockSize,
|
||||
uint32_t guard_bits)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < blockSize; i++)
|
||||
{
|
||||
input_buf[i] = input_buf[i] >> guard_bits;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Caluclates number of guard bits
|
||||
* @param uint32_t number of additions
|
||||
* @return none
|
||||
* The function Caluclates the number of guard bits
|
||||
* depending on the numtaps
|
||||
*/
|
||||
|
||||
uint32_t arm_calc_guard_bits (uint32_t num_adds)
|
||||
{
|
||||
uint32_t i = 1, j = 0;
|
||||
|
||||
if (num_adds == 1)
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
|
||||
while (i < num_adds)
|
||||
{
|
||||
i = i * 2;
|
||||
j++;
|
||||
}
|
||||
|
||||
return (j);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Converts Q15 to floating-point
|
||||
* @param uint32_t number of samples in the buffer
|
||||
* @return none
|
||||
*/
|
||||
|
||||
void arm_apply_guard_bits (float32_t * pIn,
|
||||
uint32_t numSamples,
|
||||
uint32_t guard_bits)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < numSamples; i++)
|
||||
{
|
||||
pIn[i] = pIn[i] * arm_calc_2pow(guard_bits);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Calculates pow(2, numShifts)
|
||||
* @param uint32_t number of shifts
|
||||
* @return pow(2, numShifts)
|
||||
*/
|
||||
uint32_t arm_calc_2pow(uint32_t numShifts)
|
||||
{
|
||||
|
||||
uint32_t i, val = 1;
|
||||
|
||||
for (i = 0; i < numShifts; i++)
|
||||
{
|
||||
val = val * 2;
|
||||
}
|
||||
|
||||
return(val);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts float to fixed q14
|
||||
* @param uint32_t number of samples in the buffer
|
||||
* @return none
|
||||
* The function converts floating point values to fixed point values
|
||||
*/
|
||||
|
||||
void arm_float_to_q14 (float *pIn, q15_t * pOut,
|
||||
uint32_t numSamples)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < numSamples; i++)
|
||||
{
|
||||
/* 16384.0f corresponds to pow(2, 14) */
|
||||
pOut[i] = (q15_t) (pIn[i] * 16384.0f);
|
||||
|
||||
pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
|
||||
|
||||
if (pIn[i] == (float) 2.0)
|
||||
{
|
||||
pOut[i] = 0x7FFF;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts float to fixed q30 format
|
||||
* @param uint32_t number of samples in the buffer
|
||||
* @return none
|
||||
* The function converts floating point values to fixed point values
|
||||
*/
|
||||
|
||||
void arm_float_to_q30 (float *pIn, q31_t * pOut,
|
||||
uint32_t numSamples)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < numSamples; i++)
|
||||
{
|
||||
/* 1073741824.0f corresponds to pow(2, 30) */
|
||||
pOut[i] = (q31_t) (pIn[i] * 1073741824.0f);
|
||||
|
||||
pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
|
||||
|
||||
if (pIn[i] == (float) 2.0)
|
||||
{
|
||||
pOut[i] = 0x7FFFFFFF;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Converts float to fixed q30 format
|
||||
* @param uint32_t number of samples in the buffer
|
||||
* @return none
|
||||
* The function converts floating point values to fixed point values
|
||||
*/
|
||||
|
||||
void arm_float_to_q29 (float *pIn, q31_t * pOut,
|
||||
uint32_t numSamples)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < numSamples; i++)
|
||||
{
|
||||
/* 1073741824.0f corresponds to pow(2, 30) */
|
||||
pOut[i] = (q31_t) (pIn[i] * 536870912.0f);
|
||||
|
||||
pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
|
||||
|
||||
if (pIn[i] == (float) 4.0)
|
||||
{
|
||||
pOut[i] = 0x7FFFFFFF;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts float to fixed q28 format
|
||||
* @param uint32_t number of samples in the buffer
|
||||
* @return none
|
||||
* The function converts floating point values to fixed point values
|
||||
*/
|
||||
|
||||
void arm_float_to_q28 (float *pIn, q31_t * pOut,
|
||||
uint32_t numSamples)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < numSamples; i++)
|
||||
{
|
||||
/* 268435456.0f corresponds to pow(2, 28) */
|
||||
pOut[i] = (q31_t) (pIn[i] * 268435456.0f);
|
||||
|
||||
pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
|
||||
|
||||
if (pIn[i] == (float) 8.0)
|
||||
{
|
||||
pOut[i] = 0x7FFFFFFF;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clip the float values to +/- 1
|
||||
* @param pIn input buffer
|
||||
* @param numSamples number of samples in the buffer
|
||||
* @return none
|
||||
* The function converts floating point values to fixed point values
|
||||
*/
|
||||
|
||||
void arm_clip_f32 (float *pIn, uint32_t numSamples)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < numSamples; i++)
|
||||
{
|
||||
if(pIn[i] > 1.0f)
|
||||
{
|
||||
pIn[i] = 1.0;
|
||||
}
|
||||
else if( pIn[i] < -1.0f)
|
||||
{
|
||||
pIn[i] = -1.0;
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
@ -0,0 +1,62 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||
*
|
||||
* $Date: 16/06/16 3:43p $Revision: V1.4.0
|
||||
*
|
||||
* Project: CMSIS DSP Library
|
||||
*
|
||||
* Title: math_helper.h
|
||||
*
|
||||
* Description: Prototypes of all helper functions required.
|
||||
*
|
||||
* Target Processor: Cortex-M4/Cortex-M3
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
|
||||
#include "arm_math.h"
|
||||
|
||||
#ifndef MATH_HELPER_H
|
||||
#define MATH_HELPER_H
|
||||
|
||||
float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize);
|
||||
void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples);
|
||||
void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
|
||||
void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
|
||||
void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples);
|
||||
void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples);
|
||||
void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples);
|
||||
void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples);
|
||||
void arm_clip_f32(float *pIn, uint32_t numSamples);
|
||||
uint32_t arm_calc_guard_bits(uint32_t num_adds);
|
||||
void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits);
|
||||
uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples);
|
||||
uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples);
|
||||
uint32_t arm_calc_2pow(uint32_t guard_bits);
|
||||
#endif
|
||||
|
||||
@ -0,0 +1,4 @@
|
||||
CMSIS DSP_Lib example arm_convolution_example for
|
||||
Cortex-M0, Cortex-M3 and Cortex-M4 with FPU
|
||||
|
||||
The example is configured for uVision Simulator
|
||||
@ -0,0 +1,195 @@
|
||||
/* Linker script to configure memory regions. */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 /* 256k */
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x08000 /* 32k */
|
||||
}
|
||||
|
||||
/* Library configurations */
|
||||
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __copy_table_start__
|
||||
* __copy_table_end__
|
||||
* __zero_table_start__
|
||||
* __zero_table_end__
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
* __Vectors_End
|
||||
* __Vectors_Size
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
KEEP(*(.vectors))
|
||||
__Vectors_End = .;
|
||||
__Vectors_Size = __Vectors_End - __Vectors;
|
||||
__end__ = .;
|
||||
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
/* To copy multiple ROM to RAM sections,
|
||||
* uncomment .copy.table section and,
|
||||
* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
|
||||
/*
|
||||
.copy.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__copy_table_start__ = .;
|
||||
LONG (__etext)
|
||||
LONG (__data_start__)
|
||||
LONG (__data_end__ - __data_start__)
|
||||
LONG (__etext2)
|
||||
LONG (__data2_start__)
|
||||
LONG (__data2_end__ - __data2_start__)
|
||||
__copy_table_end__ = .;
|
||||
} > FLASH
|
||||
*/
|
||||
|
||||
/* To clear multiple BSS sections,
|
||||
* uncomment .zero.table section and,
|
||||
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
|
||||
/*
|
||||
.zero.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__zero_table_start__ = .;
|
||||
LONG (__bss_start__)
|
||||
LONG (__bss_end__ - __bss_start__)
|
||||
LONG (__bss2_start__)
|
||||
LONG (__bss2_end__ - __bss2_start__)
|
||||
__zero_table_end__ = .;
|
||||
} > FLASH
|
||||
*/
|
||||
|
||||
__etext = .;
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
} > RAM
|
||||
|
||||
.heap (COPY):
|
||||
{
|
||||
__HeapBase = .;
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
KEEP(*(.heap*))
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy (COPY):
|
||||
{
|
||||
KEEP(*(.stack*)) /* changed MG 30.05.14 */
|
||||
} > RAM
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Check if data + heap + stack exceeds RAM limit */
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||
}
|
||||
@ -0,0 +1,320 @@
|
||||
/* File: startup_ARMCM0.S
|
||||
* Purpose: startup file for Cortex-M0 devices. Should use with
|
||||
* GCC for ARM Embedded Processors
|
||||
* Version: V2.01
|
||||
* Date: 12 June 2014
|
||||
*
|
||||
*/
|
||||
/* Copyright (c) 2011 - 2014 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
.syntax unified
|
||||
.arch armv6-m
|
||||
|
||||
.section .stack
|
||||
.align 3
|
||||
#ifdef __STACK_SIZE
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.equ Stack_Size, 0x00000400
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#ifdef __HEAP_SIZE
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 0x00000C00
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .vectors
|
||||
.align 2
|
||||
.globl __Vectors
|
||||
__Vectors:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long SVC_Handler /* SVCall Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long PendSV_Handler /* PendSV Handler */
|
||||
.long SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External interrupts */
|
||||
.long WDT_IRQHandler /* 0: Watchdog Timer */
|
||||
.long RTC_IRQHandler /* 1: Real Time Clock */
|
||||
.long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
|
||||
.long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
|
||||
.long MCIA_IRQHandler /* 4: MCIa */
|
||||
.long MCIB_IRQHandler /* 5: MCIb */
|
||||
.long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
|
||||
.long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
|
||||
.long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
|
||||
.long UART4_IRQHandler /* 9: UART4 - not connected */
|
||||
.long AACI_IRQHandler /* 10: AACI / AC97 */
|
||||
.long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
|
||||
.long ENET_IRQHandler /* 12: Ethernet */
|
||||
.long USBDC_IRQHandler /* 13: USB Device */
|
||||
.long USBHC_IRQHandler /* 14: USB Host Controller */
|
||||
.long CHLCD_IRQHandler /* 15: Character LCD */
|
||||
.long FLEXRAY_IRQHandler /* 16: Flexray */
|
||||
.long CAN_IRQHandler /* 17: CAN */
|
||||
.long LIN_IRQHandler /* 18: LIN */
|
||||
.long I2C_IRQHandler /* 19: I2C ADC/DAC */
|
||||
.long 0 /* 20: Reserved */
|
||||
.long 0 /* 21: Reserved */
|
||||
.long 0 /* 22: Reserved */
|
||||
.long 0 /* 23: Reserved */
|
||||
.long 0 /* 24: Reserved */
|
||||
.long 0 /* 25: Reserved */
|
||||
.long 0 /* 26: Reserved */
|
||||
.long 0 /* 27: Reserved */
|
||||
.long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
|
||||
.long 0 /* 29: Reserved - CPU FPGA */
|
||||
.long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
|
||||
.long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
|
||||
|
||||
.size __Vectors, . - __Vectors
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 1
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
/* Firstly it copies data from read only memory to RAM. There are two schemes
|
||||
* to copy. One can copy more than one sections. Another can only copy
|
||||
* one section. The former scheme needs more instructions and read-only
|
||||
* data to implement than the latter.
|
||||
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
|
||||
|
||||
#ifdef __STARTUP_COPY_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of triplets, each of which specify:
|
||||
* offset 0: LMA of start of a section to copy from
|
||||
* offset 4: VMA of start of a section to copy to
|
||||
* offset 8: size of the section to copy. Must be multiply of 4
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r4, =__copy_table_start__
|
||||
ldr r5, =__copy_table_end__
|
||||
|
||||
.L_loop0:
|
||||
cmp r4, r5
|
||||
bge .L_loop0_done
|
||||
ldr r1, [r4]
|
||||
ldr r2, [r4, #4]
|
||||
ldr r3, [r4, #8]
|
||||
|
||||
.L_loop0_0:
|
||||
subs r3, #4
|
||||
blt .L_loop0_0_done
|
||||
ldr r0, [r1, r3]
|
||||
str r0, [r2, r3]
|
||||
b .L_loop0_0
|
||||
|
||||
.L_loop0_0_done:
|
||||
adds r4, #12
|
||||
b .L_loop0
|
||||
|
||||
.L_loop0_done:
|
||||
#else
|
||||
/* Single section scheme.
|
||||
*
|
||||
* The ranges of copy from/to are specified by following symbols
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to
|
||||
* __data_end__: VMA of end of the section to copy to
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__data_end__
|
||||
|
||||
subs r3, r2
|
||||
ble .L_loop1_done
|
||||
|
||||
.L_loop1:
|
||||
subs r3, #4
|
||||
ldr r0, [r1,r3]
|
||||
str r0, [r2,r3]
|
||||
bgt .L_loop1
|
||||
|
||||
.L_loop1_done:
|
||||
#endif /*__STARTUP_COPY_MULTIPLE */
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define this macro to enable it in this startup.
|
||||
*
|
||||
* There are two schemes too. One can clear multiple BSS sections. Another
|
||||
* can only clear one section. The former is more size expensive than the
|
||||
* latter.
|
||||
*
|
||||
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
|
||||
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of tuples specifying:
|
||||
* offset 0: Start of a BSS section
|
||||
* offset 4: Size of this BSS section. Must be multiply of 4
|
||||
*/
|
||||
ldr r3, =__zero_table_start__
|
||||
ldr r4, =__zero_table_end__
|
||||
|
||||
.L_loop2:
|
||||
cmp r3, r4
|
||||
bge .L_loop2_done
|
||||
ldr r1, [r3]
|
||||
ldr r2, [r3, #4]
|
||||
movs r0, 0
|
||||
|
||||
.L_loop2_0:
|
||||
subs r2, #4
|
||||
blt .L_loop2_0_done
|
||||
str r0, [r1, r2]
|
||||
b .L_loop2_0
|
||||
.L_loop2_0_done:
|
||||
|
||||
adds r3, #8
|
||||
b .L_loop2
|
||||
.L_loop2_done:
|
||||
#elif defined (__STARTUP_CLEAR_BSS)
|
||||
/* Single BSS section scheme.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* Both addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
|
||||
subs r2, r1
|
||||
ble .L_loop3_done
|
||||
|
||||
.L_loop3:
|
||||
subs r2, #4
|
||||
str r0, [r1, r2]
|
||||
bgt .L_loop3
|
||||
.L_loop3_done:
|
||||
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
|
||||
|
||||
#ifndef __NO_SYSTEM_INIT
|
||||
bl SystemInit
|
||||
#endif
|
||||
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
bl __START
|
||||
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_irq_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, Default_Handler
|
||||
.endm
|
||||
|
||||
def_irq_handler NMI_Handler
|
||||
def_irq_handler HardFault_Handler
|
||||
def_irq_handler SVC_Handler
|
||||
def_irq_handler PendSV_Handler
|
||||
def_irq_handler SysTick_Handler
|
||||
|
||||
def_irq_handler WDT_IRQHandler
|
||||
def_irq_handler RTC_IRQHandler
|
||||
def_irq_handler TIM0_IRQHandler
|
||||
def_irq_handler TIM2_IRQHandler
|
||||
def_irq_handler MCIA_IRQHandler
|
||||
def_irq_handler MCIB_IRQHandler
|
||||
def_irq_handler UART0_IRQHandler
|
||||
def_irq_handler UART1_IRQHandler
|
||||
def_irq_handler UART2_IRQHandler
|
||||
def_irq_handler UART3_IRQHandler
|
||||
def_irq_handler UART4_IRQHandler
|
||||
def_irq_handler AACI_IRQHandler
|
||||
def_irq_handler CLCD_IRQHandler
|
||||
def_irq_handler ENET_IRQHandler
|
||||
def_irq_handler USBDC_IRQHandler
|
||||
def_irq_handler USBHC_IRQHandler
|
||||
def_irq_handler CHLCD_IRQHandler
|
||||
def_irq_handler FLEXRAY_IRQHandler
|
||||
def_irq_handler CAN_IRQHandler
|
||||
def_irq_handler LIN_IRQHandler
|
||||
def_irq_handler I2C_IRQHandler
|
||||
def_irq_handler CPU_CLCD_IRQHandler
|
||||
def_irq_handler SPI_IRQHandler
|
||||
|
||||
.end
|
||||
@ -0,0 +1,314 @@
|
||||
/* File: startup_ARMCM3.S
|
||||
* Purpose: startup file for Cortex-M3 devices. Should use with
|
||||
* GCC for ARM Embedded Processors
|
||||
* Version: V2.01
|
||||
* Date: 12 June 2014
|
||||
*
|
||||
*/
|
||||
/* Copyright (c) 2011 - 2014 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
.syntax unified
|
||||
.arch armv7-m
|
||||
|
||||
.section .stack
|
||||
.align 3
|
||||
#ifdef __STACK_SIZE
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.equ Stack_Size, 0x00000400
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#ifdef __HEAP_SIZE
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 0x00000C00
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .vectors
|
||||
.align 2
|
||||
.globl __Vectors
|
||||
__Vectors:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
.long MemManage_Handler /* MPU Fault Handler */
|
||||
.long BusFault_Handler /* Bus Fault Handler */
|
||||
.long UsageFault_Handler /* Usage Fault Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long SVC_Handler /* SVCall Handler */
|
||||
.long DebugMon_Handler /* Debug Monitor Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long PendSV_Handler /* PendSV Handler */
|
||||
.long SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External interrupts */
|
||||
.long WDT_IRQHandler /* 0: Watchdog Timer */
|
||||
.long RTC_IRQHandler /* 1: Real Time Clock */
|
||||
.long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
|
||||
.long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
|
||||
.long MCIA_IRQHandler /* 4: MCIa */
|
||||
.long MCIB_IRQHandler /* 5: MCIb */
|
||||
.long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
|
||||
.long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
|
||||
.long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
|
||||
.long UART4_IRQHandler /* 9: UART4 - not connected */
|
||||
.long AACI_IRQHandler /* 10: AACI / AC97 */
|
||||
.long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
|
||||
.long ENET_IRQHandler /* 12: Ethernet */
|
||||
.long USBDC_IRQHandler /* 13: USB Device */
|
||||
.long USBHC_IRQHandler /* 14: USB Host Controller */
|
||||
.long CHLCD_IRQHandler /* 15: Character LCD */
|
||||
.long FLEXRAY_IRQHandler /* 16: Flexray */
|
||||
.long CAN_IRQHandler /* 17: CAN */
|
||||
.long LIN_IRQHandler /* 18: LIN */
|
||||
.long I2C_IRQHandler /* 19: I2C ADC/DAC */
|
||||
.long 0 /* 20: Reserved */
|
||||
.long 0 /* 21: Reserved */
|
||||
.long 0 /* 22: Reserved */
|
||||
.long 0 /* 23: Reserved */
|
||||
.long 0 /* 24: Reserved */
|
||||
.long 0 /* 25: Reserved */
|
||||
.long 0 /* 26: Reserved */
|
||||
.long 0 /* 27: Reserved */
|
||||
.long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
|
||||
.long 0 /* 29: Reserved - CPU FPGA */
|
||||
.long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
|
||||
.long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
|
||||
|
||||
.size __Vectors, . - __Vectors
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 2
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
/* Firstly it copies data from read only memory to RAM. There are two schemes
|
||||
* to copy. One can copy more than one sections. Another can only copy
|
||||
* one section. The former scheme needs more instructions and read-only
|
||||
* data to implement than the latter.
|
||||
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
|
||||
|
||||
#ifdef __STARTUP_COPY_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of triplets, each of which specify:
|
||||
* offset 0: LMA of start of a section to copy from
|
||||
* offset 4: VMA of start of a section to copy to
|
||||
* offset 8: size of the section to copy. Must be multiply of 4
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r4, =__copy_table_start__
|
||||
ldr r5, =__copy_table_end__
|
||||
|
||||
.L_loop0:
|
||||
cmp r4, r5
|
||||
bge .L_loop0_done
|
||||
ldr r1, [r4]
|
||||
ldr r2, [r4, #4]
|
||||
ldr r3, [r4, #8]
|
||||
|
||||
.L_loop0_0:
|
||||
subs r3, #4
|
||||
ittt ge
|
||||
ldrge r0, [r1, r3]
|
||||
strge r0, [r2, r3]
|
||||
bge .L_loop0_0
|
||||
|
||||
adds r4, #12
|
||||
b .L_loop0
|
||||
|
||||
.L_loop0_done:
|
||||
#else
|
||||
/* Single section scheme.
|
||||
*
|
||||
* The ranges of copy from/to are specified by following symbols
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to
|
||||
* __data_end__: VMA of end of the section to copy to
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__data_end__
|
||||
|
||||
.L_loop1:
|
||||
cmp r2, r3
|
||||
ittt lt
|
||||
ldrlt r0, [r1], #4
|
||||
strlt r0, [r2], #4
|
||||
blt .L_loop1
|
||||
#endif /*__STARTUP_COPY_MULTIPLE */
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define this macro to enable it in this startup.
|
||||
*
|
||||
* There are two schemes too. One can clear multiple BSS sections. Another
|
||||
* can only clear one section. The former is more size expensive than the
|
||||
* latter.
|
||||
*
|
||||
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
|
||||
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of tuples specifying:
|
||||
* offset 0: Start of a BSS section
|
||||
* offset 4: Size of this BSS section. Must be multiply of 4
|
||||
*/
|
||||
ldr r3, =__zero_table_start__
|
||||
ldr r4, =__zero_table_end__
|
||||
|
||||
.L_loop2:
|
||||
cmp r3, r4
|
||||
bge .L_loop2_done
|
||||
ldr r1, [r3]
|
||||
ldr r2, [r3, #4]
|
||||
movs r0, 0
|
||||
|
||||
.L_loop2_0:
|
||||
subs r2, #4
|
||||
itt ge
|
||||
strge r0, [r1, r2]
|
||||
bge .L_loop2_0
|
||||
|
||||
adds r3, #8
|
||||
b .L_loop2
|
||||
.L_loop2_done:
|
||||
#elif defined (__STARTUP_CLEAR_BSS)
|
||||
/* Single BSS section scheme.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* Both addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
.L_loop3:
|
||||
cmp r1, r2
|
||||
itt lt
|
||||
strlt r0, [r1], #4
|
||||
blt .L_loop3
|
||||
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
|
||||
|
||||
#ifndef __NO_SYSTEM_INIT
|
||||
bl SystemInit
|
||||
#endif
|
||||
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
bl __START
|
||||
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_irq_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, Default_Handler
|
||||
.endm
|
||||
|
||||
def_irq_handler NMI_Handler
|
||||
def_irq_handler HardFault_Handler
|
||||
def_irq_handler MemManage_Handler
|
||||
def_irq_handler BusFault_Handler
|
||||
def_irq_handler UsageFault_Handler
|
||||
def_irq_handler SVC_Handler
|
||||
def_irq_handler DebugMon_Handler
|
||||
def_irq_handler PendSV_Handler
|
||||
def_irq_handler SysTick_Handler
|
||||
|
||||
def_irq_handler WDT_IRQHandler
|
||||
def_irq_handler RTC_IRQHandler
|
||||
def_irq_handler TIM0_IRQHandler
|
||||
def_irq_handler TIM2_IRQHandler
|
||||
def_irq_handler MCIA_IRQHandler
|
||||
def_irq_handler MCIB_IRQHandler
|
||||
def_irq_handler UART0_IRQHandler
|
||||
def_irq_handler UART1_IRQHandler
|
||||
def_irq_handler UART2_IRQHandler
|
||||
def_irq_handler UART3_IRQHandler
|
||||
def_irq_handler UART4_IRQHandler
|
||||
def_irq_handler AACI_IRQHandler
|
||||
def_irq_handler CLCD_IRQHandler
|
||||
def_irq_handler ENET_IRQHandler
|
||||
def_irq_handler USBDC_IRQHandler
|
||||
def_irq_handler USBHC_IRQHandler
|
||||
def_irq_handler CHLCD_IRQHandler
|
||||
def_irq_handler FLEXRAY_IRQHandler
|
||||
def_irq_handler CAN_IRQHandler
|
||||
def_irq_handler LIN_IRQHandler
|
||||
def_irq_handler I2C_IRQHandler
|
||||
def_irq_handler CPU_CLCD_IRQHandler
|
||||
def_irq_handler SPI_IRQHandler
|
||||
|
||||
.end
|
||||
@ -0,0 +1,314 @@
|
||||
/* File: startup_ARMCM4.S
|
||||
* Purpose: startup file for Cortex-M4 devices. Should use with
|
||||
* GCC for ARM Embedded Processors
|
||||
* Version: V2.01
|
||||
* Date: 12 June 2014
|
||||
*
|
||||
*/
|
||||
/* Copyright (c) 2011 - 2014 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
.syntax unified
|
||||
.arch armv7-m
|
||||
|
||||
.section .stack
|
||||
.align 3
|
||||
#ifdef __STACK_SIZE
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.equ Stack_Size, 0x00000400
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#ifdef __HEAP_SIZE
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 0x00000C00
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .vectors
|
||||
.align 2
|
||||
.globl __Vectors
|
||||
__Vectors:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
.long MemManage_Handler /* MPU Fault Handler */
|
||||
.long BusFault_Handler /* Bus Fault Handler */
|
||||
.long UsageFault_Handler /* Usage Fault Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long SVC_Handler /* SVCall Handler */
|
||||
.long DebugMon_Handler /* Debug Monitor Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long PendSV_Handler /* PendSV Handler */
|
||||
.long SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External interrupts */
|
||||
.long WDT_IRQHandler /* 0: Watchdog Timer */
|
||||
.long RTC_IRQHandler /* 1: Real Time Clock */
|
||||
.long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
|
||||
.long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
|
||||
.long MCIA_IRQHandler /* 4: MCIa */
|
||||
.long MCIB_IRQHandler /* 5: MCIb */
|
||||
.long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
|
||||
.long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
|
||||
.long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
|
||||
.long UART4_IRQHandler /* 9: UART4 - not connected */
|
||||
.long AACI_IRQHandler /* 10: AACI / AC97 */
|
||||
.long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
|
||||
.long ENET_IRQHandler /* 12: Ethernet */
|
||||
.long USBDC_IRQHandler /* 13: USB Device */
|
||||
.long USBHC_IRQHandler /* 14: USB Host Controller */
|
||||
.long CHLCD_IRQHandler /* 15: Character LCD */
|
||||
.long FLEXRAY_IRQHandler /* 16: Flexray */
|
||||
.long CAN_IRQHandler /* 17: CAN */
|
||||
.long LIN_IRQHandler /* 18: LIN */
|
||||
.long I2C_IRQHandler /* 19: I2C ADC/DAC */
|
||||
.long 0 /* 20: Reserved */
|
||||
.long 0 /* 21: Reserved */
|
||||
.long 0 /* 22: Reserved */
|
||||
.long 0 /* 23: Reserved */
|
||||
.long 0 /* 24: Reserved */
|
||||
.long 0 /* 25: Reserved */
|
||||
.long 0 /* 26: Reserved */
|
||||
.long 0 /* 27: Reserved */
|
||||
.long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
|
||||
.long 0 /* 29: Reserved - CPU FPGA */
|
||||
.long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
|
||||
.long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
|
||||
|
||||
.size __Vectors, . - __Vectors
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 2
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
/* Firstly it copies data from read only memory to RAM. There are two schemes
|
||||
* to copy. One can copy more than one sections. Another can only copy
|
||||
* one section. The former scheme needs more instructions and read-only
|
||||
* data to implement than the latter.
|
||||
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
|
||||
|
||||
#ifdef __STARTUP_COPY_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of triplets, each of which specify:
|
||||
* offset 0: LMA of start of a section to copy from
|
||||
* offset 4: VMA of start of a section to copy to
|
||||
* offset 8: size of the section to copy. Must be multiply of 4
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r4, =__copy_table_start__
|
||||
ldr r5, =__copy_table_end__
|
||||
|
||||
.L_loop0:
|
||||
cmp r4, r5
|
||||
bge .L_loop0_done
|
||||
ldr r1, [r4]
|
||||
ldr r2, [r4, #4]
|
||||
ldr r3, [r4, #8]
|
||||
|
||||
.L_loop0_0:
|
||||
subs r3, #4
|
||||
ittt ge
|
||||
ldrge r0, [r1, r3]
|
||||
strge r0, [r2, r3]
|
||||
bge .L_loop0_0
|
||||
|
||||
adds r4, #12
|
||||
b .L_loop0
|
||||
|
||||
.L_loop0_done:
|
||||
#else
|
||||
/* Single section scheme.
|
||||
*
|
||||
* The ranges of copy from/to are specified by following symbols
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to
|
||||
* __data_end__: VMA of end of the section to copy to
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__data_end__
|
||||
|
||||
.L_loop1:
|
||||
cmp r2, r3
|
||||
ittt lt
|
||||
ldrlt r0, [r1], #4
|
||||
strlt r0, [r2], #4
|
||||
blt .L_loop1
|
||||
#endif /*__STARTUP_COPY_MULTIPLE */
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define this macro to enable it in this startup.
|
||||
*
|
||||
* There are two schemes too. One can clear multiple BSS sections. Another
|
||||
* can only clear one section. The former is more size expensive than the
|
||||
* latter.
|
||||
*
|
||||
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
|
||||
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of tuples specifying:
|
||||
* offset 0: Start of a BSS section
|
||||
* offset 4: Size of this BSS section. Must be multiply of 4
|
||||
*/
|
||||
ldr r3, =__zero_table_start__
|
||||
ldr r4, =__zero_table_end__
|
||||
|
||||
.L_loop2:
|
||||
cmp r3, r4
|
||||
bge .L_loop2_done
|
||||
ldr r1, [r3]
|
||||
ldr r2, [r3, #4]
|
||||
movs r0, 0
|
||||
|
||||
.L_loop2_0:
|
||||
subs r2, #4
|
||||
itt ge
|
||||
strge r0, [r1, r2]
|
||||
bge .L_loop2_0
|
||||
|
||||
adds r3, #8
|
||||
b .L_loop2
|
||||
.L_loop2_done:
|
||||
#elif defined (__STARTUP_CLEAR_BSS)
|
||||
/* Single BSS section scheme.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* Both addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
.L_loop3:
|
||||
cmp r1, r2
|
||||
itt lt
|
||||
strlt r0, [r1], #4
|
||||
blt .L_loop3
|
||||
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
|
||||
|
||||
#ifndef __NO_SYSTEM_INIT
|
||||
bl SystemInit
|
||||
#endif
|
||||
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
bl __START
|
||||
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_irq_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, Default_Handler
|
||||
.endm
|
||||
|
||||
def_irq_handler NMI_Handler
|
||||
def_irq_handler HardFault_Handler
|
||||
def_irq_handler MemManage_Handler
|
||||
def_irq_handler BusFault_Handler
|
||||
def_irq_handler UsageFault_Handler
|
||||
def_irq_handler SVC_Handler
|
||||
def_irq_handler DebugMon_Handler
|
||||
def_irq_handler PendSV_Handler
|
||||
def_irq_handler SysTick_Handler
|
||||
|
||||
def_irq_handler WDT_IRQHandler
|
||||
def_irq_handler RTC_IRQHandler
|
||||
def_irq_handler TIM0_IRQHandler
|
||||
def_irq_handler TIM2_IRQHandler
|
||||
def_irq_handler MCIA_IRQHandler
|
||||
def_irq_handler MCIB_IRQHandler
|
||||
def_irq_handler UART0_IRQHandler
|
||||
def_irq_handler UART1_IRQHandler
|
||||
def_irq_handler UART2_IRQHandler
|
||||
def_irq_handler UART3_IRQHandler
|
||||
def_irq_handler UART4_IRQHandler
|
||||
def_irq_handler AACI_IRQHandler
|
||||
def_irq_handler CLCD_IRQHandler
|
||||
def_irq_handler ENET_IRQHandler
|
||||
def_irq_handler USBDC_IRQHandler
|
||||
def_irq_handler USBHC_IRQHandler
|
||||
def_irq_handler CHLCD_IRQHandler
|
||||
def_irq_handler FLEXRAY_IRQHandler
|
||||
def_irq_handler CAN_IRQHandler
|
||||
def_irq_handler LIN_IRQHandler
|
||||
def_irq_handler I2C_IRQHandler
|
||||
def_irq_handler CPU_CLCD_IRQHandler
|
||||
def_irq_handler SPI_IRQHandler
|
||||
|
||||
.end
|
||||
@ -0,0 +1,80 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_ARMCM0.c
|
||||
* @brief CMSIS Device System Source File for
|
||||
* ARMCM0 Device Series
|
||||
* @version V1.08
|
||||
* @date 23. November 2012
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#include "ARMCM0.h"
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __HSI ( 8000000UL)
|
||||
#define __XTAL ( 5000000UL) /* Oscillator frequency */
|
||||
|
||||
#define __SYSTEM_CLOCK (5*__XTAL)
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||
{
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
@ -0,0 +1,84 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_ARMCM3.c
|
||||
* @brief CMSIS Device System Source File for
|
||||
* ARMCM3 Device Series
|
||||
* @version V1.08
|
||||
* @date 23. November 2012
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#include "ARMCM3.h"
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __HSI ( 8000000UL)
|
||||
#define __XTAL ( 5000000UL) /* Oscillator frequency */
|
||||
|
||||
#define __SYSTEM_CLOCK (5*__XTAL)
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||
{
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
|
||||
#ifdef UNALIGNED_SUPPORT_DISABLE
|
||||
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
|
||||
#endif
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
@ -0,0 +1,93 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_ARMCM4.c
|
||||
* @brief CMSIS Device System Source File for
|
||||
* ARMCM4 Device Series
|
||||
* @version V1.09
|
||||
* @date 26. August 2014
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
#if defined (ARMCM4)
|
||||
#include "ARMCM4.h"
|
||||
#elif defined (ARMCM4_FP)
|
||||
#include "ARMCM4_FP.h"
|
||||
#else
|
||||
#error device not specified!
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __HSI ( 8000000UL)
|
||||
#define __XTAL ( 5000000UL) /* Oscillator frequency */
|
||||
|
||||
#define __SYSTEM_CLOCK (5*__XTAL)
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||
{
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
#if (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
|
||||
(3UL << 11*2) ); /* set CP11 Full Access */
|
||||
#endif
|
||||
|
||||
#ifdef UNALIGNED_SUPPORT_DISABLE
|
||||
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
|
||||
#endif
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
@ -0,0 +1,15 @@
|
||||
|
||||
/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions
|
||||
|
||||
The file can be executed in the following way:
|
||||
1) manually from uVision command window (in debug mode) using command:
|
||||
INCLUIDE arm_convolution_example.ini
|
||||
|
||||
*/
|
||||
|
||||
|
||||
// usual initialisation for target setup
|
||||
MAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash
|
||||
MAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,246 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
|
||||
*
|
||||
* $Date: 16/06/16 3:43p $Revision: V1.4.0
|
||||
*
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_convolution_example_f32.c
|
||||
*
|
||||
* Description: Example code demonstrating Convolution of two input signals using fft.
|
||||
*
|
||||
* Target Processor: Cortex-M4/Cortex-M3
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
/**
|
||||
* @ingroup groupExamples
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup ConvolutionExample Convolution Example
|
||||
*
|
||||
* \par Description:
|
||||
* \par
|
||||
* Demonstrates the convolution theorem with the use of the Complex FFT, Complex-by-Complex
|
||||
* Multiplication, and Support Functions.
|
||||
*
|
||||
* \par Algorithm:
|
||||
* \par
|
||||
* The convolution theorem states that convolution in the time domain corresponds to
|
||||
* multiplication in the frequency domain. Therefore, the Fourier transform of the convoution of
|
||||
* two signals is equal to the product of their individual Fourier transforms.
|
||||
* The Fourier transform of a signal can be evaluated efficiently using the Fast Fourier Transform (FFT).
|
||||
* \par
|
||||
* Two input signals, <code>a[n]</code> and <code>b[n]</code>, with lengths \c n1 and \c n2 respectively,
|
||||
* are zero padded so that their lengths become \c N, which is greater than or equal to <code>(n1+n2-1)</code>
|
||||
* and is a power of 4 as FFT implementation is radix-4.
|
||||
* The convolution of <code>a[n]</code> and <code>b[n]</code> is obtained by taking the FFT of the input
|
||||
* signals, multiplying the Fourier transforms of the two signals, and taking the inverse FFT of
|
||||
* the multiplied result.
|
||||
* \par
|
||||
* This is denoted by the following equations:
|
||||
* <pre> A[k] = FFT(a[n],N)
|
||||
* B[k] = FFT(b[n],N)
|
||||
* conv(a[n], b[n]) = IFFT(A[k] * B[k], N)</pre>
|
||||
* where <code>A[k]</code> and <code>B[k]</code> are the N-point FFTs of the signals <code>a[n]</code>
|
||||
* and <code>b[n]</code> respectively.
|
||||
* The length of the convolved signal is <code>(n1+n2-1)</code>.
|
||||
*
|
||||
* \par Block Diagram:
|
||||
* \par
|
||||
* \image html Convolution.gif
|
||||
*
|
||||
* \par Variables Description:
|
||||
* \par
|
||||
* \li \c testInputA_f32 points to the first input sequence
|
||||
* \li \c srcALen length of the first input sequence
|
||||
* \li \c testInputB_f32 points to the second input sequence
|
||||
* \li \c srcBLen length of the second input sequence
|
||||
* \li \c outLen length of convolution output sequence, <code>(srcALen + srcBLen - 1)</code>
|
||||
* \li \c AxB points to the output array where the product of individual FFTs of inputs is stored.
|
||||
*
|
||||
* \par CMSIS DSP Software Library Functions Used:
|
||||
* \par
|
||||
* - arm_fill_f32()
|
||||
* - arm_copy_f32()
|
||||
* - arm_cfft_radix4_init_f32()
|
||||
* - arm_cfft_radix4_f32()
|
||||
* - arm_cmplx_mult_cmplx_f32()
|
||||
*
|
||||
* <b> Refer </b>
|
||||
* \link arm_convolution_example_f32.c \endlink
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
/** \example arm_convolution_example_f32.c
|
||||
*/
|
||||
|
||||
#include "arm_math.h"
|
||||
#include "math_helper.h"
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
* Defines each of the tests performed
|
||||
* ------------------------------------------------------------------- */
|
||||
#define MAX_BLOCKSIZE 128
|
||||
#define DELTA (0.000001f)
|
||||
#define SNR_THRESHOLD 90
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
* Declare I/O buffers
|
||||
* ------------------------------------------------------------------- */
|
||||
float32_t Ak[MAX_BLOCKSIZE]; /* Input A */
|
||||
float32_t Bk[MAX_BLOCKSIZE]; /* Input B */
|
||||
float32_t AxB[MAX_BLOCKSIZE * 2]; /* Output */
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
* Test input data for Floating point Convolution example for 32-blockSize
|
||||
* Generated by the MATLAB randn() function
|
||||
* ------------------------------------------------------------------- */
|
||||
float32_t testInputA_f32[64] =
|
||||
{
|
||||
-0.808920, 1.357369, 1.180861, -0.504544, 1.762637, -0.703285,
|
||||
1.696966, 0.620571, -0.151093, -0.100235, -0.872382, -0.403579,
|
||||
-0.860749, -0.382648, -1.052338, 0.128113, -0.646269, 1.093377,
|
||||
-2.209198, 0.471706, 0.408901, 1.266242, 0.598252, 1.176827,
|
||||
-0.203421, 0.213596, -0.851964, -0.466958, 0.021841, -0.698938,
|
||||
-0.604107, 0.461778, -0.318219, 0.942520, 0.577585, 0.417619,
|
||||
0.614665, 0.563679, -1.295073, -0.764437, 0.952194, -0.859222,
|
||||
-0.618554, -2.268542, -1.210592, 1.655853, -2.627219, -0.994249,
|
||||
-1.374704, 0.343799, 0.025619, 1.227481, -0.708031, 0.069355,
|
||||
-1.845228, -1.570886, 1.010668, -1.802084, 1.630088, 1.286090,
|
||||
-0.161050, -0.940794, 0.367961, 0.291907
|
||||
|
||||
};
|
||||
|
||||
float32_t testInputB_f32[64] =
|
||||
{
|
||||
0.933724, 0.046881, 1.316470, 0.438345, 0.332682, 2.094885,
|
||||
0.512081, 0.035546, 0.050894, -2.320371, 0.168711, -1.830493,
|
||||
-0.444834, -1.003242, -0.531494, -1.365600, -0.155420, -0.757692,
|
||||
-0.431880, -0.380021, 0.096243, -0.695835, 0.558850, -1.648962,
|
||||
0.020369, -0.363630, 0.887146, 0.845503, -0.252864, -0.330397,
|
||||
1.269131, -1.109295, -1.027876, 0.135940, 0.116721, -0.293399,
|
||||
-1.349799, 0.166078, -0.802201, 0.369367, -0.964568, -2.266011,
|
||||
0.465178, 0.651222, -0.325426, 0.320245, -0.784178, -0.579456,
|
||||
0.093374, 0.604778, -0.048225, 0.376297, -0.394412, 0.578182,
|
||||
-1.218141, -1.387326, 0.692462, -0.631297, 0.153137, -0.638952,
|
||||
0.635474, -0.970468, 1.334057, -0.111370
|
||||
};
|
||||
|
||||
const float testRefOutput_f32[127] =
|
||||
{
|
||||
-0.818943, 1.229484, -0.533664, 1.016604, 0.341875, -1.963656,
|
||||
5.171476, 3.478033, 7.616361, 6.648384, 0.479069, 1.792012,
|
||||
-1.295591, -7.447818, 0.315830, -10.657445, -2.483469, -6.524236,
|
||||
-7.380591, -3.739005, -8.388957, 0.184147, -1.554888, 3.786508,
|
||||
-1.684421, 5.400610, -1.578126, 7.403361, 8.315999, 2.080267,
|
||||
11.077776, 2.749673, 7.138962, 2.748762, 0.660363, 0.981552,
|
||||
1.442275, 0.552721, -2.576892, 4.703989, 0.989156, 8.759344,
|
||||
-0.564825, -3.994680, 0.954710, -5.014144, 6.592329, 1.599488,
|
||||
-13.979146, -0.391891, -4.453369, -2.311242, -2.948764, 1.761415,
|
||||
-0.138322, 10.433007, -2.309103, 4.297153, 8.535523, 3.209462,
|
||||
8.695819, 5.569919, 2.514304, 5.582029, 2.060199, 0.642280,
|
||||
7.024616, 1.686615, -6.481756, 1.343084, -3.526451, 1.099073,
|
||||
-2.965764, -0.173723, -4.111484, 6.528384, -6.965658, 1.726291,
|
||||
1.535172, 11.023435, 2.338401, -4.690188, 1.298210, 3.943885,
|
||||
8.407885, 5.168365, 0.684131, 1.559181, 1.859998, 2.852417,
|
||||
8.574070, -6.369078, 6.023458, 11.837963, -6.027632, 4.469678,
|
||||
-6.799093, -2.674048, 6.250367, -6.809971, -3.459360, 9.112410,
|
||||
-2.711621, -1.336678, 1.564249, -1.564297, -1.296760, 8.904013,
|
||||
-3.230109, 6.878013, -7.819823, 3.369909, -1.657410, -2.007358,
|
||||
-4.112825, 1.370685, -3.420525, -6.276605, 3.244873, -3.352638,
|
||||
1.545372, 0.902211, 0.197489, -1.408732, 0.523390, 0.348440, 0
|
||||
};
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
* Declare Global variables
|
||||
* ------------------------------------------------------------------- */
|
||||
uint32_t srcALen = 64; /* Length of Input A */
|
||||
uint32_t srcBLen = 64; /* Length of Input B */
|
||||
uint32_t outLen; /* Length of convolution output */
|
||||
float32_t snr; /* output SNR */
|
||||
|
||||
int32_t main(void)
|
||||
{
|
||||
arm_status status; /* Status of the example */
|
||||
arm_cfft_radix4_instance_f32 cfft_instance; /* CFFT Structure instance */
|
||||
|
||||
/* CFFT Structure instance pointer */
|
||||
arm_cfft_radix4_instance_f32 *cfft_instance_ptr =
|
||||
(arm_cfft_radix4_instance_f32*) &cfft_instance;
|
||||
|
||||
/* output length of convolution */
|
||||
outLen = srcALen + srcBLen - 1;
|
||||
|
||||
/* Initialise the fft input buffers with all zeros */
|
||||
arm_fill_f32(0.0, Ak, MAX_BLOCKSIZE);
|
||||
arm_fill_f32(0.0, Bk, MAX_BLOCKSIZE);
|
||||
|
||||
/* Copy the input values to the fft input buffers */
|
||||
arm_copy_f32(testInputA_f32, Ak, MAX_BLOCKSIZE/2);
|
||||
arm_copy_f32(testInputB_f32, Bk, MAX_BLOCKSIZE/2);
|
||||
|
||||
/* Initialize the CFFT function to compute 64 point fft */
|
||||
status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 0, 1);
|
||||
|
||||
/* Transform input a[n] from time domain to frequency domain A[k] */
|
||||
arm_cfft_radix4_f32(cfft_instance_ptr, Ak);
|
||||
/* Transform input b[n] from time domain to frequency domain B[k] */
|
||||
arm_cfft_radix4_f32(cfft_instance_ptr, Bk);
|
||||
|
||||
/* Complex Multiplication of the two input buffers in frequency domain */
|
||||
arm_cmplx_mult_cmplx_f32(Ak, Bk, AxB, MAX_BLOCKSIZE/2);
|
||||
|
||||
/* Initialize the CIFFT function to compute 64 point ifft */
|
||||
status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 1, 1);
|
||||
|
||||
/* Transform the multiplication output from frequency domain to time domain,
|
||||
that gives the convolved output */
|
||||
arm_cfft_radix4_f32(cfft_instance_ptr, AxB);
|
||||
|
||||
/* SNR Calculation */
|
||||
snr = arm_snr_f32((float32_t *)testRefOutput_f32, AxB, srcALen + srcBLen - 1);
|
||||
|
||||
/* Compare the SNR with threshold to test whether the
|
||||
computed output is matched with the reference output values. */
|
||||
if( snr > SNR_THRESHOLD)
|
||||
{
|
||||
status = ARM_MATH_SUCCESS;
|
||||
}
|
||||
|
||||
if( status != ARM_MATH_SUCCESS)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
while(1); /* main function does not return */
|
||||
}
|
||||
|
||||
/** \endlink */
|
||||
@ -0,0 +1,457 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
|
||||
*
|
||||
* $Date: 16/06/16 3:43p $Revision: V1.4.0
|
||||
*
|
||||
* Project: CMSIS DSP Library
|
||||
*
|
||||
* Title: math_helper.c
|
||||
*
|
||||
* Description: Definition of all helper functions required.
|
||||
*
|
||||
* Target Processor: Cortex-M4/Cortex-M3
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
* Include standard header files
|
||||
* -------------------------------------------------------------------- */
|
||||
#include<math.h>
|
||||
|
||||
/* ----------------------------------------------------------------------
|
||||
* Include project header files
|
||||
* -------------------------------------------------------------------- */
|
||||
#include "math_helper.h"
|
||||
|
||||
/**
|
||||
* @brief Caluclation of SNR
|
||||
* @param float* Pointer to the reference buffer
|
||||
* @param float* Pointer to the test buffer
|
||||
* @param uint32_t total number of samples
|
||||
* @return float SNR
|
||||
* The function Caluclates signal to noise ratio for the reference output
|
||||
* and test output
|
||||
*/
|
||||
|
||||
float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize)
|
||||
{
|
||||
float EnergySignal = 0.0, EnergyError = 0.0;
|
||||
uint32_t i;
|
||||
float SNR;
|
||||
int temp;
|
||||
int *test;
|
||||
|
||||
for (i = 0; i < buffSize; i++)
|
||||
{
|
||||
/* Checking for a NAN value in pRef array */
|
||||
test = (int *)(&pRef[i]);
|
||||
temp = *test;
|
||||
|
||||
if(temp == 0x7FC00000)
|
||||
{
|
||||
return(0);
|
||||
}
|
||||
|
||||
/* Checking for a NAN value in pTest array */
|
||||
test = (int *)(&pTest[i]);
|
||||
temp = *test;
|
||||
|
||||
if(temp == 0x7FC00000)
|
||||
{
|
||||
return(0);
|
||||
}
|
||||
EnergySignal += pRef[i] * pRef[i];
|
||||
EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]);
|
||||
}
|
||||
|
||||
/* Checking for a NAN value in EnergyError */
|
||||
test = (int *)(&EnergyError);
|
||||
temp = *test;
|
||||
|
||||
if(temp == 0x7FC00000)
|
||||
{
|
||||
return(0);
|
||||
}
|
||||
|
||||
|
||||
SNR = 10 * log10 (EnergySignal / EnergyError);
|
||||
|
||||
return (SNR);
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Provide guard bits for Input buffer
|
||||
* @param q15_t* Pointer to input buffer
|
||||
* @param uint32_t blockSize
|
||||
* @param uint32_t guard_bits
|
||||
* @return none
|
||||
* The function Provides the guard bits for the buffer
|
||||
* to avoid overflow
|
||||
*/
|
||||
|
||||
void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize,
|
||||
uint32_t guard_bits)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < blockSize; i++)
|
||||
{
|
||||
input_buf[i] = input_buf[i] >> guard_bits;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Converts float to fixed in q12.20 format
|
||||
* @param uint32_t number of samples in the buffer
|
||||
* @return none
|
||||
* The function converts floating point values to fixed point(q12.20) values
|
||||
*/
|
||||
|
||||
void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < numSamples; i++)
|
||||
{
|
||||
/* 1048576.0f corresponds to pow(2, 20) */
|
||||
pOut[i] = (q31_t) (pIn[i] * 1048576.0f);
|
||||
|
||||
pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
|
||||
|
||||
if (pIn[i] == (float) 1.0)
|
||||
{
|
||||
pOut[i] = 0x000FFFFF;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Compare MATLAB Reference Output and ARM Test output
|
||||
* @param q15_t* Pointer to Ref buffer
|
||||
* @param q15_t* Pointer to Test buffer
|
||||
* @param uint32_t number of samples in the buffer
|
||||
* @return none
|
||||
*/
|
||||
|
||||
uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples)
|
||||
{
|
||||
uint32_t i;
|
||||
int32_t diff, diffCrnt = 0;
|
||||
uint32_t maxDiff = 0;
|
||||
|
||||
for (i = 0; i < numSamples; i++)
|
||||
{
|
||||
diff = pIn[i] - pOut[i];
|
||||
diffCrnt = (diff > 0) ? diff : -diff;
|
||||
|
||||
if(diffCrnt > maxDiff)
|
||||
{
|
||||
maxDiff = diffCrnt;
|
||||
}
|
||||
}
|
||||
|
||||
return(maxDiff);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Compare MATLAB Reference Output and ARM Test output
|
||||
* @param q31_t* Pointer to Ref buffer
|
||||
* @param q31_t* Pointer to Test buffer
|
||||
* @param uint32_t number of samples in the buffer
|
||||
* @return none
|
||||
*/
|
||||
|
||||
uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples)
|
||||
{
|
||||
uint32_t i;
|
||||
int32_t diff, diffCrnt = 0;
|
||||
uint32_t maxDiff = 0;
|
||||
|
||||
for (i = 0; i < numSamples; i++)
|
||||
{
|
||||
diff = pIn[i] - pOut[i];
|
||||
diffCrnt = (diff > 0) ? diff : -diff;
|
||||
|
||||
if(diffCrnt > maxDiff)
|
||||
{
|
||||
maxDiff = diffCrnt;
|
||||
}
|
||||
}
|
||||
|
||||
return(maxDiff);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Provide guard bits for Input buffer
|
||||
* @param q31_t* Pointer to input buffer
|
||||
* @param uint32_t blockSize
|
||||
* @param uint32_t guard_bits
|
||||
* @return none
|
||||
* The function Provides the guard bits for the buffer
|
||||
* to avoid overflow
|
||||
*/
|
||||
|
||||
void arm_provide_guard_bits_q31 (q31_t * input_buf,
|
||||
uint32_t blockSize,
|
||||
uint32_t guard_bits)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < blockSize; i++)
|
||||
{
|
||||
input_buf[i] = input_buf[i] >> guard_bits;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Provide guard bits for Input buffer
|
||||
* @param q31_t* Pointer to input buffer
|
||||
* @param uint32_t blockSize
|
||||
* @param uint32_t guard_bits
|
||||
* @return none
|
||||
* The function Provides the guard bits for the buffer
|
||||
* to avoid overflow
|
||||
*/
|
||||
|
||||
void arm_provide_guard_bits_q7 (q7_t * input_buf,
|
||||
uint32_t blockSize,
|
||||
uint32_t guard_bits)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < blockSize; i++)
|
||||
{
|
||||
input_buf[i] = input_buf[i] >> guard_bits;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Caluclates number of guard bits
|
||||
* @param uint32_t number of additions
|
||||
* @return none
|
||||
* The function Caluclates the number of guard bits
|
||||
* depending on the numtaps
|
||||
*/
|
||||
|
||||
uint32_t arm_calc_guard_bits (uint32_t num_adds)
|
||||
{
|
||||
uint32_t i = 1, j = 0;
|
||||
|
||||
if (num_adds == 1)
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
|
||||
while (i < num_adds)
|
||||
{
|
||||
i = i * 2;
|
||||
j++;
|
||||
}
|
||||
|
||||
return (j);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Converts Q15 to floating-point
|
||||
* @param uint32_t number of samples in the buffer
|
||||
* @return none
|
||||
*/
|
||||
|
||||
void arm_apply_guard_bits (float32_t * pIn,
|
||||
uint32_t numSamples,
|
||||
uint32_t guard_bits)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < numSamples; i++)
|
||||
{
|
||||
pIn[i] = pIn[i] * arm_calc_2pow(guard_bits);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Calculates pow(2, numShifts)
|
||||
* @param uint32_t number of shifts
|
||||
* @return pow(2, numShifts)
|
||||
*/
|
||||
uint32_t arm_calc_2pow(uint32_t numShifts)
|
||||
{
|
||||
|
||||
uint32_t i, val = 1;
|
||||
|
||||
for (i = 0; i < numShifts; i++)
|
||||
{
|
||||
val = val * 2;
|
||||
}
|
||||
|
||||
return(val);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts float to fixed q14
|
||||
* @param uint32_t number of samples in the buffer
|
||||
* @return none
|
||||
* The function converts floating point values to fixed point values
|
||||
*/
|
||||
|
||||
void arm_float_to_q14 (float *pIn, q15_t * pOut,
|
||||
uint32_t numSamples)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < numSamples; i++)
|
||||
{
|
||||
/* 16384.0f corresponds to pow(2, 14) */
|
||||
pOut[i] = (q15_t) (pIn[i] * 16384.0f);
|
||||
|
||||
pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
|
||||
|
||||
if (pIn[i] == (float) 2.0)
|
||||
{
|
||||
pOut[i] = 0x7FFF;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts float to fixed q30 format
|
||||
* @param uint32_t number of samples in the buffer
|
||||
* @return none
|
||||
* The function converts floating point values to fixed point values
|
||||
*/
|
||||
|
||||
void arm_float_to_q30 (float *pIn, q31_t * pOut,
|
||||
uint32_t numSamples)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < numSamples; i++)
|
||||
{
|
||||
/* 1073741824.0f corresponds to pow(2, 30) */
|
||||
pOut[i] = (q31_t) (pIn[i] * 1073741824.0f);
|
||||
|
||||
pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
|
||||
|
||||
if (pIn[i] == (float) 2.0)
|
||||
{
|
||||
pOut[i] = 0x7FFFFFFF;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Converts float to fixed q30 format
|
||||
* @param uint32_t number of samples in the buffer
|
||||
* @return none
|
||||
* The function converts floating point values to fixed point values
|
||||
*/
|
||||
|
||||
void arm_float_to_q29 (float *pIn, q31_t * pOut,
|
||||
uint32_t numSamples)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < numSamples; i++)
|
||||
{
|
||||
/* 1073741824.0f corresponds to pow(2, 30) */
|
||||
pOut[i] = (q31_t) (pIn[i] * 536870912.0f);
|
||||
|
||||
pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
|
||||
|
||||
if (pIn[i] == (float) 4.0)
|
||||
{
|
||||
pOut[i] = 0x7FFFFFFF;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts float to fixed q28 format
|
||||
* @param uint32_t number of samples in the buffer
|
||||
* @return none
|
||||
* The function converts floating point values to fixed point values
|
||||
*/
|
||||
|
||||
void arm_float_to_q28 (float *pIn, q31_t * pOut,
|
||||
uint32_t numSamples)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < numSamples; i++)
|
||||
{
|
||||
/* 268435456.0f corresponds to pow(2, 28) */
|
||||
pOut[i] = (q31_t) (pIn[i] * 268435456.0f);
|
||||
|
||||
pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
|
||||
|
||||
if (pIn[i] == (float) 8.0)
|
||||
{
|
||||
pOut[i] = 0x7FFFFFFF;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clip the float values to +/- 1
|
||||
* @param pIn input buffer
|
||||
* @param numSamples number of samples in the buffer
|
||||
* @return none
|
||||
* The function converts floating point values to fixed point values
|
||||
*/
|
||||
|
||||
void arm_clip_f32 (float *pIn, uint32_t numSamples)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < numSamples; i++)
|
||||
{
|
||||
if(pIn[i] > 1.0f)
|
||||
{
|
||||
pIn[i] = 1.0;
|
||||
}
|
||||
else if( pIn[i] < -1.0f)
|
||||
{
|
||||
pIn[i] = -1.0;
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
@ -0,0 +1,62 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||
*
|
||||
* $Date: 16/06/16 3:43p $Revision: V1.4.0
|
||||
*
|
||||
* Project: CMSIS DSP Library
|
||||
*
|
||||
* Title: math_helper.h
|
||||
*
|
||||
* Description: Prototypes of all helper functions required.
|
||||
*
|
||||
* Target Processor: Cortex-M4/Cortex-M3
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
|
||||
#include "arm_math.h"
|
||||
|
||||
#ifndef MATH_HELPER_H
|
||||
#define MATH_HELPER_H
|
||||
|
||||
float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize);
|
||||
void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples);
|
||||
void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
|
||||
void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
|
||||
void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples);
|
||||
void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples);
|
||||
void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples);
|
||||
void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples);
|
||||
void arm_clip_f32(float *pIn, uint32_t numSamples);
|
||||
uint32_t arm_calc_guard_bits(uint32_t num_adds);
|
||||
void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits);
|
||||
uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples);
|
||||
uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples);
|
||||
uint32_t arm_calc_2pow(uint32_t guard_bits);
|
||||
#endif
|
||||
|
||||
@ -0,0 +1,4 @@
|
||||
CMSIS DSP_Lib example arm_dotproduct_example for
|
||||
Cortex-M0, Cortex-M3 and Cortex-M4 with FPU
|
||||
|
||||
The example is configured for uVision Simulator
|
||||
@ -0,0 +1,253 @@
|
||||
;/**************************************************************************//**
|
||||
; * @file startup_ARMCM0.s
|
||||
; * @brief CMSIS Core Device Startup File for
|
||||
; * ARMCM0 Device Series
|
||||
; * @version V1.08
|
||||
; * @date 23. November 2012
|
||||
; *
|
||||
; * @note
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
;/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
; ---------------------------------------------------------------------------*/
|
||||
;/*
|
||||
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
;*/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000C00
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WDT_IRQHandler ; 0: Watchdog Timer
|
||||
DCD RTC_IRQHandler ; 1: Real Time Clock
|
||||
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
|
||||
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
|
||||
DCD MCIA_IRQHandler ; 4: MCIa
|
||||
DCD MCIB_IRQHandler ; 5: MCIb
|
||||
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
|
||||
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
|
||||
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
|
||||
DCD UART4_IRQHandler ; 9: UART4 - not connected
|
||||
DCD AACI_IRQHandler ; 10: AACI / AC97
|
||||
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
|
||||
DCD ENET_IRQHandler ; 12: Ethernet
|
||||
DCD USBDC_IRQHandler ; 13: USB Device
|
||||
DCD USBHC_IRQHandler ; 14: USB Host Controller
|
||||
DCD CHLCD_IRQHandler ; 15: Character LCD
|
||||
DCD FLEXRAY_IRQHandler ; 16: Flexray
|
||||
DCD CAN_IRQHandler ; 17: CAN
|
||||
DCD LIN_IRQHandler ; 18: LIN
|
||||
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
|
||||
DCD 0 ; 20: Reserved
|
||||
DCD 0 ; 21: Reserved
|
||||
DCD 0 ; 22: Reserved
|
||||
DCD 0 ; 23: Reserved
|
||||
DCD 0 ; 24: Reserved
|
||||
DCD 0 ; 25: Reserved
|
||||
DCD 0 ; 26: Reserved
|
||||
DCD 0 ; 27: Reserved
|
||||
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
|
||||
DCD 0 ; 29: Reserved - CPU FPGA
|
||||
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
|
||||
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT TIM0_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT MCIA_IRQHandler [WEAK]
|
||||
EXPORT MCIB_IRQHandler [WEAK]
|
||||
EXPORT UART0_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT UART2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT AACI_IRQHandler [WEAK]
|
||||
EXPORT CLCD_IRQHandler [WEAK]
|
||||
EXPORT ENET_IRQHandler [WEAK]
|
||||
EXPORT USBDC_IRQHandler [WEAK]
|
||||
EXPORT USBHC_IRQHandler [WEAK]
|
||||
EXPORT CHLCD_IRQHandler [WEAK]
|
||||
EXPORT FLEXRAY_IRQHandler [WEAK]
|
||||
EXPORT CAN_IRQHandler [WEAK]
|
||||
EXPORT LIN_IRQHandler [WEAK]
|
||||
EXPORT I2C_IRQHandler [WEAK]
|
||||
EXPORT CPU_CLCD_IRQHandler [WEAK]
|
||||
EXPORT SPI_IRQHandler [WEAK]
|
||||
|
||||
WDT_IRQHandler
|
||||
RTC_IRQHandler
|
||||
TIM0_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
MCIA_IRQHandler
|
||||
MCIB_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
AACI_IRQHandler
|
||||
CLCD_IRQHandler
|
||||
ENET_IRQHandler
|
||||
USBDC_IRQHandler
|
||||
USBHC_IRQHandler
|
||||
CHLCD_IRQHandler
|
||||
FLEXRAY_IRQHandler
|
||||
CAN_IRQHandler
|
||||
LIN_IRQHandler
|
||||
I2C_IRQHandler
|
||||
CPU_CLCD_IRQHandler
|
||||
SPI_IRQHandler
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
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Reference in New Issue
Block a user