352 lines
14 KiB
Plaintext
352 lines
14 KiB
Plaintext
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; generated by Component: ARM Compiler 5.06 update 4 (build 422) Tool: ArmCC [4d3604]
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; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\obj\adc.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\adc.d --cpu=Cortex-M0 --apcs=interwork -O3 --diag_suppress=9931 -I..\..\..\Library\CMSIS\Include -I..\..\..\Library\Device\Nuvoton\Mini58Series\Include -I..\..\..\Library\StdDriver\inc -I..\..\Template -I..\..\..\Library\StdDriver\driver -I.\RTE\_Template -ID:\Keil_v5\ARM\PACK\Nuvoton\NuMicro_DFP\1.0.9\Device\Mini58\Include -ID:\Keil_v5\ARM\CMSIS\Include -D__MICROLIB -D__UVISION_VERSION=523 --omf_browse=.\obj\adc.crf ..\..\..\Library\StdDriver\src\adc.c]
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THUMB
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AREA ||i.ADC_Close||, CODE, READONLY, ALIGN=1
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ADC_Close PROC
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;;;57 */
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;;;58 void ADC_Close(ADC_T *adc)
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000000 2005 MOVS r0,#5
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;;;59 {
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;;;60 SYS->IPRST1 |= SYS_IPRST1_ADCRST_Msk;
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000002 0700 LSLS r0,r0,#28
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000004 68c2 LDR r2,[r0,#0xc]
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000006 2101 MOVS r1,#1
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000008 0709 LSLS r1,r1,#28
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00000a 430a ORRS r2,r2,r1
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00000c 60c2 STR r2,[r0,#0xc]
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;;;61 SYS->IPRST1 &= ~SYS_IPRST1_ADCRST_Msk;
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00000e 68c2 LDR r2,[r0,#0xc]
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000010 438a BICS r2,r2,r1
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000012 60c2 STR r2,[r0,#0xc]
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;;;62 return;
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;;;63
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;;;64 }
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000014 4770 BX lr
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;;;65
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ENDP
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AREA ||i.ADC_DisableHWTrigger||, CODE, READONLY, ALIGN=2
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ADC_DisableHWTrigger PROC
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;;;98 */
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;;;99 void ADC_DisableHWTrigger(ADC_T *adc)
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000000 4803 LDR r0,|L2.16|
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;;;100 {
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;;;101 ADC->CTL &= ~(ADC_TRIGGER_BY_PWM | ADC_RISING_EDGE_TRIGGER | ADC_CTL_HWTRGEN_Msk);
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000002 6a01 LDR r1,[r0,#0x20]
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000004 22ff MOVS r2,#0xff
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000006 3271 ADDS r2,r2,#0x71
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000008 4391 BICS r1,r1,r2
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00000a 6201 STR r1,[r0,#0x20]
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;;;102 return;
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;;;103 }
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00000c 4770 BX lr
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;;;104
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ENDP
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00000e 0000 DCW 0x0000
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|L2.16|
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DCD 0x400e0000
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AREA ||i.ADC_DisableInt||, CODE, READONLY, ALIGN=2
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ADC_DisableInt PROC
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;;;164 */
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;;;165 void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask)
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000000 07cb LSLS r3,r1,#31
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;;;166 {
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;;;167 if(u32Mask & ADC_ADIF_INT)
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;;;168 ADC->CTL &= ~ADC_CTL_ADCIEN_Msk;
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000002 4809 LDR r0,|L3.40|
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000004 2202 MOVS r2,#2
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000006 2b00 CMP r3,#0 ;167
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000008 d002 BEQ |L3.16|
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00000a 6a03 LDR r3,[r0,#0x20]
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00000c 4393 BICS r3,r3,r2
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00000e 6203 STR r3,[r0,#0x20]
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|L3.16|
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;;;169 if(u32Mask & ADC_CMP0_INT)
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000010 078b LSLS r3,r1,#30
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000012 d502 BPL |L3.26|
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;;;170 ADC->CMP0 &= ~ADC_CMP0_ADCMPIE_Msk;
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000014 6a83 LDR r3,[r0,#0x28]
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000016 4393 BICS r3,r3,r2
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000018 6283 STR r3,[r0,#0x28]
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|L3.26|
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;;;171 if(u32Mask & ADC_CMP1_INT)
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00001a 0749 LSLS r1,r1,#29
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00001c d502 BPL |L3.36|
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;;;172 ADC->CMP1 &= ~ADC_CMP1_ADCMPIE_Msk;
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00001e 6ac1 LDR r1,[r0,#0x2c]
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000020 4391 BICS r1,r1,r2
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000022 62c1 STR r1,[r0,#0x2c]
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|L3.36|
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;;;173
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;;;174 return;
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;;;175 }
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000024 4770 BX lr
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;;;176
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ENDP
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000026 0000 DCW 0x0000
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|L3.40|
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DCD 0x400e0000
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AREA ||i.ADC_EnableHWTrigger||, CODE, READONLY, ALIGN=2
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ADC_EnableHWTrigger PROC
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;;;79 */
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;;;80 void ADC_EnableHWTrigger(ADC_T *adc,
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000000 b530 PUSH {r4,r5,lr}
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;;;81 uint32_t u32Source,
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;;;82 uint32_t u32Param)
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;;;83 {
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;;;84 ADC->CTL &= ~(ADC_TRIGGER_BY_PWM | ADC_RISING_EDGE_TRIGGER | ADC_CTL_HWTRGEN_Msk);
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000002 480d LDR r0,|L4.56|
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000004 6a03 LDR r3,[r0,#0x20]
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000006 24ff MOVS r4,#0xff
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000008 3471 ADDS r4,r4,#0x71
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00000a 43a3 BICS r3,r3,r4
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00000c 6203 STR r3,[r0,#0x20]
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;;;85 if(u32Source == ADC_TRIGGER_BY_EXT_PIN) {
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;;;86 ADC->CTL |= u32Source | u32Param | ADC_CTL_HWTRGEN_Msk;
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00000e 1583 ASRS r3,r0,#22
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000010 2900 CMP r1,#0 ;85
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000012 d00b BEQ |L4.44|
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;;;87 } else {
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;;;88 ADC->TRGDLY = (ADC->TRGDLY & ~ADC_TRGDLY_DELAY_Msk) | u32Param;
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000014 4c08 LDR r4,|L4.56|
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000016 3440 ADDS r4,r4,#0x40
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000018 6865 LDR r5,[r4,#4]
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00001a 0a2d LSRS r5,r5,#8
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00001c 022d LSLS r5,r5,#8
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00001e 4315 ORRS r5,r5,r2
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000020 6065 STR r5,[r4,#4]
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;;;89 ADC->CTL |= u32Source | ADC_CTL_HWTRGEN_Msk;
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000022 6a02 LDR r2,[r0,#0x20]
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000024 4319 ORRS r1,r1,r3
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000026 430a ORRS r2,r2,r1
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000028 6202 STR r2,[r0,#0x20]
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;;;90 }
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;;;91 return;
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;;;92 }
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00002a bd30 POP {r4,r5,pc}
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|L4.44|
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00002c 6a01 LDR r1,[r0,#0x20] ;86
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00002e 431a ORRS r2,r2,r3 ;86
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000030 4311 ORRS r1,r1,r2 ;86
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000032 6201 STR r1,[r0,#0x20] ;86
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000034 bd30 POP {r4,r5,pc}
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;;;93
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ENDP
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000036 0000 DCW 0x0000
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|L4.56|
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DCD 0x400e0000
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AREA ||i.ADC_EnableInt||, CODE, READONLY, ALIGN=2
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ADC_EnableInt PROC
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;;;141 */
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;;;142 void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask)
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000000 07cb LSLS r3,r1,#31
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;;;143 {
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;;;144 if(u32Mask & ADC_ADIF_INT)
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;;;145 ADC->CTL |= ADC_CTL_ADCIEN_Msk;
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000002 4809 LDR r0,|L5.40|
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000004 2202 MOVS r2,#2
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000006 2b00 CMP r3,#0 ;144
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000008 d002 BEQ |L5.16|
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00000a 6a03 LDR r3,[r0,#0x20]
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00000c 4313 ORRS r3,r3,r2
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00000e 6203 STR r3,[r0,#0x20]
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|L5.16|
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;;;146 if(u32Mask & ADC_CMP0_INT)
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000010 078b LSLS r3,r1,#30
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000012 d502 BPL |L5.26|
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;;;147 ADC->CMP0 |= ADC_CMP0_ADCMPIE_Msk;
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000014 6a83 LDR r3,[r0,#0x28]
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000016 4313 ORRS r3,r3,r2
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000018 6283 STR r3,[r0,#0x28]
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|L5.26|
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;;;148 if(u32Mask & ADC_CMP1_INT)
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00001a 0749 LSLS r1,r1,#29
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00001c d502 BPL |L5.36|
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;;;149 ADC->CMP1 |= ADC_CMP1_ADCMPIE_Msk;
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00001e 6ac1 LDR r1,[r0,#0x2c]
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000020 4311 ORRS r1,r1,r2
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000022 62c1 STR r1,[r0,#0x2c]
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|L5.36|
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;;;150
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;;;151 return;
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;;;152 }
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000024 4770 BX lr
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;;;153
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ENDP
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000026 0000 DCW 0x0000
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|L5.40|
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DCD 0x400e0000
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AREA ||i.ADC_Open||, CODE, READONLY, ALIGN=2
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ADC_Open PROC
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;;;36 */
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;;;37 void ADC_Open(ADC_T *adc,
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000000 4803 LDR r0,|L6.16|
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;;;38 uint32_t u32InputMode,
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;;;39 uint32_t u32OpMode,
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;;;40 uint32_t u32ChMask)
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;;;41 {
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;;;42 ADC->CHEN = (ADC->CHEN & ~(ADC_CHEN_CHEN0_Msk |
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000002 6a41 LDR r1,[r0,#0x24]
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000004 0a09 LSRS r1,r1,#8
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000006 0209 LSLS r1,r1,#8
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000008 4319 ORRS r1,r1,r3
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00000a 6241 STR r1,[r0,#0x24]
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;;;43 ADC_CHEN_CHEN1_Msk |
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;;;44 ADC_CHEN_CHEN2_Msk |
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;;;45 ADC_CHEN_CHEN3_Msk |
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;;;46 ADC_CHEN_CHEN4_Msk |
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;;;47 ADC_CHEN_CHEN5_Msk |
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;;;48 ADC_CHEN_CHEN6_Msk |
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;;;49 ADC_CHEN_CHEN7_Msk)) | u32ChMask;
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;;;50 return;
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;;;51 }
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00000c 4770 BX lr
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;;;52
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ENDP
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00000e 0000 DCW 0x0000
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|L6.16|
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DCD 0x400e0000
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AREA ||i.ADC_SeqModeEnable||, CODE, READONLY, ALIGN=2
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ADC_SeqModeEnable PROC
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;;;188 */
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;;;189 void ADC_SeqModeEnable(ADC_T *adc, uint32_t u32SeqTYPE, uint32_t u32ModeSel)
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000000 b510 PUSH {r4,lr}
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;;;190 {
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;;;191 // Enable ADC Sequential Mode
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;;;192 ADC->SEQCTL = ADC->SEQCTL | ADC_SEQCTL_SEQEN_Msk;
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000002 4809 LDR r0,|L7.40|
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000004 68c3 LDR r3,[r0,#0xc]
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000006 2401 MOVS r4,#1
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000008 4323 ORRS r3,r3,r4
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00000a 60c3 STR r3,[r0,#0xc]
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;;;193
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;;;194 // Select ADC Sequential Mode Type
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;;;195 ADC->SEQCTL = (ADC->SEQCTL & ~(ADC_SEQCTL_SEQTYPE_Msk)) | (u32SeqTYPE << ADC_SEQCTL_SEQTYPE_Pos);
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00000c 68c3 LDR r3,[r0,#0xc]
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00000e 2402 MOVS r4,#2
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000010 43a3 BICS r3,r3,r4
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000012 0049 LSLS r1,r1,#1
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000014 430b ORRS r3,r3,r1
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000016 60c3 STR r3,[r0,#0xc]
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;;;196
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;;;197 // Select ADC Sequential Mode Type
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;;;198 ADC->SEQCTL = (ADC->SEQCTL & ~(ADC_SEQCTL_MODESEL_Msk)) | (u32ModeSel << ADC_SEQCTL_MODESEL_Pos);
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000018 68c1 LDR r1,[r0,#0xc]
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00001a 230c MOVS r3,#0xc
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00001c 4399 BICS r1,r1,r3
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00001e 0092 LSLS r2,r2,#2
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000020 4311 ORRS r1,r1,r2
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000022 60c1 STR r1,[r0,#0xc]
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;;;199
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;;;200 return;
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;;;201 }
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000024 bd10 POP {r4,pc}
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;;;202
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ENDP
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000026 0000 DCW 0x0000
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|L7.40|
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DCD 0x400e0040
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AREA ||i.ADC_SeqModeTriggerSrc||, CODE, READONLY, ALIGN=2
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ADC_SeqModeTriggerSrc PROC
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;;;211 */
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;;;212 void ADC_SeqModeTriggerSrc(ADC_T *adc, uint32_t u32SeqModeTriSrc1, uint32_t u32SeqModeTriSrc2)
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000000 b510 PUSH {r4,lr}
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;;;213 {
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;;;214 // Select PWM Trigger Source Selection for TRG1CTL or TRG2CTL
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;;;215 ADC->SEQCTL = (ADC->SEQCTL & ~(ADC_SEQCTL_TRG1CTL_Msk)) | (u32SeqModeTriSrc1 << ADC_SEQCTL_TRG1CTL_Pos);
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000002 4807 LDR r0,|L8.32|
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000004 68c3 LDR r3,[r0,#0xc]
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000006 240f MOVS r4,#0xf
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000008 0224 LSLS r4,r4,#8
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00000a 43a3 BICS r3,r3,r4
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00000c 0209 LSLS r1,r1,#8
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00000e 430b ORRS r3,r3,r1
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000010 60c3 STR r3,[r0,#0xc]
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;;;216 ADC->SEQCTL = (ADC->SEQCTL & ~(ADC_SEQCTL_TRG2CTL_Msk)) | (u32SeqModeTriSrc2 << ADC_SEQCTL_TRG2CTL_Pos);
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000012 68c1 LDR r1,[r0,#0xc]
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000014 0223 LSLS r3,r4,#8
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000016 4399 BICS r1,r1,r3
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000018 0412 LSLS r2,r2,#16
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00001a 4311 ORRS r1,r1,r2
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00001c 60c1 STR r1,[r0,#0xc]
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;;;217 return;
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;;;218 }
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00001e bd10 POP {r4,pc}
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;;;219
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ENDP
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|L8.32|
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DCD 0x400e0040
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AREA ||i.ADC_SetExtraSampleTime||, CODE, READONLY, ALIGN=2
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ADC_SetExtraSampleTime PROC
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;;;123 */
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;;;124 void ADC_SetExtraSampleTime(ADC_T *adc,
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000000 4803 LDR r0,|L9.16|
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;;;125 uint32_t u32ChNum,
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;;;126 uint32_t u32SampleTime)
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;;;127 {
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;;;128 ADC->EXTSMPT = (ADC->EXTSMPT & ~ADC_EXTSMPT_EXTSMPT_Msk) | u32SampleTime;
|
||
|
|
000002 6881 LDR r1,[r0,#8]
|
||
|
|
000004 0909 LSRS r1,r1,#4
|
||
|
|
000006 0109 LSLS r1,r1,#4
|
||
|
|
000008 4311 ORRS r1,r1,r2
|
||
|
|
00000a 6081 STR r1,[r0,#8]
|
||
|
|
;;;129 }
|
||
|
|
00000c 4770 BX lr
|
||
|
|
;;;130
|
||
|
|
ENDP
|
||
|
|
|
||
|
|
00000e 0000 DCW 0x0000
|
||
|
|
|L9.16|
|
||
|
|
DCD 0x400e0040
|
||
|
|
|
||
|
|
;*** Start embedded assembler ***
|
||
|
|
|
||
|
|
#line 1 "..\\..\\..\\Library\\StdDriver\\src\\adc.c"
|
||
|
|
AREA ||.rev16_text||, CODE
|
||
|
|
THUMB
|
||
|
|
EXPORT |__asm___5_adc_c_ADC_Open____REV16|
|
||
|
|
#line 388 "..\\..\\..\\Library\\CMSIS\\Include\\cmsis_armcc.h"
|
||
|
|
|__asm___5_adc_c_ADC_Open____REV16| PROC
|
||
|
|
#line 389
|
||
|
|
|
||
|
|
rev16 r0, r0
|
||
|
|
bx lr
|
||
|
|
ENDP
|
||
|
|
AREA ||.revsh_text||, CODE
|
||
|
|
THUMB
|
||
|
|
EXPORT |__asm___5_adc_c_ADC_Open____REVSH|
|
||
|
|
#line 402
|
||
|
|
|__asm___5_adc_c_ADC_Open____REVSH| PROC
|
||
|
|
#line 403
|
||
|
|
|
||
|
|
revsh r0, r0
|
||
|
|
bx lr
|
||
|
|
ENDP
|
||
|
|
|
||
|
|
;*** End embedded assembler ***
|