283 lines
12 KiB
C
283 lines
12 KiB
C
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/**************************************************************************//**
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* @file pwm.h
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* @version V1.00
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* $Revision: 6 $
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* $Date: 15/06/05 1:41p $
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* @brief Mini58 series PWM driver header file
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*
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* @note
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* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __PWM_H__
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#define __PWM_H__
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
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@{
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*/
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/** @addtogroup Mini58_PWM_Driver PWM Driver
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@{
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*/
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/** @addtogroup Mini58_PWM_EXPORTED_CONSTANTS PWM Exported Constants
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@{
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*/
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#define PWM_CHANNEL_NUM (6) /*!< PWM channel number */
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#define PWM_CLK_DIV_1 (4UL) /*!< PWM clock divide by 1 */
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#define PWM_CLK_DIV_2 (0UL) /*!< PWM clock divide by 2 */
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#define PWM_CLK_DIV_4 (1UL) /*!< PWM clock divide by 4 */
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#define PWM_CLK_DIV_8 (2UL) /*!< PWM clock divide by 8 */
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#define PWM_CLK_DIV_16 (3UL) /*!< PWM clock divide by 16 */
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#define PWM_EDGE_ALIGNED (0UL) /*!< PWM working in edge aligned type */
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#define PWM_CENTER_ALIGNED (PWM_CTL_CNTTYPE_Msk) /*!< PWM working in center aligned type */
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#define PWM_TRIGGER_ADC_CNTR_IS_0 PWM_ADCTCTL0_ZPTRGEN0_Msk /*!< PWM trigger ADC while counter matches 0 */
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#define PWM_TRIGGER_ADC_CNTR_IS_CMR_D PWM_ADCTCTL0_CDTRGEN0_Msk /*!< PWM trigger ADC while counter matches CMR during down count */
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#define PWM_TRIGGER_ADC_CNTR_IS_CNR PWM_ADCTCTL0_CPTRGEN0_Msk /*!< PWM trigger ADC while counter matches CNR */
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#define PWM_TRIGGER_ADC_CNTR_IS_CMR_U PWM_ADCTCTL0_CUTRGEN0_Msk /*!< PWM trigger ADC while counter matches CMR during up count */
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#define PWM_FB0_EINT0 (PWM_BRKCTL_BRK0EN_Msk) /*!< External interrupt 0 as fault brake 0 source */
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#define PWM_FB0_ACMP1 (PWM_BRKCTL_BRK0EN_Msk | PWM_BRKCTL_BRK1SEL_Msk) /*!< Comparator 1 as fault brake 0 source */
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#define PWM_FB1_EINT1 (PWM_BRKCTL_BRK1EN_Msk) /*!< External interrupt 1 as fault brake 1 source */
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#define PWM_FB1_ACMP0 (PWM_BRKCTL_BRK1EN_Msk | PWM_BRKCTL_BRK0SEL_Msk) /*!< Comparator 0 as fault brake 1 source */
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#define PWM_PERIOD_INT_UNDERFLOW (0) /*!< PWM period interrupt trigger if counter underflow */
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#define PWM_PERIOD_INT_MATCH_CNR (PWM_INTEN_PINTTYPE_Msk) /*!< PWM period interrupt trigger if counter match CNR */
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/*---------------------------------------------------------------------------------------------------------*/
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/* PWM Group channel number constants definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define PWM_CH0 0x0 /*!< PWM channel 0 */
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#define PWM_CH1 0x1 /*!< PWM channel 1 */
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#define PWM_CH2 0x2 /*!< PWM channel 2 */
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#define PWM_CH3 0x3 /*!< PWM channel 3 */
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#define PWM_CH4 0x4 /*!< PWM channel 4 */
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#define PWM_CH5 0x5 /*!< PWM channel 5 */
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/*@}*/ /* end of group Mini58_PWM_EXPORTED_CONSTANTS */
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/** @addtogroup Mini58_PWM_EXPORTED_FUNCTIONS PWM Exported Functions
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@{
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*/
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/**
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* @brief This macro enable complementary mode
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* @param[in] pwm The base address of PWM module
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* @return None
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* \hideinitializer
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*/
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#define PWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL = (PWM->CTL & ~PWM_CTL_MODE_Msk) |(1UL << PWM_CTL_MODE_Pos))
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/**
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* @brief This macro disable complementary mode, and enable independent mode.
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* @param[in] pwm The base address of PWM module
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* @return None
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* \hideinitializer
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*/
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#define PWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_MODE_Msk)
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/**
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* @brief This macro enable group mode
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* @param[in] pwm The base address of PWM module
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* @return None
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* \hideinitializer
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*/
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#define PWM_ENABLE_GROUP_MODE(pwm) ((pwm)->CTL |= PWM_CTL_GROUPEN_Msk)
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/**
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* @brief This macro disable group mode
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* @param[in] pwm The base address of PWM module
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* @return None
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* \hideinitializer
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*/
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#define PWM_DISABLE_GROUP_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_GROUPEN_Msk)
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/**
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* @brief This macro enable synchronous mode
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* @param[in] pwm The base address of PWM module
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* @return None
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* \hideinitializer
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*/
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#define PWM_ENABLE_SYNC_MODE(pwm) (PWM->CTL = ((pwm)->CTL & ~PWM_CTL_MODE_Msk) |(2UL << PWM_CTL_MODE_Pos))
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/**
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* @brief This macro disable synchronous mode, and enable independent mode.
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* @param[in] pwm The base address of PWM module
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* @return None
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* \hideinitializer
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*/
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#define PWM_DISABLE_SYNC_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_MODE_Msk)
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/**
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* @brief This macro enable output inverter of specified channel(s)
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
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* Bit 0 represents channel 0, bit 1 represents channel 1...
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* @return None
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* \hideinitializer
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*/
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#define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) \
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do{ \
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int i;\
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(pwm)->CTL &= ~(PWM_CTL_PINV0_Msk|PWM_CTL_PINV1_Msk|PWM_CTL_PINV2_Msk|PWM_CTL_PINV3_Msk|PWM_CTL_PINV4_Msk|PWM_CTL_PINV5_Msk);\
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for(i = 0; i < 6; i++) { \
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if((u32ChannelMask) & (1 << i)) \
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(pwm)->CTL |= (1 << (PWM_CTL_PINV0_Pos + (i * 4))); \
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} \
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}while(0)
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/**
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* @brief This macro set the prescaler of the selected channel
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFF
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* @return None
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* @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed,
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* channel 1 will also be affected.
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* \hideinitializer
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*/
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#define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) \
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((pwm)->CLKPSC = ((pwm)->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))
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/**
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* @brief This macro set the divider of the selected channel
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32Divider Clock divider of specified channel. Valid values are
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* - \ref PWM_CLK_DIV_1
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* - \ref PWM_CLK_DIV_2
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* - \ref PWM_CLK_DIV_4
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* - \ref PWM_CLK_DIV_8
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* - \ref PWM_CLK_DIV_16
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* @return None
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* \hideinitializer
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*/
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#define PWM_SET_DIVIDER(pwm, u32ChannelNum, u32Divider) \
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((pwm)->CLKDIV = ((pwm)->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << ((u32ChannelNum) * 4))) | ((u32Divider) << ((u32ChannelNum) * 4)))
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/**
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* @brief This macro set the duty of the selected channel
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF
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* @return None
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* @note This new setting will take effect on next PWM period
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* \hideinitializer
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*/
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#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) (*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + u32ChannelNum * 4)))= (u32CMR))
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/**
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* @brief This macro set the period of the selected channel
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
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* @return None
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* @note This new setting will take effect on next PWM period
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* @note PWM counter will stop if period length set to 0
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* \hideinitializer
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*/
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#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->PERIOD0)) + (u32ChannelNum) * 4))) = (u32CNR))
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/**
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* @brief This macro set the duty of the selected channel for PWM asymmetric Mode
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32CMRD Down counter in Asymmetric Mode. Valid values are between 0~0xFFFF
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* @return None
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* @note This new setting will take effect on next PWM period
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* \hideinitializer
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*/
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#define PWM_SET_CMRD(pwm, u32ChannelNum, u32CMRD) (*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + (u32ChannelNum) * 4)))= (u32CMRD << 16))
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/**
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* @brief This macro set the PWM aligned type
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelMask This parameter is not used
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* @param[in] u32AlignedType PWM aligned type, valid values are:
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* - \ref PWM_EDGE_ALIGNED
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* - \ref PWM_CENTER_ALIGNED
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* @return None
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* \hideinitializer
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*/
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#define PWM_SET_ALIGNED_TYPE(pwm, u32ChannelMask, u32AlignedType) \
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((pwm)->CTL = ((pwm)->CTL & ~PWM_CTL_CNTTYPE_Msk) | (u32AlignedType))
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/**
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* @brief This macro enables PWM asymmetric mode
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* @param[in] pwm The base address of PWM module
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* @return None
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* \hideinitializer
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*/
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#define PWM_ENABLE_ASYMMETRIC_MODE(pwm) ((pwm)->CTL |= PWM_CTL_ASYMEN_Msk)
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/**
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* @brief This macro enables PWM Precise Center-Aligned Type
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* @param[in] pwm The base address of PWM module
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* @return None
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* \hideinitializer
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*/
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#define PWM_ENABLE_PCAEN(pwm) (PWM->PCACTL |= PWM_PCACTL_PCAEN_Msk)
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uint32_t PWM_ConfigOutputChannel(PWM_T *pwm,
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uint32_t u32ChannelNum,
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uint32_t u32Frequency,
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uint32_t u32DutyCycle);
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void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask);
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void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask);
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void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask);
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void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
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void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
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uint32_t PWM_GetADCTriggerFlag (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
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void PWM_EnableFaultBrake(PWM_T *pwm,
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uint32_t u32ChannelMask,
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uint32_t u32LevelMask,
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uint32_t u32BrakeSource);
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void PWM_ClearFaultBrakeFlag(PWM_T *pwm, uint32_t u32BrakeSource);
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void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
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void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
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void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration);
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void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
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void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
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uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
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void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
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void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
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uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
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void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
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uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_EnableCenterInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
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void PWM_DisableCenterInt(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_ClearCenterIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
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uint32_t PWM_GetCenterIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_EnableRiseInt(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_DisableRiseInt(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_ClearRiseIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
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uint32_t PWM_GetRiseIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
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/*@}*/ /* end of group Mini58_PWM_EXPORTED_FUNCTIONS */
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/*@}*/ /* end of group Mini58_PWM_Driver */
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/*@}*/ /* end of group Mini58_Device_Driver */
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#ifdef __cplusplus
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}
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#endif
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#endif //__PWM_H__
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/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
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