193 lines
9.0 KiB
C
193 lines
9.0 KiB
C
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/****************************************************************************************************//**
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* @file ARM_Example.h
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*
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* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File for
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* ARM_Example from ARM Ltd..
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*
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* @version V1.2
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* @date 16. April 2014
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*
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* @note Generated with SVDConv V2.81e
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* from CMSIS SVD File 'ARM_Example.svd' Version 1.2,
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*
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* @par ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontroller, but can be equally used for other
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* suitable processor architectures. This file can be freely distributed.
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* Modifications to this file shall be clearly marked.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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*******************************************************************************************************/
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/** @addtogroup ARM Ltd.
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* @{
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*/
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/** @addtogroup ARM_Example
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* @{
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*/
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#ifndef ARM_EXAMPLE_H
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#define ARM_EXAMPLE_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ------------------------- Interrupt Number Definition ------------------------ */
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typedef enum {
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/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
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Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
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NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
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HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
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MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
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and No Match */
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BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
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related Fault */
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UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
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SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
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DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
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PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
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SysTick_IRQn = -1, /*!< 15 System Tick Timer */
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/* ------------------- ARM_Example Specific Interrupt Numbers ------------------- */
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TIMER0_IRQn = 0, /*!< 0 TIMER0 */
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TIMER1_IRQn = 4, /*!< 4 TIMER1 */
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TIMER2_IRQn = 6 /*!< 6 TIMER2 */
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} IRQn_Type;
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/** @addtogroup Configuration_of_CMSIS
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* @{
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*/
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/* ================================================================================ */
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/* ================ Processor and Core Peripheral Section ================ */
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/* ================================================================================ */
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/* ----------------Configuration of the Cortex-M3 Processor and Core Peripherals---------------- */
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#define __CM3_REV 0x0100 /*!< Cortex-M3 Core Revision */
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#define __MPU_PRESENT 1 /*!< MPU present or not */
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#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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/** @} */ /* End of group Configuration_of_CMSIS */
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#include "core_cm3.h" /*!< Cortex-M3 processor and core peripherals */
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#include "system_ARMCM3.h" /*!< ARM_Example System */
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/* ================================================================================ */
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/* ================ Device Specific Peripheral Section ================ */
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/* ================================================================================ */
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/** @addtogroup Device_Peripheral_Registers
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* @{
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*/
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/* ------------------- Start of section using anonymous unions ------------------ */
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#if defined(__CC_ARM)
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#pragma push
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#pragma anon_unions
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#elif defined(__ICCARM__)
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#pragma language=extended
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#elif defined(__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined(__TMS470__)
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/* anonymous unions are enabled by default */
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#elif defined(__TASKING__)
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#pragma warning 586
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#else
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#warning Not supported compiler type
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#endif
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/* ================================================================================ */
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/* ================ TIMER0 ================ */
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/* ================================================================================ */
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/**
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* @brief 32 Timer / Counter, counting up or down from different sources (TIMER0)
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*/
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typedef struct { /*!< TIMER0 Structure */
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__IO uint32_t CR; /*!< Control Register */
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__IO uint16_t SR; /*!< Status Register */
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__I uint16_t RESERVED0[5];
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__IO uint16_t INT; /*!< Interrupt Register */
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__I uint16_t RESERVED1[7];
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__IO uint32_t COUNT; /*!< The Counter Register reflects the actual Value of the Timer/Counter */
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__IO uint32_t MATCH; /*!< The Match Register stores the compare Value for the MATCH condition */
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union {
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__O uint32_t PRESCALE_WR; /*!< The Prescale Register stores the Value for the prescaler. The
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cont event gets divided by this value */
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__I uint32_t PRESCALE_RD; /*!< The Prescale Register stores the Value for the prescaler. The
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cont event gets divided by this value */
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};
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__I uint32_t RESERVED2[9];
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__IO uint32_t RELOAD[4]; /*!< The Reload Register stores the Value the COUNT Register gets
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reloaded on a when a condition was met. */
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} TIMER0_Type;
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/* -------------------- End of section using anonymous unions ------------------- */
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#if defined(__CC_ARM)
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#pragma pop
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#elif defined(__ICCARM__)
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/* leave anonymous unions enabled */
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#elif defined(__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined(__TMS470__)
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/* anonymous unions are enabled by default */
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#elif defined(__TASKING__)
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#pragma warning restore
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#else
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#warning Not supported compiler type
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#endif
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/* ================================================================================ */
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/* ================ Peripheral memory map ================ */
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/* ================================================================================ */
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#define TIMER0_BASE 0x40010000UL
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#define TIMER1_BASE 0x40010100UL
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#define TIMER2_BASE 0x40010200UL
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/* ================================================================================ */
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/* ================ Peripheral declaration ================ */
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/* ================================================================================ */
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#define TIMER0 ((TIMER0_Type *) TIMER0_BASE)
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#define TIMER1 ((TIMER0_Type *) TIMER1_BASE)
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#define TIMER2 ((TIMER0_Type *) TIMER2_BASE)
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/** @} */ /* End of group Device_Peripheral_Registers */
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/** @} */ /* End of group ARM_Example */
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/** @} */ /* End of group ARM Ltd. */
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#ifdef __cplusplus
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}
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#endif
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#endif /* ARM_Example_H */
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