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ChipTest/PAN159/PAN159-Template/Library/StdDriver/driver/lib_driver_xn297l.h

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添加PAN159资料
2021-09-26 09:18:47 +00:00
/*******************************************************************************
* @note Copyright (C) 2017 Shanghai Panchip Microelectronics Co., Ltd.
* All rights reserved.
*
* @file drv_xn297l.h
* @brief XN297L RF<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*
* @history - V1.0, 2017-03-06, xiaoguolin, first implementation.
*******************************************************************************/
#ifndef __DRV_XN297L_H
#define __DRV_XN297L_H
#ifdef __cplusplus
extern "C"{
#endif
#include "lib_driver_delay_pan159.h"
#include "lib_driver_rfspi_pan159.h"
#define XN297L_RF_DATA_RATE_1M 0x00
#define XN297L_RF_DATA_RATE_2M 0x40
#define XN297L_RF_DATA_RATE_250K 0xC0
#define USER_RF_POWER (CONF_RF_REMOTE_POWER|CONF_RF_REMOTE_RATE)
//#define MONITOR_RF_POWER (CONF_RF_CONGLEX_POWER|CONF_RF_DONGLEX_RATE)
#define TRANS_ENHANCE_MODE 1 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǿģʽ
#define TRANS_NORMAL_MODE 2 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨģʽ
#define TRANSMIT_TYPE TRANS_NORMAL_MODE //<2F><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>ͨģʽ
#define RX_DR_FLAG 0x40 // <20><><EFBFBD><EFBFBD><EFBFBD>жϱ<D0B6>־λ
#define TX_DS_FLAG 0x20 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϱ<D0B6>־λ
#define RX_TX_FLAG 0x60 // <20><><EFBFBD>ͽ<EFBFBD><CDBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϱ<D0B6>־λ<D6BE><CEBB>ack_payload ģʽ<C4A3><CABD>ʹ<EFBFBD><CAB9>
#define MAX_RT_FLAG 0x10 // <20><><EFBFBD><EFBFBD><EFBFBD>ش<EFBFBD><D8B4><EFBFBD>ʱ<EFBFBD>жϱ<D0B6>־λ
#define XN297L_RF_POWER_P_11 0x27 /** 11dBm */
#define XN297L_RF_POWER_P_10 0x26 /** 10dBm */
#define XN297L_RF_POWER_P_9 0x15 /** 9dBm */
#define XN297L_RF_POWER_P_5 0x2c /** 5dBm */
#define XN297L_RF_POWER_P_4 0x14 /** 4dBm */
#define XN297L_RF_POWER_N_1 0x2A /** -1dBm */
#define XN297L_RF_POWER_N_9 0x29 /** -9dBm */
#define XN297L_RF_POWER_N_10 0x19 /** -10dBm */
#define XN297L_RF_POWER_N_23 0x30 /** -23dBm */
#if( (DATA_RATE ==DR_1M) || (DATA_RATE==DR_2M) )
#define rf7dBm 0X0D // 7dBm ֻ<><D6BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1M<31><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define rf6dBm 0X06 // 6dBm ֻ<><D6BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1M<31><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define rf3dBm 0X0C // 3dBm ֻ<><D6BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1M<31><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#endif
//////////////////////////////////////////////////////////////////////////////////////////////////////////
//XN297L<37>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define RF_READ_REG 0x00 //<2F><><EFBFBD><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD>,<2C><>5λΪ<CEBB>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ
#define RF_WRITE_REG 0x20 //д<><D0B4><EFBFBD>üĴ<C3BC><C4B4><EFBFBD>,<2C><>5λΪ<CEBB>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ
#define W_REGISTER 0x20 //д<><D0B4><EFBFBD>üĴ<C3BC><C4B4><EFBFBD>,<2C><>5λΪ<CEBB>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ
#define R_RX_PAYLOAD 0x61 //<2F><>RX<52><58>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD>, 1~32<33>ֽ<EFBFBD>
#define W_TX_PAYLOAD 0xA0 //дTX<54><58>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD>,1~32<33>ֽ<EFBFBD>
#define FLUSH_TX 0xE1 //<2F><><EFBFBD><EFBFBD>TX FIFO<46>Ĵ<EFBFBD><C4B4><EFBFBD>.<2E><><EFBFBD><EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD>
#define FLUSH_RX 0xE2 //<2F><><EFBFBD><EFBFBD>RX FIFO<46>Ĵ<EFBFBD><C4B4><EFBFBD>.<2E><><EFBFBD><EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD>
#define REUSE_TX_PL 0xE3 //<2F><><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,CEΪ<45><CEAA>,<2C><><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϸ<EFBFBD><CFB7><EFBFBD>.
#define NOP 0xFF //<2F>ղ<EFBFBD><D5B2><EFBFBD>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD>
#define ACTIVATE 0x50 //ACTIVATE
#define DEACTIVATE 0x50 //DEACTIVATE
#define R_RX_PL_WID 0x60 //Read width of RX data
#define W_ACK_PAYLOAD 0xA8 //Data with ACK
#define W_TX_PAYLOAD_NOACK 0xB0 //TX Payload no ACK Request
#define CE_FSPI_ON 0xFD // CE HIGH
#define CE_FSPI_OFF 0xFC // CE LOW
#define RST_FSPI 0x53 // RESET
//SPI(XN297L)<29>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ
#define CONFIG 0x00 //<2F><><EFBFBD>üĴ<C3BC><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ;bit0:1<><31><EFBFBD><EFBFBD>ģʽ,0<><30><EFBFBD><EFBFBD>ģʽ;bit1:<3A><>ѡ<EFBFBD><D1A1>;bit2:CRCģʽ;bit3:CRCʹ<43><CAB9>;
//bit4:<3A>ж<EFBFBD>MAX_RT(<28>ﵽ<EFBFBD><EFB5BD><EFBFBD><EFBFBD><EFBFBD>ط<EFBFBD><D8B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>)ʹ<><CAB9>;bit5:<3A>ж<EFBFBD>TX_DSʹ<53><CAB9>;bit6:<3A>ж<EFBFBD>RX_DRʹ<52><CAB9>
#define EN_AA 0x01 //ʹ<><CAB9><EFBFBD>Զ<EFBFBD>Ӧ<EFBFBD><D3A6><EFBFBD><EFBFBD><EFBFBD><EFBFBD> bit0~5,<2C><>Ӧͨ<D3A6><CDA8>0~5
#define EN_RXADDR 0x02 //<2F><><EFBFBD>յ<EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>,bit0~5,<2C><>Ӧͨ<D3A6><CDA8>0~5
#define SETUP_AW 0x03 //<2F><><EFBFBD>õ<EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>):bit1,0:00,3<>ֽ<EFBFBD>;01,4<>ֽ<EFBFBD>;02,5<>ֽ<EFBFBD>;
#define SETUP_RETR 0x04 //<2F><><EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD><D4B6>ط<EFBFBD>;bit3:0,<2C>Զ<EFBFBD><D4B6>ط<EFBFBD><D8B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>;bit7:4,<2C>Զ<EFBFBD><D4B6>ط<EFBFBD><D8B7><EFBFBD>ʱ 250*x+86us
#define RF_CH 0x05 //rfͨ<66><CDA8>,bit6:0,<2C><><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>Ƶ<EFBFBD><C6B5>;
#define RF_SETUP 0x06 //rf<72>Ĵ<EFBFBD><C4B4><EFBFBD>;bit3:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(0:1Mbps,1:2Mbps);bit2:1,<2C><><EFBFBD>书<EFBFBD><E4B9A6>;bit0:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ŵ<EFBFBD><C5B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define RF_STATUS 0x07 //״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD>;bit0:TX FIFO<46><4F><EFBFBD><EFBFBD>־;bit3:1,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD>(<28><><EFBFBD><EFBFBD>:6);bit4,<2C>ﵽ<EFBFBD><EFB5BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ط<EFBFBD>
//bit5:<3A><><EFBFBD>ݷ<EFBFBD><DDB7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>;bit6:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>;
#define MAX_TX 0x10 //<2F>ﵽ<EFBFBD><EFB5BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CDB4><EFBFBD><EFBFBD>ж<EFBFBD>
#define TX_OK 0x20 //TX<54><58><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
#define RX_OK 0x40 //<2F><><EFBFBD>յ<EFBFBD><D5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
#define OBSERVE_TX 0x08 //<2F><><EFBFBD><EFBFBD>״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD>,bit7:4,<2C><><EFBFBD>ݰ<EFBFBD><DDB0><EFBFBD>ʧ<EFBFBD><CAA7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>;bit3:0,<2C>ط<EFBFBD><D8B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define CD 0x09 //<2F>ز<EFBFBD><D8B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>,bit0,<2C>ز<EFBFBD><D8B2><EFBFBD><EFBFBD><EFBFBD>;
#define RX_ADDR_P0 0x0A //<2F><><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>0<EFBFBD><30><EFBFBD>յ<EFBFBD>ַ,<2C><><EFBFBD>󳤶<EFBFBD>5<EFBFBD><35><EFBFBD>ֽ<EFBFBD>,<2C><><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD>ǰ
#define RX_ADDR_P1 0x0B //<2F><><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>1<EFBFBD><31><EFBFBD>յ<EFBFBD>ַ,<2C><><EFBFBD>󳤶<EFBFBD>5<EFBFBD><35><EFBFBD>ֽ<EFBFBD>,<2C><><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD>ǰ
#define RX_ADDR_P2 0x0C //<2F><><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>2<EFBFBD><32><EFBFBD>յ<EFBFBD>ַ,<2C><><EFBFBD><EFBFBD><EFBFBD>ֽڿ<D6BD><DABF><EFBFBD><EFBFBD><EFBFBD>,<2C><><EFBFBD>ֽ<EFBFBD>,<2C><><EFBFBD><EFBFBD>ͬRX_ADDR_P1[39:8]<5D><><EFBFBD><EFBFBD>;
#define RX_ADDR_P3 0x0D //<2F><><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>3<EFBFBD><33><EFBFBD>յ<EFBFBD>ַ,<2C><><EFBFBD><EFBFBD><EFBFBD>ֽڿ<D6BD><DABF><EFBFBD><EFBFBD><EFBFBD>,<2C><><EFBFBD>ֽ<EFBFBD>,<2C><><EFBFBD><EFBFBD>ͬRX_ADDR_P1[39:8]<5D><><EFBFBD><EFBFBD>;
#define RX_ADDR_P4 0x0E //<2F><><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>4<EFBFBD><34><EFBFBD>յ<EFBFBD>ַ,<2C><><EFBFBD><EFBFBD><EFBFBD>ֽڿ<D6BD><DABF><EFBFBD><EFBFBD><EFBFBD>,<2C><><EFBFBD>ֽ<EFBFBD>,<2C><><EFBFBD><EFBFBD>ͬRX_ADDR_P1[39:8]<5D><><EFBFBD><EFBFBD>;
#define RX_ADDR_P5 0x0F //<2F><><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>5<EFBFBD><35><EFBFBD>յ<EFBFBD>ַ,<2C><><EFBFBD><EFBFBD><EFBFBD>ֽڿ<D6BD><DABF><EFBFBD><EFBFBD><EFBFBD>,<2C><><EFBFBD>ֽ<EFBFBD>,<2C><><EFBFBD><EFBFBD>ͬRX_ADDR_P1[39:8]<5D><><EFBFBD><EFBFBD>;
#define TX_ADDR 0x10 //<2F><><EFBFBD>͵<EFBFBD>ַ(<28><><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD>ǰ),ShockBurstTMģʽ<C4A3><CABD>,RX_ADDR_P0<50><30><EFBFBD>˵<EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>
#define RX_PW_P0 0x11 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>0<EFBFBD><30>Ч<EFBFBD><D0A7><EFBFBD>ݿ<EFBFBD><DDBF><EFBFBD>(1~32<33>ֽ<EFBFBD>),<2C><><EFBFBD><EFBFBD>Ϊ0<CEAA><30><EFBFBD>Ƿ<EFBFBD>
#define RX_PW_P1 0x12 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>1<EFBFBD><31>Ч<EFBFBD><D0A7><EFBFBD>ݿ<EFBFBD><DDBF><EFBFBD>(1~32<33>ֽ<EFBFBD>),<2C><><EFBFBD><EFBFBD>Ϊ0<CEAA><30><EFBFBD>Ƿ<EFBFBD>
#define RX_PW_P2 0x13 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>2<EFBFBD><32>Ч<EFBFBD><D0A7><EFBFBD>ݿ<EFBFBD><DDBF><EFBFBD>(1~32<33>ֽ<EFBFBD>),<2C><><EFBFBD><EFBFBD>Ϊ0<CEAA><30><EFBFBD>Ƿ<EFBFBD>
#define RX_PW_P3 0x14 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>3<EFBFBD><33>Ч<EFBFBD><D0A7><EFBFBD>ݿ<EFBFBD><DDBF><EFBFBD>(1~32<33>ֽ<EFBFBD>),<2C><><EFBFBD><EFBFBD>Ϊ0<CEAA><30><EFBFBD>Ƿ<EFBFBD>
#define RX_PW_P4 0x15 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>4<EFBFBD><34>Ч<EFBFBD><D0A7><EFBFBD>ݿ<EFBFBD><DDBF><EFBFBD>(1~32<33>ֽ<EFBFBD>),<2C><><EFBFBD><EFBFBD>Ϊ0<CEAA><30><EFBFBD>Ƿ<EFBFBD>
#define RX_PW_P5 0x16 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>5<EFBFBD><35>Ч<EFBFBD><D0A7><EFBFBD>ݿ<EFBFBD><DDBF><EFBFBD>(1~32<33>ֽ<EFBFBD>),<2C><><EFBFBD><EFBFBD>Ϊ0<CEAA><30><EFBFBD>Ƿ<EFBFBD>
#define FIFO_STATUS 0x17 //FIFO״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD>;bit0,RX FIFO<46>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD>ձ<EFBFBD>־;bit1,RX FIFO<46><4F><EFBFBD><EFBFBD>־;bit2,3,<2C><><EFBFBD><EFBFBD>
//bit4,TX FIFO<46>ձ<EFBFBD>־;bit5,TX FIFO<46><4F><EFBFBD><EFBFBD>־;bit6,1,ѭ<><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD>ݰ<EFBFBD>.0,<2C><>ѭ<EFBFBD><D1AD>;
#define DEM_CAL 0x19
#define RF_CAL2 0x1A
#define DEM_CAL2 0x1B
#define DYNPD 0x1C
#define FEATURE 0x1D
#define RF_CAL 0x1E
#define BB_CAL 0x1F
#define USER_CHN CONF_RF_REMOTE_CHN //ͨ<><CDA8><EFBFBD>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>
#define MONITOR_CHN CONF_RF_DONGLEX_CHN //<2F><><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>
#define PAYLOAD_WIDTH CONF_RF_REMOTE_RX_PAYLOAD_WIDTH //XN297L<37><4C><EFBFBD>ͽ<EFBFBD><CDBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݿ<EFBFBD><DDBF>ȶ<EFBFBD><C8B6><EFBFBD>
#define MONITOR_WIDTH CONF_RF_DONGLEX_TX_PAYLOAD_WIDTH
//#define TX_ADR_WIDTH 5 //5<>ֽڵĵ<DAB5>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>
//#define RX_ADR_WIDTH 5 //5<>ֽڵĵ<DAB5>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>
//#define TX_PLOAD_WIDTH 32 //32<33>ֽڵ<D6BD><DAB5>û<EFBFBD><C3BB><EFBFBD><EFBFBD>ݿ<EFBFBD><DDBF><EFBFBD>
//#define RX_PLOAD_WIDTH 32 //32<33>ֽڵ<D6BD><DAB5>û<EFBFBD><C3BB><EFBFBD><EFBFBD>ݿ<EFBFBD><DDBF><EFBFBD>
#define CE_SOFTWARE_MODE 1 //CE<43><45><EFBFBD><EFBFBD>ģʽ
#define CE_HARDWARE_MODE 2 //CEӲ<45><D3B2>ģʽ
#define CE_TYPE CE_HARDWARE_MODE //<2F><><EFBFBD><EFBFBD>ΪӲ<CEAA><D3B2>ģʽ
#define IRQ_STATUS rfspi_irq()
#define CSN_HIGH P01=1
#define CSN_LOW P01=0
//#if 0
////PAN163
//#if(CE_TYPE==CE_HARDWARE_MODE)
// #define set_CE() (P02=1)
// #define clear_CE() (P02=0)
//#else
// #define set_CE() (xn297l_write_reg(CE_FSPI_ON, 0))//<2F>ڲ<EFBFBD><DAB2><EFBFBD>λCE
// #define clear_CE() (xn297l_write_reg(CE_FSPI_OFF, 0))//<2F>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD>CE
//#endif
//#endif
////PAN159
//#define set_CE() (xn297l_write_reg(CE_FSPI_ON, 0))//<2F>ڲ<EFBFBD><DAB2><EFBFBD>λCE
//#define clear_CE() (xn297l_write_reg(CE_FSPI_OFF, 0))//<2F>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD>CE
#if(CE_TYPE==CE_HARDWARE_MODE)
#define set_CE() rfspi_ce(1)
#define clear_CE() rfspi_ce(0)
#else
#define set_CE() (xn297l_write_reg(CE_FSPI_ON, 0))//<2F>ڲ<EFBFBD><DAB2><EFBFBD>λCE
#define clear_CE() (xn297l_write_reg(CE_FSPI_OFF, 0))//<2F>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD>CE
#endif
void xn297l_write_reg(uint8_t reg,uint8_t data);//rfд<66>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
uint8_t xn297l_read_reg(uint8_t reg);//rf<72><66><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
void xn297l_write_buf(uint8_t reg,uint8_t *pbuf,uint8_t length);//rfд<66><D0B4><EFBFBD>庯<EFBFBD><E5BAAF>
void xn297l_read_buf(uint8_t reg,uint8_t *pbuf,uint8_t length);//rf<72><66><EFBFBD><EFBFBD><EFBFBD>庯<EFBFBD><E5BAAF>
//void xn297l_init(void);//rf<72><66>ʼ<EFBFBD><CABC>
void xn297l_init(uint8_t* addr,uint8_t addr_len,uint8_t chn,uint8_t payload,uint8_t rate_power);
void xn297l_tx_mode(void);//XN297L<37><4C><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>ģʽ
void xn297l_rx_mode(void);//XN297L<37><4C><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>ģʽ
uint8_t xn297l_get_status(void);//XN297L<37><4C>ȡ״̬<D7B4><CCAC>Ϣ
void xn297l_clear_status(void);//XN297L<37><4C><EFBFBD><EFBFBD>״̬<D7B4><CCAC>Ϣ
void xn297l_clear_fifo(void);//XN297L<37><4C><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
void xn297l_set_channel(uint8_t channel);//XN297L<37><4C><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD>ŵ<EFBFBD>
void xn297l_tx_data(uint8_t *data, uint8_t length);//XN297L<37><4C><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
uint8_t xn297l_rx_data(uint8_t *data,uint8_t length);//rf<72><66><EFBFBD>պ<EFBFBD><D5BA><EFBFBD>
void xn297l_set_addr(uint8_t reg,uint8_t *rf_addr_array,uint8_t addr_len);//rf<72><66><EFBFBD><EFBFBD>ͨ<EFBFBD>ŵ<EFBFBD>ַ
void rf_init(void);
#ifdef __cplusplus
}
#endif
#endif // __DRV_XN297L_H
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