412 lines
16 KiB
Plaintext
412 lines
16 KiB
Plaintext
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; generated by Component: ARM Compiler 5.06 update 4 (build 422) Tool: ArmCC [4d3604]
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; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\obj\timer.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\timer.d --cpu=Cortex-M0 --apcs=interwork -O3 --diag_suppress=9931 -I..\..\..\Library\CMSIS\Include -I..\..\..\Library\Device\Nuvoton\Mini58Series\Include -I..\..\..\Library\StdDriver\inc -I..\..\Template -I..\..\..\Library\StdDriver\driver -I.\RTE\_Template -ID:\Keil_v5\ARM\PACK\Nuvoton\NuMicro_DFP\1.0.9\Device\Mini58\Include -ID:\Keil_v5\ARM\CMSIS\Include -D__MICROLIB -D__UVISION_VERSION=523 --omf_browse=.\obj\timer.crf ..\..\..\Library\StdDriver\src\timer.c]
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THUMB
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AREA ||i.TIMER_Close||, CODE, READONLY, ALIGN=1
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TIMER_Close PROC
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;;;70 */
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;;;71 void TIMER_Close(TIMER_T *timer)
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000000 2100 MOVS r1,#0
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;;;72 {
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;;;73 timer->CTL = 0;
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000002 6001 STR r1,[r0,#0]
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;;;74 timer->EXTCTL = 0;
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000004 6141 STR r1,[r0,#0x14]
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;;;75
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;;;76 }
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000006 4770 BX lr
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;;;77
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ENDP
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AREA ||i.TIMER_Delay||, CODE, READONLY, ALIGN=2
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TIMER_Delay PROC
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;;;85 */
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;;;86 void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec)
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000000 b5f3 PUSH {r0,r1,r4-r7,lr}
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;;;87 {
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000002 b081 SUB sp,sp,#4
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000004 4606 MOV r6,r0
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;;;88 uint32_t u32Clk = TIMER_GetModuleClock(timer);
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000006 f7fffffe BL TIMER_GetModuleClock
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00000a 4604 MOV r4,r0
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;;;89 uint32_t u32Prescale = 0, delay = SystemCoreClock / u32Clk;
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00000c 4601 MOV r1,r0
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00000e 4823 LDR r0,|L2.156|
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000010 2700 MOVS r7,#0
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000012 6800 LDR r0,[r0,#0] ; SystemCoreClock
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000014 f7fffffe BL __aeabi_uidivmod
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000018 4605 MOV r5,r0
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;;;90 float fCmpr;
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;;;91
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;;;92 // Clear current timer configuration
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;;;93 timer->CTL = 0;
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00001a 2000 MOVS r0,#0
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00001c 6030 STR r0,[r6,#0]
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;;;94 timer->EXTCTL = 0;
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00001e 6170 STR r0,[r6,#0x14]
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;;;95
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;;;96 if(u32Clk == 10000) { // min delay is 100us if timer clock source is LIRC 10k
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000020 481f LDR r0,|L2.160|
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000022 4284 CMP r4,r0
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000024 d108 BNE |L2.56|
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;;;97 u32Usec = ((u32Usec + 99) / 100) * 100;
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000026 9802 LDR r0,[sp,#8]
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000028 2164 MOVS r1,#0x64
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00002a 3063 ADDS r0,r0,#0x63
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00002c f7fffffe BL __aeabi_uidivmod
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000030 2164 MOVS r1,#0x64
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000032 4348 MULS r0,r1,r0
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000034 9002 STR r0,[sp,#8]
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000036 e014 B |L2.98|
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|L2.56|
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;;;98 } else { // 10 usec every step
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;;;99 u32Usec = ((u32Usec + 9) / 10) * 10;
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000038 9802 LDR r0,[sp,#8]
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00003a 210a MOVS r1,#0xa
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00003c 3009 ADDS r0,r0,#9
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00003e f7fffffe BL __aeabi_uidivmod
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000042 210a MOVS r1,#0xa
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000044 4348 MULS r0,r1,r0
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;;;100 }
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;;;101
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;;;102 if(u32Clk >= 0x2000000) {
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000046 9002 STR r0,[sp,#8]
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000048 2001 MOVS r0,#1
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00004a 0640 LSLS r0,r0,#25
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00004c 4284 CMP r4,r0
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00004e d302 BCC |L2.86|
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;;;103 u32Prescale = 3; // real prescaler value is 4
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000050 2703 MOVS r7,#3
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;;;104 u32Clk >>= 2;
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000052 08a4 LSRS r4,r4,#2
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000054 e005 B |L2.98|
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|L2.86|
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;;;105 } else if(u32Clk >= 0x1000000) {
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000056 2001 MOVS r0,#1
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000058 0600 LSLS r0,r0,#24
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00005a 4284 CMP r4,r0
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00005c d301 BCC |L2.98|
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;;;106 u32Prescale = 1; // real prescaler value is 2
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00005e 2701 MOVS r7,#1
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;;;107 u32Clk >>= 1;
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000060 0864 LSRS r4,r4,#1
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|L2.98|
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;;;108 }
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;;;109
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;;;110 // u32Usec * u32Clk might overflow if using uint32_t
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;;;111 fCmpr = ((float)u32Usec * (float)u32Clk) / 1000000.0;
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000062 4620 MOV r0,r4
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000064 f7fffffe BL __aeabi_ui2f
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000068 4604 MOV r4,r0
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00006a 9802 LDR r0,[sp,#8]
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00006c f7fffffe BL __aeabi_ui2f
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000070 4621 MOV r1,r4
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000072 f7fffffe BL __aeabi_fmul
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000076 490b LDR r1,|L2.164|
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000078 f7fffffe BL __aeabi_fdiv
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;;;112
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;;;113 timer->CMP = (uint32_t)fCmpr;
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00007c f7fffffe BL __aeabi_f2uiz
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000080 6070 STR r0,[r6,#4]
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;;;114 timer->CTL = TIMER_CTL_CNTEN_Msk | u32Prescale; // one shot mode
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000082 2001 MOVS r0,#1
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000084 0780 LSLS r0,r0,#30
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000086 4307 ORRS r7,r7,r0
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000088 6037 STR r7,[r6,#0]
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;;;115
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;;;116 // When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it.
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;;;117 // And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag.
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;;;118 for(; delay > 0; delay--) {
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00008a 2d00 CMP r5,#0
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00008c d002 BEQ |L2.148|
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|L2.142|
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;;;119 __NOP();
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00008e bf00 NOP
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000090 1e6d SUBS r5,r5,#1
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000092 d1fc BNE |L2.142|
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|L2.148|
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;;;120 }
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;;;121
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;;;122 while(timer->CTL & TIMER_CTL_ACTSTS_Msk);
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000094 6830 LDR r0,[r6,#0]
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000096 0180 LSLS r0,r0,#6
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000098 d4fc BMI |L2.148|
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;;;123
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;;;124 }
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00009a bdfe POP {r1-r7,pc}
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;;;125
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ENDP
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|L2.156|
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DCD SystemCoreClock
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|L2.160|
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DCD 0x00002710
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|L2.164|
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DCD 0x49742400
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AREA ||i.TIMER_DisableCapture||, CODE, READONLY, ALIGN=1
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TIMER_DisableCapture PROC
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;;;154 */
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;;;155 void TIMER_DisableCapture(TIMER_T *timer)
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000000 6941 LDR r1,[r0,#0x14]
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;;;156 {
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;;;157 timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk;
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000002 2208 MOVS r2,#8
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000004 4391 BICS r1,r1,r2
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000006 6141 STR r1,[r0,#0x14]
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;;;158
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;;;159 }
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000008 4770 BX lr
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;;;160
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ENDP
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AREA ||i.TIMER_DisableEventCounter||, CODE, READONLY, ALIGN=1
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TIMER_DisableEventCounter PROC
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;;;180 */
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;;;181 void TIMER_DisableEventCounter(TIMER_T *timer)
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000000 6801 LDR r1,[r0,#0]
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;;;182 {
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;;;183 timer->CTL &= ~TIMER_CTL_EXTCNTEN_Msk;
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000002 2201 MOVS r2,#1
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000004 0612 LSLS r2,r2,#24
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000006 4391 BICS r1,r1,r2
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000008 6001 STR r1,[r0,#0]
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;;;184 }
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00000a 4770 BX lr
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;;;185
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ENDP
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AREA ||i.TIMER_EnableCapture||, CODE, READONLY, ALIGN=1
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TIMER_EnableCapture PROC
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;;;140 */
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;;;141 void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge)
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000000 b510 PUSH {r4,lr}
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;;;142 {
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;;;143
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;;;144 timer->EXTCTL = (timer->EXTCTL & ~(TIMER_EXTCTL_CAPSEL_Msk |
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000002 6943 LDR r3,[r0,#0x14]
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000004 24ff MOVS r4,#0xff
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000006 3417 ADDS r4,r4,#0x17
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000008 43a3 BICS r3,r3,r4
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00000a 430b ORRS r3,r3,r1
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00000c 4313 ORRS r3,r3,r2
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00000e 2108 MOVS r1,#8
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000010 430b ORRS r3,r3,r1
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000012 6143 STR r3,[r0,#0x14]
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;;;145 TIMER_EXTCTL_CAPFUNCS_Msk |
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;;;146 TIMER_EXTCTL_CAPEDGE_Msk)) |
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;;;147 u32CapMode | u32Edge | TIMER_EXTCTL_CAPEN_Msk;
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;;;148 }
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000014 bd10 POP {r4,pc}
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;;;149
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ENDP
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AREA ||i.TIMER_EnableEventCounter||, CODE, READONLY, ALIGN=1
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TIMER_EnableEventCounter PROC
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;;;169 */
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;;;170 void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge)
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000000 6942 LDR r2,[r0,#0x14]
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;;;171 {
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;;;172 timer->EXTCTL = (timer->EXTCTL & ~TIMER_EXTCTL_CNTPHASE_Msk) | u32Edge;
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000002 0852 LSRS r2,r2,#1
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000004 0052 LSLS r2,r2,#1
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000006 430a ORRS r2,r2,r1
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000008 6142 STR r2,[r0,#0x14]
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;;;173 timer->CTL |= TIMER_CTL_EXTCNTEN_Msk;
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00000a 6801 LDR r1,[r0,#0]
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00000c 2201 MOVS r2,#1
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00000e 0612 LSLS r2,r2,#24
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000010 4311 ORRS r1,r1,r2
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000012 6001 STR r1,[r0,#0]
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;;;174 }
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000014 4770 BX lr
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;;;175
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ENDP
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AREA ||i.TIMER_GetModuleClock||, CODE, READONLY, ALIGN=2
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TIMER_GetModuleClock PROC
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;;;191 */
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;;;192 uint32_t TIMER_GetModuleClock(TIMER_T *timer)
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000000 4a0f LDR r2,|L7.64|
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;;;193 {
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;;;194 uint32_t u32Src;
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;;;195 if(timer == TIMER0)
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;;;196 u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0SEL_Msk) >> CLK_CLKSEL1_TMR0SEL_Pos;
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000002 4910 LDR r1,|L7.68|
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000004 4290 CMP r0,r2 ;195
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;;;197 else
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;;;198 u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1SEL_Msk) >> CLK_CLKSEL1_TMR1SEL_Pos;
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000006 6948 LDR r0,[r1,#0x14]
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000008 d101 BNE |L7.14|
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;;;199
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;;;200 if(u32Src == 0)
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;;;201 return((CLK->PWRCTL & CLK_PWRCTL_XTLEN_Msk) == 1 ? __XTAL12M : __XTAL32K);
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;;;202 else if(u32Src == 1)
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;;;203 return __IRC10K;
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;;;204 else if(u32Src == 2)
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;;;205 return SystemCoreClock;
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;;;206 else
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;;;207 return __HSI;
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;;;208
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;;;209 }
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00000a 0a00 LSRS r0,r0,#8
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00000c e000 B |L7.16|
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|L7.14|
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00000e 0b00 LSRS r0,r0,#12
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|L7.16|
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000010 0740 LSLS r0,r0,#29
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000012 0f40 LSRS r0,r0,#29
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000014 d006 BEQ |L7.36|
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000016 2801 CMP r0,#1 ;202
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000018 d00e BEQ |L7.56|
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00001a 2802 CMP r0,#2 ;204
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00001c d00e BEQ |L7.60|
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00001e 480a LDR r0,|L7.72|
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|L7.32|
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000020 6800 LDR r0,[r0,#0] ;207 ; __HSI
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000022 4770 BX lr
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|L7.36|
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000024 6808 LDR r0,[r1,#0] ;201
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000026 0780 LSLS r0,r0,#30 ;201
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000028 0f80 LSRS r0,r0,#30 ;201
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00002a 2801 CMP r0,#1 ;201
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00002c d002 BEQ |L7.52|
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00002e 2001 MOVS r0,#1 ;201
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000030 03c0 LSLS r0,r0,#15 ;201
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000032 4770 BX lr
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|L7.52|
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000034 4805 LDR r0,|L7.76|
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000036 4770 BX lr
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|L7.56|
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000038 4805 LDR r0,|L7.80|
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00003a 4770 BX lr
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|L7.60|
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00003c 4805 LDR r0,|L7.84|
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00003e e7ef B |L7.32|
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;;;210
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ENDP
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|L7.64|
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DCD 0x40010000
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|L7.68|
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DCD 0x50000200
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|L7.72|
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DCD __HSI
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|L7.76|
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DCD 0x00b71b00
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|L7.80|
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DCD 0x00002710
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|L7.84|
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DCD SystemCoreClock
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AREA ||i.TIMER_Open||, CODE, READONLY, ALIGN=1
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TIMER_Open PROC
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;;;40 */
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;;;41 uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq)
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000000 b5f8 PUSH {r3-r7,lr}
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;;;42 {
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000002 4613 MOV r3,r2
|
||
|
|
000004 460f MOV r7,r1
|
||
|
|
000006 4606 MOV r6,r0
|
||
|
|
;;;43 uint32_t u32Clk = TIMER_GetModuleClock(timer);
|
||
|
|
000008 f7fffffe BL TIMER_GetModuleClock
|
||
|
|
00000c 4604 MOV r4,r0
|
||
|
|
;;;44 uint32_t u32Cmpr = 0, u32Prescale = 0;
|
||
|
|
00000e 2500 MOVS r5,#0
|
||
|
|
;;;45
|
||
|
|
;;;46 // Fastest possible timer working freq is u32Clk / 2. While cmpr = 2, pre-scale = 0
|
||
|
|
;;;47 if(u32Freq > (u32Clk / 2)) {
|
||
|
|
000010 0840 LSRS r0,r0,#1
|
||
|
|
000012 4298 CMP r0,r3
|
||
|
|
000014 d201 BCS |L8.26|
|
||
|
|
;;;48 u32Cmpr = 2;
|
||
|
|
000016 2002 MOVS r0,#2
|
||
|
|
000018 e010 B |L8.60|
|
||
|
|
|L8.26|
|
||
|
|
;;;49 } else {
|
||
|
|
;;;50 if(u32Clk >= 0x2000000) {
|
||
|
|
00001a 2101 MOVS r1,#1
|
||
|
|
00001c 0649 LSLS r1,r1,#25
|
||
|
|
00001e 428c CMP r4,r1
|
||
|
|
000020 d302 BCC |L8.40|
|
||
|
|
;;;51 u32Prescale = 3; // real prescaler value is 4
|
||
|
|
000022 2503 MOVS r5,#3
|
||
|
|
;;;52 u32Clk >>= 2;
|
||
|
|
000024 08a4 LSRS r4,r4,#2
|
||
|
|
000026 e005 B |L8.52|
|
||
|
|
|L8.40|
|
||
|
|
;;;53 } else if(u32Clk >= 0x1000000) {
|
||
|
|
000028 2101 MOVS r1,#1
|
||
|
|
00002a 0609 LSLS r1,r1,#24
|
||
|
|
00002c 428c CMP r4,r1
|
||
|
|
00002e d301 BCC |L8.52|
|
||
|
|
;;;54 u32Prescale = 1; // real prescaler value is 2
|
||
|
|
000030 2501 MOVS r5,#1
|
||
|
|
;;;55 u32Clk >>= 1;
|
||
|
|
000032 4604 MOV r4,r0
|
||
|
|
|L8.52|
|
||
|
|
;;;56 }
|
||
|
|
;;;57 u32Cmpr = u32Clk / u32Freq;
|
||
|
|
000034 4619 MOV r1,r3
|
||
|
|
000036 4620 MOV r0,r4
|
||
|
|
000038 f7fffffe BL __aeabi_uidivmod
|
||
|
|
|L8.60|
|
||
|
|
;;;58 }
|
||
|
|
;;;59
|
||
|
|
;;;60 timer->CTL = u32Mode | u32Prescale;
|
||
|
|
00003c 432f ORRS r7,r7,r5
|
||
|
|
00003e 6037 STR r7,[r6,#0]
|
||
|
|
;;;61 timer->CMP = u32Cmpr;
|
||
|
|
000040 6070 STR r0,[r6,#4]
|
||
|
|
000042 1c6d ADDS r5,r5,#1
|
||
|
|
;;;62
|
||
|
|
;;;63 return(u32Clk / (u32Cmpr * (u32Prescale + 1)));
|
||
|
|
000044 4368 MULS r0,r5,r0
|
||
|
|
000046 4601 MOV r1,r0
|
||
|
|
000048 4620 MOV r0,r4
|
||
|
|
00004a f7fffffe BL __aeabi_uidivmod
|
||
|
|
;;;64 }
|
||
|
|
00004e bdf8 POP {r3-r7,pc}
|
||
|
|
;;;65
|
||
|
|
ENDP
|
||
|
|
|
||
|
|
|
||
|
|
;*** Start embedded assembler ***
|
||
|
|
|
||
|
|
#line 1 "..\\..\\..\\Library\\StdDriver\\src\\timer.c"
|
||
|
|
AREA ||.rev16_text||, CODE
|
||
|
|
THUMB
|
||
|
|
EXPORT |__asm___7_timer_c_5bec749a____REV16|
|
||
|
|
#line 388 "..\\..\\..\\Library\\CMSIS\\Include\\cmsis_armcc.h"
|
||
|
|
|__asm___7_timer_c_5bec749a____REV16| PROC
|
||
|
|
#line 389
|
||
|
|
|
||
|
|
rev16 r0, r0
|
||
|
|
bx lr
|
||
|
|
ENDP
|
||
|
|
AREA ||.revsh_text||, CODE
|
||
|
|
THUMB
|
||
|
|
EXPORT |__asm___7_timer_c_5bec749a____REVSH|
|
||
|
|
#line 402
|
||
|
|
|__asm___7_timer_c_5bec749a____REVSH| PROC
|
||
|
|
#line 403
|
||
|
|
|
||
|
|
revsh r0, r0
|
||
|
|
bx lr
|
||
|
|
ENDP
|
||
|
|
|
||
|
|
;*** End embedded assembler ***
|